JP2003218275A - Packaging method for wafer class integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide the packaging method of a wafer class integrated circuit device capable of maintaining the perfectness of the wafer by providing a hold space to the thermal expansion of a buffer layer at the time of perfectly baking the buffer layer, by operating precut before perfectly hardening the buffer layer to reduce any stress to be imposed on the wafer at the time of thermally expanding the buffer layer. <P>SOLUTION: A semiconductor wafer where a plurality of independently existing chip units are formed is provided and pre-cured, and the buffer layer is temporarily imperfectly baked so as to be imperfectly hardened, and the buffer layer is slightly put into a stable state. Then, cut edges are formed at the corresponding positions of each circuit layout unit boundary of the buffer layer, by operating precut so that a gap in which any buffer layer is not included can be arranged between the two adjacent circuit layout units. Then, the wafer is post-cured, the buffer layer is perfectly backed so as to be perfectly hardened, and the wafer is divided with the buffer into a plurality of independently operating circuit layout units so that an integrated circuit device can be configured. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a type of wafer class integrated circuit device packaging method, and more particularly, to packaging of the integrated circuit device according to the traditional wafer process and BGA packaging technology to completely eliminate extra special wafers. The present invention relates to a method for packaging a wafer class integrated circuit device, which has advantages of being smaller than the same package volume as an integrated circuit device manufactured by a wafer level package and having a thinner thickness without requiring any process.

[0002]

2. Description of the Related Art In a package of an integrated circuit device (IC device), in addition to a conventional lead frame, an integrated circuit chip (IC chip) is used as an interface for signal connection with an external environment such as a board or a mother board. There is a BGA package in which a metal ball, for example, a solder ball serves as a medium for electrical connection. However, both the known lead frame package and BGA package have a drawback that the package device size is relatively large, and the width-to-chip width ratio of the package device is (Package / Chip R).
aio) is at least 1.6, thus forming a lot of wasted space and for the demanding electronics industry,
It was not always possible to meet the demand for miniaturization.

For this reason, the package / chip ratio of the integrated circuit device has been lowered to 1.2 by the so-called chip scale package (CSP) technology currently developed by the semiconductor industry. Further, the trader uses the so-called wafer class packaging technology, which integrates the packaging process into the wafer process, and makes the size of the integrated circuit device almost the same as the size of the original chip.
The p Ratio is increased to close to 1, significantly preventing the wasted space of the traditional Package / Chip Ratio.

A wafer class integrated circuit device packaging apparatus 1 shown in FIG. 1 includes a plurality of circuit layout units (not shown) which have already completed a semiconductor pre-process and can exist independently of each other. On the working surface of the wafer 11 of the packaging device 1 of the circuit device, the patterned metal layer 13 already formed, some bonding pads 16 (generally aluminum pads), some metal posts 1
7 (usually a copper pillar) and resin layers 12a and 12b, and a solder ball pad 14 which is separately extended from the circuit layout on the wafer 11 is used to bond the solder balls 15. Finally, the solder balls 15 of the package device 1 of the wafer class integrated circuit device are soldered to the substrate (referred to as SMT process or on-board step).

Then, the entire package device 1 of the wafer class integrated circuit device is separated, and the wafer 11 is divided into independent circuit layout units. Before the wafer 11 is separated, it is cured by an appropriate baking step, and at this time, the resin layer 12b of the buffer layer has a coefficient of thermal expansion (C
efficient of Thermal Exp
Since the thermal expansion coefficient (CTE) is significantly different from the thermal expansion coefficient of the wafer 11, the wafer 11 is often deformed due to excessive stress due to the difference in thermal expansion state during the baking process, which causes severe damage to the wafer 11. However, the phenomenon of damage may occur, which makes it impossible to effectively increase the yield of products.

However, in general, when soldering the package device 1 of the wafer class integrated circuit device to the substrate (SMT process) in the industry, the phenomenon of damage of the wafer 11 due to the difference between the thermal expansion coefficient of the buffer layer and the thermal expansion coefficient of the substrate is caused. In order to prevent this, the design of the buffer layer is devised to increase the product yield, but it is not known that the phenomenon of wafer 11 damage occurs even in the pre-baking process. This phenomenon becomes more severe as the wafer size is increased from 8 inches to 12 inches and the number of designed chip units is greatly increased. Therefore, the present invention provides a novel wafer class integrated circuit device packaging method and solves the above-mentioned problems.

[0007]

SUMMARY OF THE INVENTION The main object of the present invention is to provide a kind of wafer class integrated circuit device packaging method. According to the method of the present invention, the buffer layer is heated when the wafer is baked. Even if there is a considerable difference between the coefficient of thermal expansion and the coefficient of thermal expansion of the wafer, the wafer will not be deformed due to excessive stress due to the difference in coefficient of thermal expansion, and this will effectively increase the product yield, but the package The cost and required technology need not be relatively high.

Another object of the present invention is to provide a method of packaging a wafer class integrated circuit device, wherein according to the method of the present invention, precutting is performed before baking and two adjacent circuit layouts are provided. There is a gap that does not include the buffer layer between the units, so that the reserve space is subjected to thermal expansion of the buffer layer when completely baked,
That is, the stress received by the wafer during thermal expansion can be reduced, and the integrity of the wafer can be maintained.

[0009]

According to a first aspect of the present invention, there is provided a method of packaging a wafer class integrated circuit device, comprising: a. Providing a semiconductor wafer in which a plurality of circuit layout units that can exist independently are formed and a buffer layer covers the wafer. B. Curing with precure, c. Forming a cut by pre-cutting at a position corresponding to the boundary of each circuit layout unit of the buffer layer, whereby a gap not containing the buffer layer is present between each two adjacent circuit layout units, d. Post cure step, e. A method of packaging a wafer class integrated circuit device, comprising the steps of cutting a semiconductor wafer to separate a plurality of circuit layout units into independent integrated circuit devices, and the above steps. Claim 2
2. The invention of claim 1 is characterized in that a plurality of bonding pads are provided at predetermined positions of each circuit layout unit of the semiconductor wafer to form an electrical contact for connecting the circuit layout unit and the outside world. The wafer class integrated circuit device packaging method of The invention of claim 3 provides the method of packaging a wafer class integrated circuit device according to claim 1, wherein the buffer layer is a resin layer. The invention according to claim 4 is the method for packaging a wafer class integrated circuit device according to claim 1, characterized in that a plurality of copper pillars are provided in the buffer layer. The invention of claim 5 further comprises, after the step of e, e1. The method of packaging a wafer class integrated circuit device according to claim 1, further comprising a step of implanting a plurality of metal balls on a surface of the buffer layer on a side remote from the wafer.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION A preferred embodiment of a method for packaging a wafer class integrated circuit device of the present invention includes the following steps. That is: a. Device preparation step. In this step, a wafer manufactured by a commonly used semiconductor process is prepared. Among them, a plurality of chip units that can exist independently by a semiconductor process are already formed on the operating surface of the wafer,
Each chip unit has its own independently operated integrated circuit layout unit, each of the independent circuit layout units has a patterned metal layer formed thereon, and bonding pads are provided for electrical contact, and also covers the wafer. A buffer layer is provided. b. Precure step. In this step, the buffer layer is incompletely baked for a while at an appropriate temperature to incompletely cure it, and the buffer layer is slightly stabilized. c. Pre-cut step. In this step, a cut is formed by precutting in the buffer layer at a position corresponding to the boundary of each circuit layout unit, so that a gap not containing the buffer layer exists between each two adjacent circuit layout units. d. Post cure step. The buffer layer is completely baked at an appropriate temperature to completely cure the buffer layer. e. Metal ball implantation step. A plurality of metal balls are implanted on the surface of the buffer layer remote from the wafer and bonded to the solder ball pads. f. Separation step. The wafer is cut together with the buffer layer to separate a plurality of circuit layout units into an independently operated integrated circuit device.

The present invention proceeds with a pre-cut step prior to full cure to create a buffer layer-free gap between each two adjacent circuit layout units so that during a complete bake, the retention space is heated to the buffer layer heat. Subject to expansion to reduce stress on the wafer during thermal expansion and maintain wafer integrity.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention is applied to a packaging device for a wafer class integrated circuit device, and avoids the problems that occur during the packaging process without requiring a completely extra special wafer process, and heats the buffer layer and the wafer. It is possible to prevent a damage phenomenon that may occur due to a difference in expansion coefficient.

2 to 5 show a preferred embodiment of the packaging device for the wafer class integrated circuit device of the present invention, those skilled in the art of integrated circuit packaging will understand the present invention based on the description of the present invention. The invention may be implemented. It should be noted that any modification or alteration of details that can be easily made based on the present invention belongs to the scope of claims of the present invention.

The wafer class integrated circuit device packaging method of the present invention includes the following steps. (1) Device preparation step. See FIG. In this step, a wafer 101 manufactured by a commonly used semiconductor process is prepared. Among them, a plurality of chip units (Chips) that can exist independently on a working surface (Active Side) of the wafer 101 by a semiconductor process.
, Each of the chip units has an independently operating integrated circuit layout unit (IC), and each of the independent circuit layout units has a single-layer or multi-layer patterned metal layer 102a formed thereon. A plurality of bonding pads 104 are provided at predetermined positions to serve as electrical contacts (only one bonding pad is shown in the figure) for connecting the circuit layout unit and the outside world.
Is usually an aluminum pad, the buffer layer 103 covers the wafer 101, the buffer layer 103 is a resin layer (resin), an epoxy resin or other non-conductive material, and the metal is formed on the buffer layer 103. Layer 10
2b and a plurality of metal columns 105 are defined.
Reference numeral 05 may be a copper post. In addition to the metal pillar 105, a solder ball pad 106 extended from the metal layer 102b is provided. (2) Pre-cure step. In this step, the buffer layer 103 is incompletely baked at an appropriate temperature for a while to be incompletely cured, and the buffer layer 103 is slightly stabilized. (3) Pre-cut step. This step is the focus of the present invention, and the buffer layer 1
03, a cut is formed by pre-cutting at a position corresponding to the boundary of each circuit layout unit, whereby a gap 110 (gap) not including the buffer layer 103 exists between each two adjacent circuit layout units. Among them, the cut edge slightly extends into the boundary of each circuit layout unit, as shown in FIG. (4) Post-cure step.
The buffer layer 103 is completely baked at an appropriate temperature to completely cure the buffer layer 103. At this time, the gap 110 (ga) that does not include the buffer layer 103 is already formed between each two adjacent circuit layout units by the above-mentioned steps.
Since p) is formed, the storage space is subjected to thermal expansion of the buffer layer 103 during the complete baking, that is, the stress applied to the wafer 101 during the thermal expansion is reduced, and the integrity of the wafer 101 is maintained. (5) Step of implanting a metal ball. As shown in FIG. 4, a plurality of metal balls 107 are embedded in the surface of the buffer layer 103 on the side away from the chip 101, and the metal balls 107 and the solder ball pads 106 are bonded.
The metal balls 107 are preferably solder balls. (6) Separation step. Figure 5
2, the wafer 101 is cut together with the buffer layer 103, and a plurality of circuit layout units (chip units) are separated to form an integrated circuit device that operates independently.

To facilitate understanding of the method of the present invention, FIG.
The flowchart of the packaging method of the wafer class integrated circuit device of the preferred embodiment of the present invention is shown in FIG. The flow covers the following: (301) Providing a wafer manufactured in a semiconductor process. A plurality of chip units (Chips) that can exist independently by a semiconductor process are already formed on the operating surface of the wafer, and each chip unit has an independently operating integrated circuit layout unit (IC). And a buffer layer overlies the wafer. (302) Pre-cure step.
In this step, the buffer layer is incompletely baked for a while at an appropriate temperature to incompletely cure it, and the buffer layer is slightly stabilized. (303) Perform a pre-cut step. Pre-cut cuts are formed in the buffer layer at positions corresponding to the boundaries of each circuit layout unit, so that a gap (gap) not containing the buffer layer exists between each two adjacent circuit layout units. (304) Post-cure step (post-cur)
e). The buffer layer is fully baked at a suitable temperature to fully cure the buffer layer and the presence of the buffer layer-free gap between each two adjacent circuit layout units causes the retention space to undergo thermal expansion of the buffer layer, i.e. Reduces stress on the wafer during thermal expansion and maintains wafer integrity. (305) Separation step.
The wafer is cut together with the buffer layer, and a plurality of circuit layout units (chip units) are separated to form an independently operated integrated circuit device. Of course, there is a step of implanting a metal ball, but this is not the focus of the present invention, so the description thereof will be omitted.

[0016]

The present invention has the following advantages over known techniques. (1) The packaging method of the wafer class integrated circuit device of the present invention is obviously not complicated in process, and can be perfectly implemented by those skilled in the field of this technology. (2) According to the present invention, when a wafer is baked, it is possible to prevent deformation due to excessive stress caused by the difference between the thermal expansion coefficient of the buffer layer and the thermal expansion coefficient of the wafer, and it is possible to effectively increase the yield of products.

The above is a description of specific examples of the present invention and does not limit the scope of the present invention, and any modifications or alterations in details that can be made based on the present invention are within the scope of the present invention. Shall belong.

[Brief description of drawings]

FIG. 1 is a view showing a package device of a known wafer class integrated circuit device.

FIG. 2 is a step display diagram of a packaging method for a wafer class integrated circuit device according to the present invention.

FIG. 3 is a step display diagram of a packaging method of a wafer class integrated circuit device of the present invention.

FIG. 4 is a step display diagram of a packaging method for a wafer class integrated circuit device according to the present invention.

FIG. 5 is a step display diagram of a packaging method for a wafer class integrated circuit device of the present invention.

FIG. 6 is a manufacturing flowchart of the wafer class integrated circuit device packaging method according to the present invention.

[Explanation of symbols]

1 Wafer-class integrated circuit device package equipment 11, 101 wafers 12a, 12b resin layer 13, 102a, 102b Metal layer 14, 106 Solder ball pad 15 Solder balls 16, 104 Bonding pad 17,105 Metal pillar 103 buffer layer 107 metal balls 110 gap

Claims (5)

[Claims] 1. A method of packaging a wafer class integrated circuit device, comprising: a. Providing a semiconductor wafer in which a plurality of circuit layout units that can exist independently are formed and a buffer layer covers the wafer. B. Curing with precure, c. Forming a cut by pre-cutting at a position corresponding to the boundary of each circuit layout unit of the buffer layer, whereby a gap not containing the buffer layer is present between each two adjacent circuit layout units, d. Post cure step, e. A method for packaging a wafer class integrated circuit device, comprising: a step of cutting a semiconductor wafer to separate a plurality of circuit layout units into independent integrated circuit devices; and the above steps. 2. A plurality of bonding pads are provided at predetermined positions of each circuit layout unit of the semiconductor wafer to serve as electrical contacts for connecting the circuit layout unit and the outside world. A method for packaging a wafer class integrated circuit device according to claim 1. 3. The method of packaging a wafer class integrated circuit device according to claim 1, wherein the buffer layer is a resin layer. 4. The method of packaging a wafer class integrated circuit device according to claim 1, wherein the buffer layer is provided with a plurality of copper pillars. 5. After the step of e, further comprising e1. The method for packaging a wafer class integrated circuit device according to claim 1, further comprising: implanting a plurality of metal balls on a surface of the buffer layer on a side remote from the wafer.