JP2003216102A - Driving method of storage driving type display device and storage driving type display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To increase the numerical aperture of pixels, to reduce electric power consumption and to prevent the occurrence of deterioration in the parts while conducting image display. <P>SOLUTION: A display is provided with a light emitting panel 1 which is provided with pixels P(1, 1) to P(2, 2),.... The pixels are provided with TFTs 11, DG memory TFTs 12, organic EL diodes 13, address lines Y1, Y2,... which transmit address signals, data signals, a power supply voltage and a reference voltage to respective pixels, data lines X1, X2,..., power supply voltage electrodes Z and reference voltage electrodes W. Luminance data (channel states) of the light emission of each pixel stored in the DG memory TFTs 12 are erased by a data erasing operation for every pixel, luminance data are written into the DG memory TFTs 12 by the voltages of the signals being inputted into the data lines during a data writing operation and the diodes 13 made to emit light based on the luminance data stored in the TFTs 12. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage drive type display device for displaying an image using a storage drive means capable of electrically erasing and writing information, and a driving method thereof.

[0002]

2. Description of the Related Art Recently, as a new display technology replacing CRT (Cathode Ray Tube), EL (Elec
A technique for obtaining EL light emission using a troluminescence material has been studied.

Inorganic E is used as an EL material which is a fluorescent substance.
Research on the use of L materials was conducted, but after that, inorganic EL
Attention has been focused on organic EL materials having advantages not found in the above. The organic EL material has advantages over the inorganic EL material such as easy colorization and operation at a lower voltage current. Organic EL using organic EL material
An element in which a layer thin film is sandwiched between metal electrodes and a charge is injected by applying a direct current is called an organic (thin film) EL diode.
Much research has been done aiming at the realization of a flat panel display by its application.

An organic EL diode is provided in each pixel of a light emitting panel of an organic EL display, and a TFT (Thin Film Transi) is used for controlling light emission of the organic EL diode of each pixel.
stor) was provided for each pixel. Thus, conventional organic E
In the light emission control method of the L diode, a drive method in which the organic EL diode is actively controlled is mainly used in order to improve power consumption and life.

A conventional driving method for active control of an organic EL diode will be described with reference to FIG. Figure 8
It is a figure which shows the conventional light emission panel 6 of voltage control.

As shown in FIG. 8, in one pixel of the light emitting panel 6, a data line 6A for supplying a signal of an arbitrary voltage, an address line 6B as a control signal communication path, and a power supply as a power supply voltage supply path. Line 6C and a MOS (Metal Ox) with one terminal connected to the data line 6A and the gate connected to the address line 6B.
ide Semiconductor) type n-channel type TFT6D
And one terminal is connected to the power line 6C and the gate is the TFT6.
A MOS type n-channel type T connected to the other terminal of D
FT6E, an organic EL diode 6F having an anode connected to the other terminal of the TFT 6E, and an organic EL diode 6
A common ground portion 6G of each pixel connected to the F cathode is provided. Further, a capacitor 6H having one end connected to the gate of the TFT 6E and the other end connected to the common ground portion 6G is provided.

When the address line 6B is selected (address line 6B
When a high signal voltage is applied to the TFT6D,
High signal is applied to the gate of and turns on, and the data line 6A
Is transmitted to the gate of the TFT 6D, and a current according to the potential of the data line 6A flows to the common ground portion 6G through the power supply line 6C, the drain and source of the TFT 6E, and the organic EL diode 6F in order.

When the address line 6B is not selected (address line 6
When a low signal voltage is applied to B), the TFT6
A low signal is applied to the gate of D to turn it off, and the TFT6
The potential of the gate of E is stored in the capacitor 6H, and a current according to the stored potential flows to the common ground portion 6G through the power supply line 6C, the drain and source of the TFT 6E, and the organic EL diode 6F in order. In this way, the data line 6
The brightness of the organic EL diode 6G was controlled by changing the voltage of A.

A data driver for supplying a signal to the data line 6A, an address driver for supplying a signal to the address line 6B, a power source for inputting a power supply voltage to the issuing panel 6, the data driver and the address driver. And a controller for controlling the power source are provided outside the light emitting panel 6 to form a display.

[0010]

However, in the conventional organic EL diode emission control system shown in FIG.
The capacitor 6H is provided because the parasitic capacitance between the gate and the source of E is small, but a sufficiently large capacitor is required to hold the gate potential of the TFT 6E for one frame period. Diode 6F
It was difficult to increase the light emitting area. Further, even in the case of a still image, the data driver and the address driver have to be operated for each frame, which causes a problem that power consumption cannot be reduced.

Further, since a potential in one direction (a positive potential in this case) is always applied to the gate of the TFT 6E in FIG. 8, the threshold value of the TFT shifts due to long-term use and the transistor characteristic deterioration phenomenon occurs. There was also a problem that

An object of the present invention is to increase the aperture ratio of pixels, reduce power consumption, and prevent deterioration of parts in image display.

[0013]

According to a first aspect of the present invention, when a pixel is selected for each of a plurality of pixels arranged in a matrix, a control signal for controlling the luminance of light emission of the pixel is provided. The selecting means for outputting and the brightness data of the light emission are stored for a long time so as to be electrically erasable and writable in response to the control signal output from the selecting means during the selection period, and the stored brightness is stored. A light emitting panel is provided, which is provided with a memory driving unit that outputs a current input from a power source corresponding to data and a light emitting unit that emits light based on the current output from the memory driving unit. A driving method of a memory drive type display device for displaying an image, wherein during the selection period, for the selected pixel,
As the control signal, an erasing control signal for erasing the brightness data stored in the memory driving unit is generated, the selecting unit outputs the generated erasing control signal, and the memory driving unit outputs the erasing control signal. Data erasing procedure for erasing the brightness data stored therein based on the erasing control signal, and as the control signal, a light emission control signal for designating the next brightness to the light emitting means is generated, and the generation means is generated by the selecting means. A data writing procedure of causing the memory driving means to output the generated light emission control signal and writing the brightness data based on the output light emission control signal, and performing the non-selection during the non-selection period. In the pixel, the memory drive means is caused to output a current corresponding to the brightness data written in the data write procedure, and the current is generated based on the current output from the memory drive means. Executing a data reading procedure for, it becomes as characterized.

The invention described in claim 2 is characterized in that the selection and the non-selection in the feature of the invention described in claim 1 are repeatedly executed alternately.

The invention according to claim 3 is the same as claim 1 or 2.
It is characterized in that the selection in the feature of the described invention is executed when the light emission control signal is changed.

According to a fourth aspect of the present invention, the light emission control signal according to the features of the first, second or third invention is a signal for designating an arbitrary luminance of the light emitting means, and the luminance data is It is characterized in that it is data for designating arbitrary brightness.

The invention according to claim 5 is the invention as defined in claims 1, 2 and
After the data writing procedure according to the features of the invention described in 3 or 4, if the next data writing procedure can be continuously executed, the execution of the data erasing procedure executed before the next data writing procedure is omitted. Will be a feature.

According to a sixth aspect of the present invention, in a plurality of pixels arranged in a matrix, control signal generating means for generating a control signal for controlling the luminance of light emission of each pixel, and selection for designating selection of the pixel A storage drive type display device provided with a selection signal generating means for generating a signal and a light emitting panel comprising the plurality of pixels, and displaying an image by light emission of each pixel, wherein each pixel is the selection signal generating means. A selection unit that outputs the control signal output from the control signal generation unit during the selection period of the own pixel by the selection signal output from the selection signal, and a control signal output from the selection unit during the selection period. Correspondingly, a storage driving unit that stores the emission luminance data for a long time so as to be electrically erasable and writable, and outputs a current based on the stored luminance data during a non-selected period, Light emitting means for emitting light based on the output current from the storage drive means, made as characterized by being provided with.

According to a seventh aspect of the present invention, the selection signal generating means in the features of the sixth aspect alternately and repeatedly generates the selection signal indicating the selection and the selection signal indicating the non-selection. However, the control signal generating means sequentially generates, as the control signal, an erase control signal for erasing the brightness data and a light emission signal for writing the brightness data during the selection period.

The invention according to claim 8 is the invention according to claim 6 or 7.
The selection signal generating means in the feature of the described invention is characterized in that the selection signal generating means generates the selection signal indicating the selection when the luminance of the light emission of the light emitting means of each pixel is changed.

According to a ninth aspect of the present invention, the control signal generating means in the features of the sixth, seventh or eighth aspect of the present invention emits any light of the light emitting means of each pixel during the selection period. It is characterized in that a light emission control signal for designating the brightness is generated, and the storage driving means stores the brightness data for designating the brightness of arbitrary light emission corresponding to the light emission control signal.

The invention according to claim 10 is the invention according to claim 6,
In each of the pixels according to the features of the invention described in 7, 8, or 9, the selection unit is provided with a first gate and first and second terminals, and the first gate serves as the selection signal generation unit. The first terminal is connected to the control signal generating means, and the first signal is input in response to the selection signal input to the first gate and the control signal input to the first terminal. A TFT for forming a channel between a terminal and a second terminal, wherein the memory driving means is provided with second and third gates and third and fourth terminals, and the second gate is the TFT. Connected to the second terminal of
The third gate and the third terminal are connected to a power source that supplies a predetermined voltage, the fourth terminal is connected to the light emitting means, and the third gate and the third terminal correspond to a control signal input to the second gate. Is a DG memory TFT that stores the brightness data and that forms a channel between the third terminal and the fourth terminal in correspondence with the stored brightness data.

According to an eleventh aspect of the present invention, in the memory drive type display device according to the tenth aspect, the DG memory T is used.
The second and third gates of the FT are arranged to overlap each other in the vertical direction, and the DG memory TFT includes the second gate.
And an insulating layer in which a trap for capturing electrons is formed between the third gate and the third gate.

According to the first or sixth aspect of the invention, the pixel is selected by the selection signal input to the selection means, and the storage drive is performed by the control signal generated through the selection means during the selection period. The brightness data on the means is erased, written and stored, and the pixel is deselected by the selection signal input to the selection means to the effect that the control signal is not input to the storage drive means but stored in the storage drive means. The electric current corresponding to the brightness data being input is input to the memory driving means to control the light emission of the light emitting means.

Therefore, according to the invention described in claim 1 or 6, the brightness data of the light emission of each pixel can be erased and written by the storage driving means for a long time without performing the refresh, and the data is stored. Since the pixels are always made to emit light corresponding to the brightness data, the power consumption can be reduced.
Further, since only the selection means and the storage control means are provided as the switching member of the pixel, the area ratio of the light emitting means for each pixel is increased, so that the area of one pixel as a whole can be made smaller and high-definition display is possible. Therefore, the power consumption can be further reduced.

According to the second or seventh aspect of the present invention, the erase control signal and the light emission control signal are repeatedly input to the memory drive means, and the erase and write of the brightness data on the memory drive means are repeatedly executed.

Therefore, according to the second or seventh aspect of the present invention, since the erase control signal and the light emission control signal are repeatedly input to the memory drive means, deterioration of the memory drive means due to long-time input of the same signal is prevented. You can

According to the invention of claim 3 or 8, the luminance data for the pixel having the same luminance as that of the previous selection is not erased and written, and the non-selection period is continued and the current corresponding to the same luminance data is continued. Is input to the light emitting means.

Therefore, according to the invention described in claim 3 or 8, it is not necessary to erase and write the luminance data for the pixel having the same luminance as that of the previous selection, and the control signal is generated to the pixel. Since it is not necessary, the processing load and power consumption can be reduced. In particular, when a still image is displayed, the control signal generating means for all pixels can be stopped, so that the power consumption and the processing load can be significantly reduced.

According to the invention of claim 4 or 9, the light emission control signal of an arbitrary value is output during the selection period, and the brightness data corresponding thereto is also input to the storage driving means as the data of the arbitrary value. The luminance of the light emitting means corresponding to this is also arbitrary.

Therefore, according to the invention described in claim 4 or 9, it is possible to emit light while controlling each pixel to a continuous arbitrary luminance of light emission.

According to the invention described in claim 5, when the data writing procedure for different brightness can be continuously performed, the data erasing procedure performed after the previous data writing procedure is omitted and the next data writing procedure is performed. Run.

Therefore, according to the invention of claim 5,
Since the data erasing procedure is omitted when performing the data writing procedure that does not need to execute the data erasing procedure, it is possible to reduce the load of executing the data erasing procedure and the power consumption thereof.

According to the tenth aspect of the invention, when the selection signal whose selection signal voltage is higher than that of the control signal is applied to the first gate, the TFT is selected, and the first terminal and the second terminal are selected. A control signal is input to the first gate of the DG memory TFT through the terminal, and when the control signal is high (erasing control signal), electrons for channel formation between the third terminal and the fourth terminal are generated. When the control signal is low (light emission control signal) and the current from the power source is supplied to the light emitting means through the third terminal and the fourth terminal, the channel between the third terminal and the fourth terminal is replenished. Electrons for formation are emitted, and a current from a power source corresponding to the light emission control signal is input to the light emitting means through the third terminal and the fourth terminal.

When a selection signal whose selection signal voltage is lower than that of the control signal is applied to the first gate, the TFT
Is not selected, the control signal is stopped at the first terminal and the second terminal, and the channel state (luminance data) formed between the third terminal and the fourth terminal of the DG memory TFT is stored. Correspondingly, the current from the power supply is applied to the third terminal and the fourth
Input to the light emitting means through the terminal.

Therefore, according to the tenth aspect of the invention, the selection means is the TFT, and the memory drive means is the DG memory TF.
T can be used and controlled by the voltage of the select and control signals.

According to the eleventh aspect of the invention, since the DG memory TFT has a vertical structure and an insulating layer for trapping electrons is further provided, it is not necessary to provide a separate capacitor, and space can be saved. The area per pixel can be made smaller to enable high-definition display.

[0038]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the accompanying drawings. First, the device configuration will be described with reference to FIGS. 1 and 2. FIG. 1 is a diagram showing a display α of the present embodiment, and FIG. 2 is a circuit diagram showing a configuration of the light emitting panel 1 shown in FIG.

As shown in FIG. 1, the display α includes a light emitting panel 1 for controlling the light emission for each pixel provided in a matrix of n vertically and m horizontally and displaying an image, and a horizontal line. An address driver 2 (selection signal generation means) that generates an address signal (selection signal) that controls light emission of pixels of (row) and a data signal (control signal) that controls light emission of pixels of a vertical line (column). A data driver 3 (control signal generation means) for generating, a constant power source 4 for supplying a common power source voltage to each pixel, an address driver 2, a data driver 3 and a controller 5 for controlling the constant power source 4 are provided. The controller 5 receives image information from an external device (not shown) and controls each member based on the image information.

The address driver 2 is connected to the pixels in each row of the light emitting panel 2 by arbitrary n address lines Y1 to Yn, and the data driver 3 is connected to the pixels in each column of the light emitting panel 2 as desired. Connect with m data lines X1 to Xm,
An active matrix method is employed in which each pixel in each row and each column is controlled. In addition, each pixel of the light emitting panel 2 is
It is connected to a power supply voltage electrode Z that supplies a power supply voltage Vdd from the constant power supply 4 and is also connected to a reference voltage electrode W that supplies a reference voltage Vss having a lower potential than the power supply voltage Vdd. Here, the pixels of the data line Xi and the address line Yj are referred to as the pixel P (i, j), and the light emitting panel 1 has the pixel P.
(1,1) to P (m, n) are provided.

As shown in FIG. 2, the pixel P of the light emitting panel 1 is
(1,1) is a MOS-type n-channel TFT 11 (selection means) that connects the gate to the address line Y1 from the address driver 2 and connects the data line X1 from the data driver 3 to one terminal, The other terminal of the TFT 11 is connected to the top gate 12A, and the power supply voltage electrode Z from the constant power source 4 is connected to the bottom gate 12B and the terminal 12C.
OS type n channel type DG (Double Gate) memory T
FT12 (memory driving means) and an organic EL diode 1 for connecting the terminal 12D of the DG memory TFT 12 and the anode
3 and. The cathode of each organic EL diode 13 is connected to the reference voltage electrode W.

In the pixel P (i, j) (i is an integer of 1 or more and m or less, j is an integer of 1 or more and n or less), the gate of the TFT 11 is connected to the address line Yj, and one terminal is similarly connected to the data line Xj. Connected with. The reference voltage electrode W and the power supply voltage electrode Z may be a plurality of wirings provided along the address lines Y1 to Yn and for each of the address lines Y1 to Yn. It may be a single electrode.

The DG memory TFT 12 is a conventional LSI.
It cannot have high-speed data writing or semi-permanent storage like a (Large Scale Integration) flash memory, but has sufficient characteristics for use as a pixel memory in a display like this embodiment. In particular, in this embodiment mode, electron carriers having higher mobility than holes are used.

Here, the organic EL diode 13 will be described with reference to FIG. FIG. 3 is a schematic cross-sectional view of the light emitting panel 1 shown in FIG. As shown in FIG. 3, the light emitting panel 2 is formed between a partition B and a partition B made of an insulating material such as silicon nitride for partitioning each pixel on a transparent substrate A made of a transparent insulating material such as glass or quartz. To be ITO
On the anode electrode 13A of the organic EL diode 13 made of a transparent conductive material such as (Indium Tin Oxide), the organic EL layer 13B of the organic EL diode 13 formed on the anode electrode 13A, on the partition B and the organic EL layer 13B. Cathode electrode 13C of the organic EL diode 13 formed on
Then, the sealing material C formed on the cathode electrode 13C and the sealing glass D formed on the sealing material C are sequentially provided.

In FIG. 3, the TFT 11 and the DG memory TFT 1
2, the address lines Y1 to Yn, the data lines X1 to Xm, the power supply voltage electrode Z, and the reference voltage electrode W are omitted. TF
The T11 and DG memory TFT 12 are formed under the partition wall B, for example.

The organic EL layer 13B may have, for example, a three-layer structure in which a hole transporting layer, a light emitting layer and an electron transporting layer are formed in this order from the anode electrode 13A, or a hole transporting layer and an electron are formed in this order from the anode electrode 13A. It may have a two-layer structure that serves as a light-emitting layer that also serves as a transport layer, a single-layer structure that includes a light-emitting layer, or any other layer structure.

That is, the organic EL layer 13B has a function of injecting holes and electrons, a function of transporting holes and electrons, and a function of generating excitons by recombination of holes and electrons to emit light. The organic EL layer 13B is preferably an electronically neutral organic compound, and thereby holes and electrons are injected and transported in a well-balanced manner in the organic EL layer 13B.

An electron-transporting substance may be appropriately mixed in the light-emitting layer, a hole-transporting substance may be appropriately mixed in the light-emitting layer, an electron-transporting substance and a hole-transporting substance. Substance may be appropriately mixed in the light emitting layer.

The light emitting layer of the organic EL layer 13B contains a light emitting material. A polymer material is used as the light emitting material. As polymeric materials,
Polycarbazole, polyparaphenylene, polyarylene vinylene, polythiophene, polyfluorene, polysilane, polyacetylene, polyaniline, polypyridine,
Examples thereof include polypyridine vinylene and polypyrrole. Further, as the polymer material, the above polymer material (polymer)
A polymer or copolymer of a monomer or an oligomer forming a polymer, or a polymer or copolymer of a derivative of a monomer or an oligomer, and a monomer having an oxazole (oxanediazole, triazole, diazole) or triphenylamine skeleton Examples thereof include polymers and copolymers obtained by polymerizing. Further, the monomers of these polymers include monomers and precursor polymers that form the above-mentioned compounds by applying heat, pressure, UV, electron beam or the like. Further, a non-conjugated unit that bonds these monomers may be introduced.

Specific examples of the polymer material include polypinylcarbazole, polytodecylthiophene, polyethylenedioxythiophene, modified polystyrene sulfonic acid dispersion, poly 9,9-dialkylfluorene, poly (thienylene-9). , 9-dialkylfluorene), poly (2,5-dialkylparaphenylene-thienylene), (dialkyl: R = C1 to C20), polyparaphenylenevinylene, poly (2-methoxy-5- (2'-ethyl-hexyloxy) ) -Paraphenylene vinylene), poly (2-methoxy-5- (2'-ethyl-pentyloxy))
-Paraphenylene vinylene), poly (2,5-dimethyl-paraphenylene vinylene), poly (2,5-thienylene vinylene), poly (2,5-dimethoxyparaphenylene vinylene), poly (1,4-paraphenylene) Cyanovinylene) and the like.

Further, the material is not limited to the polymer material, and a low molecular material may be used by polymer dispersion. Further, depending on the properties of the low molecular weight material, the low molecular weight material may be used by being applied in a state of being dissolved in a solvent. As the polymer for polymer-dispersing the low molecular weight material, various polymers including well-known general-purpose polymers can be used depending on the situation.

Examples of the low molecular weight light emitting material (light emitting substance or dopant) include anthracene, naphthalene, phenanthrene, pyrene, tetracene, coronene, chrysene, fluorescein, perylene, phthaloperylene, naphthaloperylene, perinone, phthaloperinone, naphthaloperinone, diphenylbutadiene, tetraphenyl. Butadiene, coumarin, oxadiazole, aldazine, bisbenzoxazoline, bisstyryl, pyrazine, oxine, aminoquinoline, imine, diphenylethylene, vinylanthracene, diaminocarbazole, pyran, thiopyran, polymethine, merocyanine, imidazole chelated oxinoid compound, etc. 4-dicyanomethylene-4H
-Pyran and 4-dicyanomethylene-4H-thiopyran, diketones, chlorin compounds and derivatives thereof can be mentioned. Specific examples of the low-molecular light emitting material include A
Examples include lq3 and quinacridone.

As the light emitting material, a polyfluorene material represented by the following formula is also used.

[Chemical 1] The polyfluorene-based material is a compound having a polydispersity of less than 5.

However, in the above formula, E is independently hydrogen, halogen, aryl or aryl substituted with a reactive group capable of chain extension or crosslinking, or a trialkylsiloxy moiety, and R 1 is each Independently C1-20 hydrocarbyl or C1-20 hydrocarbyl containing one or more S, N, O, P or Si heteroatoms, or 2
R1 is a C5-20 ring structure or a C containing at least one hetero atom of S, N or O together with the 9th carbon of the fluorene ring.
4-20 ring structure may be formed, and each R2 independently represents C1.
-20 Hydrocarbyl, C1-20 Hydrocarbyloxy, C1
-20 thioether, C1-20 hydrocarbyloxycarbonyl, C1-20 hydrocarbylcarbonyloxy, or cyano. a is each independently a number from 0 to 1 and m is a non-negative number. The light emitting material is not limited to the above.

Examples of the electron-transporting substance contained in the light-emitting layer or the electron-transporting layer include quinoline derivatives such as organometallic complexes having 8-quinolinol such as tris (8-quinolinolato) aluminum (Alq3) or its derivative as a ligand. ,
Examples thereof include an oxadiazole derivative, a perylene derivative, a pyridine derivative, a pyrimidine derivative, a quinoxaline derivative, a diphenylquinone derivative, and a nitro-substituted fluorene derivative.

The hole-transporting substance contained in the light-emitting layer or the hole-transporting layer is a tetraarylbenzidine compound (triaryldiamine or triphenyldiamine:
TPD), aromatic tertiary amine, phthalocyanines, naphthaphthalocyanines (n
aphthalocyanines), porphyrin compounds
ns), triazole, imidazole (imid
azole), imidazolone, imidazolethione, pyrazoline
e), pyrazolone, tetrahydroimidazole, oxazol
e), oxadiazole, hydrazone (hydra
zone), acylhydrazone (acylhydrazone), polyarylalkane (polyarylalkane) stilbene, butadiene, benzidine-triphenylamine, styrylamine-triphenylamine, diamine-type Triphenylamine (diamine-triphenylamine) and their derivatives (derivative), polyvinylcarbazole (p
olyvinylcarbazole), polysilane, polyethylenedioxythiophop
hen: PEDOT), polystyrene sulfonic acid (polysthyr
enesulfonate: PSS), polyaniline
It is a material selected from at least one kind or more of conductive polymer materials such as

[Chemical 2] (In the formula, n and l are non-negative integers.)
EDOT is a protective colloid such as PSS.
Materials to which a polymer obtained by dispersion polymerization according to d) is applied are also included.

The cathode electrode 13C is also formed on the partition wall B, and is provided on the light emitting panel 1 in front pixels P (1,1) to P (1,1).
A layer common to all P (m, n), and the reference voltage electrode W
Connected to. Specific examples of the cathode electrode 13C include gold, silver, copper, aluminum, indium, magnesium, calcium, barium, or alloys thereof, or compounds or mixtures containing lithium, magnesium or indium in these metals or alloys. Further, the cathode electrode 13C may have a laminated structure in which layers of various materials described above are laminated. Specifically, for example, magnesium / silver obtained by co-evaporating magnesium and silver on the organic EL layer 13B. Although a normal electrode layer such as an electrode layer can be used, the efficiency of injecting electrons into the organic EL layer is particularly good in the aluminum / lithium electrode layer as compared with electrodes made of other materials, so that the luminous efficiency and luminous brightness of the EL element are improved. And the emission life and stability of the EL element due to abnormal heat generation are further improved. Further, a laminated structure in which a high-purity barium layer and a high-purity aluminum layer are sequentially formed can be given.

The light emitting panel 1 having a laminated structure as described above
During the light emitting operation of the TFT 11 and the DG memory TFT 1.
When a forward electric field is generated between the anode electrode 13A and the cathode electrode 13C due to the switching of No. 2, holes are injected from the anode electrode 13A into the light emitting layer of the organic EL layer 13B, and the cathode electrode 13C to the organic EL layer 13B. Electrons are injected into the light emitting layer of.

Then, holes and electrons are transported to the light emitting layer of the organic EL layer 13B, excitons are generated by recombination of the holes and electrons in the light emitting layer, and photons are generated when the excitons disappear. Occurs and emits light. The generated photons are transmitted through the anode electrode 13A and the transparent substrate A in order and output.

Coloring of each color of the light emitting material of the organic EL layer 13B is performed by using each light emitting material which emits each color of red, green, blue or the like, or by mixing the light emitting material which emits white light with the fluorescent paint of each color. Done.

The organic EL layer 13B is formed by a wet method in which the above-described organic EL material is dissolved in a solvent such as ethylene to produce a solution of a light emitting material and the solution is ejected by a droplet ejecting device. It is formed by a coating method or a dry vapor deposition heating method by resistance heating vapor deposition.

Next, the operation of the DG memory TFT 12 will be described with reference to FIGS. Here, the pixel P (1,
1) will be described as a representative. FIG. 4 is a sectional view of the DG memory TFT 12 showing a data erasing operation, and FIG. 5 is a sectional view of the DG memory TFT 12 showing a data writing operation. The data is data of the luminance of light emitted from the organic EL diode 13.

First, referring to FIG. 4, a DG memory TFT
The structure of 12 will be described. On the transparent substrate A shown in FIG. 3, a bottom gate 12B, an insulating layer 12F, a semiconductor layer 12E of an amorphous silicon i-type semiconductor, an insulating layer 12G, and a top gate 12A are sequentially formed. The insulating layer 12F is
For example, it is silicon nitride, and Si ₃ N ₄ is used as a usual insulating film, but the atomic ratio of silicon is increased to form silicon with a surplus of bonding and form a trap 12Fa capable of trapping electrons. . Actually, there is a hole trap, but the hole cannot move at high speed, and therefore the fluctuation range of the voltage at the time of writing data in the top gate 12A is small. The insulating layer 12F is, for example, silicon nitride and is a part of the partition wall B in FIG. The structure of each component from the bottom gate 12B to the top gate 12A is
It is arranged so as to at least partially overlap in the vertical direction. Although not shown in the figure, the semiconductor layer 12E and the terminals 12C and 12 corresponding to the source and drain electrodes, respectively.
An impurity semiconductor layer containing n-type impurity ions may be interposed between the impurity semiconductor layer and D.

Here, the data erasing operation of the DG memory TFT 12 will be described with reference to FIG. At the time of data erasing operation, a high signal (for example, 15
V) is input to the gate of the TFT 11 from the address line Y1, the TFT 11 is turned on, and a high signal (15 V) is input to the terminal (drain) of the TFT 11 from the data line X1 to obtain the high level data signal of the data line X1. Signal (15
V) (erase control signal) potential is applied to the drain of the TFT 11,
It is transmitted to the top gate 12A via the source.

In the DG memory TFT 12, the power supply voltage Vdd (15V) from the power supply voltage electrode Z is applied to the bottom gate 12B.
Since the bottom gate 12B has a high signal voltage (15V) applied to the terminal 12C (drain) and the terminal 12C (drain), the drain 12C and the terminal 12D (source, for example, 5) having a low potential are applied.
V, that is, the DG memory TFT 12 is divided by 10 V) to form a channel of an electron carrier in the semiconductor layer 12E between the power source voltage electrode Z, the drain 12C, the source 12D, and the organic EL diode 13. A current flows to the reference voltage electrode W, and the organic EL diode 13 emits light.

At the same time, the high signal voltage (15 V) of the top gate 12A pulls out the electrons trapped in the trap 12Fa of the insulating layer 12F and takes them into the semiconductor layer 12E to form a channel. It will not interfere.

Here, the data writing operation of the DG memory TFT 12 will be described with reference to FIG. At the time of data writing operation, a low signal (here, for example, 0 V) which is an address signal is input from the address line Y1 to the gate of the TFT 11. At this time, the data signal is 0 to -1.
An arbitrary signal of 5 V (light emission control signal) is input from the data line X1 to the source terminal of the TFT 11. Since the gate potential of the TFT 11 is higher than that of the source of the TFT 11, the TFT 11 is turned on, and the potential of the signal of 0 to −15 V is applied to the top gate 12A via the data line X1 and the TFT 11.
Applied to.

Between the power supply voltage electrode Z and the reference voltage electrode W, the DG memory TFT 12 and the organic EL diode 13 are provided.
Are connected in series, and the power supply voltage Vdd and the reference voltage Vss are constantly applied to both ends. Therefore, when the n channel is formed in the DG memory TFT 12, the partial pressure ratio of the organic EL diode 13 becomes high due to the low ON resistance of the DG memory TFT 12, and light is emitted. On the contrary, DG memory TF
If the n channel is not formed in T12, the DG memory TF
Due to the high off-resistance of T12, a voltage sufficient to flow a current for light emission is not divided between the anode and cathode of the organic EL diode 13. Thus, DG memory TFT
The voltage between the source and drain of 12 is controlled by the state of the channel, but the channel has a top gate voltage, a bottom gate voltage, a top gate 12A, and a bottom gate 1
It is controlled by the charge accumulated between 2B.

When writing data, the DG memory TFT 12
Then, the power supply voltage Vdd (15V) is applied from the power supply voltage electrode Z to the bottom gate 12B. On the other hand, since the signal potential of 0 to −15 V of the facing top gate 12A is applied, the electrons in the semiconductor layer 12E are repelled and are trapped by the trap 12Fa of the insulating layer 12F.
Since the bottom gate 12B is a constant voltage, the amount of trapped electrons is uniquely controlled by the light emission control signal potential applied to the top gate 12A, and the closer the potential is to 0V, the more electrons are not repelled and the trap 12Fa is trapped. Not captured, -15
The closer to V, the greater the repulsive action, so trap 12
The amount of electrons trapped in Fa increases.

Since the electrons forming the electron carriers are trapped in the semiconductor layer 12F, the more the trapped electrons are, the less current flows. In addition to the electrons forming the channel, the electrons captured in the trap 12Fa are also captured in the electron-hole pairs generated by the ambient light hitting the semiconductor layer 12E.

In this way, the potential of the data line X1 (0 to −
15V) to control the organic EL diode 1
It is possible to control the current flowing through the element 3 and control the luminance of the light emitted from the organic EL diode 13. Then, the DG memory TFT 12
The electric charge according to an arbitrary potential of 0 to -15 V of the data line X1 is stored in the trap 12Fa as luminance data (channel state) so that it can be stored for a long time without refreshing.

Next, the data read operation of the DG memory TFT 12 will be described. The organic EL diode 13 has 0 to −15 of the top gate 12A during the data writing operation.
Light emission is performed with a luminance corresponding to the potential of the V signal. Pixel P
After the (1,1) data write operation, the potential of the signal of −15V from the address line Y1 is changed to T as the data read operation.
If the potential of the data line X1 is prevented from being transmitted to the top gate 12A of the DG memory TFT 12 by inputting it to the gate of the FT11 and turning it off, the luminance data of the light emission at the time of the previous data writing operation to the semiconductor layer 12E of the DG memory TFT Since (the channel state corresponding to the potential of 0 to -15V) is stored, the organic EL diode 11 continues to emit light at the brightness stored in the previous data writing operation unless the data erasing operation is performed.

This is because in the light emitting operation of the DG memory TFT 12, the potential of the signal of −15 V from the address line Y1 is changed to TF.
Since it is inputted to the gate of T11 so that the potential of the data line X1 is not transmitted to the top gate 12A of the DG memory TFT 12, the capacitor constituted by the parasitic capacitance between the top gate 12A and the source 12D is sufficiently large.
The voltage at the time of the previous data write operation is stored in the top gate 12A. As described above, the electric field of the bottom gate 12B formed by the power supply voltage Vdd from the constant power supply 4 is generated by the electric field of the electric charge accumulated by the electrons accumulated in the trap 12Fa and the electric charge accumulated in the capacitor between the top gate 12A and the source 12D. The channel size of the DG memory TFT 12 is controlled by suppressing or canceling.

The trap 12 is formed by the top gate 12A in order to prevent channel formation by the bottom gate 12B.
The amount of electrons trapped in Fa (the amount of electrons trapped in the trap 12Fa) is equal to that of the top gate 1 during the data write operation.
It is proportional to the product of the absolute value of the voltage magnitude of 2 A and the data writing time to the top gate 12A.

Now, referring to FIG. 6, the DG memory TF
The voltage-current characteristic of T12 will be described. FIG. 6 is a graph showing an example of voltage-current characteristics of the DG memory TFT 12.
As shown in FIG. 6, D with respect to the voltage Vg (= power supply voltage Vdd) of the bottom gate 12B of the DG memory TFT 12
The drain 12C to the source 12D of the G memory TFT 12
The drain current Id flowing in the area shifts as shown in FIG. 6 when the data erasing state (I) in which the data erasing operation is completed is changed to the lowest luminance data writing state (II) in which the data writing operation is finished to the lowest luminance. .

In the lowest brightness data writing state (II) on the graph of FIG. 6, data writing is performed so that the data line X1 is set to −15 V to minimize the current flowing between the drain 12C and the source 12D of the DG memory TFT 12. Although not shown, the state in which the data line X1 is written with 0V to −15V is located between the data erased state (I) and the lowest luminance data written state (II). Therefore,
Since the power supply voltage Vdd is fixed at 15V, the drain current Id can be freely controlled between the drain current value Id1 in the data erase state and the drain current value Id2 in the data write maximum state (II).

Next, referring to FIG. 7, address lines Y1 ...
The operation timing of the pixels P (1,1) to P (m, n) of the DG memory TFT 12 according to signals input to Yn and the data lines X1 to Xm will be described. FIG. 7 shows address lines Y1 and Y.
2 is a timing chart of signals input to the data lines X1 and X2.

In the overall flow, the address line Y1 is selected, and the signal of the address line Y1 and the data lines X1 to Xm are selected.
Signal causes the pixels P (1,1) to P (m, 1) to simultaneously perform the data erasing operation and the data writing operation, and then similarly, the address line Y2 is selected and the pixel P (1,2) is selected. ~
P (m, 2) are simultaneously operated to erase data and write data, and are sequentially operated. Finally, similarly, the address line Yn is selected and pixels P (1, n) to P (m,
n) are simultaneously subjected to the data erasing operation and the data writing operation, and this operation is repeated to repeat the operations of the pixels P (1, 1) to P (m,
The brightness of the organic EL diode 13 of n) is controlled. In advance, all address lines Y1 to Yn are unselected, and −15
It is assumed that a constant V signal is input. Here, in the data writing period, a signal of 0 to −15 V is input to the data lines X1 to Xm and 0 is input to the data lines X1 to Xm.
When inputting, the semiconductor layer 12 of the DG memory TFT 12
Since the largest carrier is formed in E, the organic EL diode 13 is assumed to have the brightest brightness, and the data line X1
When −15 V is input to −Xm, carrier formation is most hindered, so that the organic EL diode 13 has the darkest luminance.

Here, all pixels P (1,1) to P (m,
n), the pixels P (1,1), P (1,) to which the address lines Y1, Y2 and the data lines X1, X2 shown in FIG. 2 are connected.
The operation timings of 2), P (2,1), and P (2,2) will be representatively described. First, in the data erasing period for selecting the address line Y1, the address driver 2 outputs 15V to the address line Y1 and −15V to the other address lines Y2, and the data driver 3 outputs the data line 3 in response to the control signal from the controller 5. A signal of 15V is para-outputted to X1 and X2 to perform the data erasing operation of the pixel P (1,1) and the pixel P (2,1).

Then, in the data write period for selecting the address line Y1, 0 V is applied to the address line Y1 and the data line X
A signal of 0 to -15 V is input to 1, X2, and the pixel P
The data write operation of (1,1) and the pixel P (2,1) is performed. Here, the data driver 3 sets 0 to the data line X1.
V signal is input, -15V signal is input to the data line X2, the brightness of the pixel P (1,1) is maximized to write brightness data, and the brightness of the pixel P (2,1) is changed. The brightness data is written in the darkest. The address line Y1
In the selected data erasing period and data writing period,
The address line Y2 is not selected, a constant signal of -15 V is input, and the brightness of the pixels P (1,2) and P (2,2) is the brightness data written in the previous data write operation. Correspondingly emitted.

Then, in the data erasing period for selecting the address line Y2, 15 V is applied to the address line Y2 and the data line X
Input a 15V signal to 1, X2, and set the pixel P (1, 2)
And the data erasing operation of the pixel P (2,2) is performed. Also,
When the address line Y1 is not selected and a constant signal of −15 V is input, the brightness of the pixels P (1,1) and P (2,1) is
Light is emitted corresponding to the brightness data written in each data writing period.

Then, in the data writing period for selecting the address line Y2, 0 V is applied to the address line Y2 and the data line X
A signal of 0 to -15 V is input to 1, X2, and the pixel P
The data write operation of (1, 2) and the pixel P (2, 2) is performed. Here, a 0V signal is input to the data line X1, a -7.5V signal is input to the data line X2, and the brightness of the pixel P (1,2) is maximized to write the brightness data. Luminance data is written to set the luminance of P (2, 2) to an intermediate value.

Then, in the data reading period in which the address lines Y1 and Y2 are not selected, the address line Y2 is deselected while the address line Y1 is deselected, and a constant signal of -15 V is input to the pixel P (1 , 2) and P (2, 2) are emitted corresponding to the luminance data written in the data writing period.

Although not shown, the address lines Y3 to Yn are sequentially selected while the address lines Y1 and Y2 are not selected. After the last address line Yn is selected, the next address line Y1 is selected, and the pixel P (1,1) and the pixel P are selected.
The data erasing operation and the data writing operation of (2, 1) are performed. Similarly, after the address line Y1 is selected this time, the next address line Y2 is selected, and the pixel P (1,2) and the pixel P are selected.
The data erase operation and the data write operation of (2, 2) are performed.

Pixels P (1,1) and P (2,1) emit light of the highest luminance in the data erasing period of selecting the address line Y1 and have the purpose of completing the data writing operation in the data writing period of selecting the address line Y1. However, since the selected period is a very short period compared to the non-selected period, it is displayed as if it were emitted to the target luminance as a whole. The same applies to the pixels P (1,2) and P (2,2).

The timing described here is the timing at which the data erasing operation and the data writing operation are periodically performed on each pixel. However, after the data writing operation is performed on a certain pixel, the next periodic data writing operation is performed. When the same brightness data is written, since the brightness data written previously is stored in the DG memory TFT 12 in the pixel, the data erasing operation and the data writing operation can be omitted.
At this time, the address line connected to the pixel is deselected (a signal of −15V is input), and no signal is input to the address line connected to the pixel (a signal of 0V is input).

For example, when the image of the light emitting panel 1 is a still image, since the brightness of all pixels is not changed, it is not necessary to operate the data driver 3 to input control signals to all the data lines X1 to Xm. It is only necessary to input a constant -15V signal from the address driver 2 to all the address lines Y1 to Ym, and it is not necessary to switch the signals generated by the data driver 3 and the address driver 2, so that the overall power consumption is small. can do.

When the data writing operation of the pixel corresponding to the address line is completed during the data writing period when a certain address line is selected, the pixel connected to the data writing is connected until the end of the data writing period. A configuration may be adopted in which 0V is input subsequently to the data line. That is,
The size of the channel is controlled by suppressing or canceling the electric field of the bottom gate 12B only by the charges due to the electrons accumulated in the trap 12Fa. In this case, since signal generation and output in the data driver 3 are stopped for the pixels for which data writing has been completed, the power consumption of the data driver 3 can be reduced.

Therefore, according to the present embodiment, the luminance data (channel state) of the light emission for each pixel is stored in the DG memory TFT 12 without performing the refresh periodically, so that the pixel is always made to emit light while Since it is not necessary to perform the data erasing operation and the data writing operation for the pixel having the same brightness as that of the frame, and it is not necessary to perform the signal switching operation by the data driver and the address driver, the power consumption and the processing load can be reduced. it can. Especially when displaying a still image, the data driver is stopped and the address driver generates a signal of a constant voltage.
The power consumption and the processing load can be significantly reduced.

The DG memory TFT 12 has the trap 1
Since the electrons are captured by 2Fa, it is not necessary to provide a capacitor other than the parasitic capacitance of the transistor, and two switching members, the TFT 11 and the DG memory TFT 12, are used. Therefore, the area ratio of the organic EL diode 13 for each pixel is increased. The aperture ratio can be increased, the pixel can be miniaturized and high-definition display can be achieved, and the increase in the aperture ratio can suppress the luminance of the light emission of the organic EL diode for each pixel in the display of the same luminance to suppress the amount of current flowing. Therefore, the power consumption can be further reduced.

In the data writing operation, 0 to -15V is applied to the top gate 12A of the DG memory TFT 12.
It is possible to control the emission of light of any brightness by applying any voltage of.

Furthermore, during the data erasing operation, a signal of 15V,
When a data write operation is performed, a signal of 0 to -15 V is input to the data line, and a strong positive and negative bias is repeatedly applied to the top gate 12A of the DG memory TFT 12, so deterioration due to long-term application of one bias is prevented, and the DG memory The life of the TFT 12 can be extended.

Although the organic EL diode 13 is used as the light emitting means in the present embodiment, the inorganic EL diode 13 is used.
A configuration using other light emitting elements such as an L diode may be used, and an LCD (Liquid Crystal Displ
ay) is adopted and the voltage applied to the liquid crystal provided for each pixel is controlled to control the light transmission through the liquid crystal to the light from the light emitting source such as a backlight, thereby displaying an image. May be.

Further, in this embodiment, the TFT 11 and the D
Although the G memory TFT 12 uses amorphous silicon for the semiconductor layer forming the n-channel, it may use polysilicon or the like.

Furthermore, in the data write operation, 0 to -15V is applied to the top gate 12A of the DG memory TFT 12.
When a voltage whose absolute value is larger than that of the previous data write operation is applied with the voltage of, the channel for flowing a target current to the semiconductor layer 12E is formed even if the data erasing operation immediately before the data write operation is omitted. Can be made. When omitting the data erasing operation for emitting light at the maximum brightness, it is possible to suppress power consumption and processing load.

Although the embodiments of the present invention have been described above, the present invention is not necessarily limited to only the above-described means and methods, and the objects referred to in the present invention can be achieved and the effects referred to in the present invention can be achieved. Modifications can be appropriately made within the range.

[0097]

According to the present invention, the luminance data of the light emission of each pixel can be erased and stored in the memory drive means for a long time without being refreshed, and the stored luminance can be stored. Since the pixel always emits light in accordance with the data, it is possible to reduce the power consumption. Further, since only the selection means and the storage control means are provided as the switching member of the pixel, the area ratio of the light emitting means for each pixel is increased, so that the area of one pixel as a whole can be made smaller and high-definition display is possible. Therefore, the power consumption can be further reduced.

According to the second or seventh aspect of the present invention, since the erase control signal and the light emission control signal are repeatedly input to the memory drive means, deterioration of the memory drive means due to long-time input of the same signal can be prevented. it can.

According to the invention of claim 3 or 8, it is not necessary to erase and write the brightness data for the pixel having the same brightness as that of the previous selection, and it is not necessary to generate the control signal to the pixel. Therefore, the processing load and power consumption can be reduced. In particular, when displaying a still image, the means for generating control signals for all pixels can be stopped,
The power consumption and the processing load can be significantly reduced.

According to the invention of claim 4 or 9, it is possible to control each pixel to emit light of continuous arbitrary emission.

According to the invention of claim 5, the data erasing procedure is omitted when the data erasing procedure which does not require the data erasing procedure is performed. Therefore, the load of executing the data erasing procedure and the power consumption thereof are reduced. Can be made.

According to the tenth aspect of the invention, a TFT is used as the selecting means and a DG memory TFT is used as the memory driving means,
It can be controlled by the voltages of the selection signal and the control signal.

According to the invention of claim 11, the DG
Since the memory TFT has a vertical structure and further has an insulating layer for trapping electrons, it is not necessary to provide a separate capacitor,
Since the space can be saved, the area per pixel can be made smaller and high-definition display can be achieved.

[Brief description of drawings]

FIG. 1 is a diagram showing a display α according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of light emitting panel 1 shown in FIG.

FIG. 3 is a schematic cross-sectional view of the light emitting panel 1 shown in FIG.

FIG. 4 is a sectional view of the DG memory TFT 12 showing a data erasing operation.

FIG. 5 is a DG memory TFT 12 showing a data writing operation.
FIG.

FIG. 6 is a graph showing a voltage-current characteristic of the DG memory TFT 12.

FIG. 7 is a timing chart of signals input to address lines Y1 and Y2 and data lines X1 and X2.

FIG. 8 is a diagram showing a conventional voltage-controlled light emitting panel 6.

[Explanation of symbols]

α ... display 1 ... Luminescent panel 11 ... TFT 12 ... DG memory TFT 12A ... Top gate 12B ... bottom gate 12C ... terminal (drain) 12D ... Terminal (source) 12E ... Semiconductor layer 12F ... Trap insulation layer 12 Fa ... trap 12G ... Insulating layer 13 ... Organic EL diode 13A ... Anode electrode 13B ... Organic EL layer 13C ... Cathode electrode 2 ... Address driver 3 ... Data driver 4 ... power supply 5 ... Controller A: Transparent substrate B ... Partition C ... Sealing material D ... Sealing glass Y1 to Yn ... address lines X1 to Xm ... Data line Z ... Power supply voltage electrode W ... Reference voltage electrode P (1,1) to P (m, n) ... Pixels 6 ... Light emitting panel 6A ... Data line 6B ... Address line 6C ... Power line 6D, 6E ... TFT 6F ... Organic EL diode 6G ... Common grounding part 6H ... Capacitor

Claims (11)

[Claims] 1. A selection unit that outputs a control signal for controlling the luminance of the light emission of the pixel when the pixel is selected for each of a plurality of pixels arranged in a matrix, and during the selection period, Corresponding to the control signal output from the selecting means, the luminance data of the light emission is stored for a long time so as to be electrically erasable and writable, and the current input from the power source is output corresponding to the stored luminance data. A driving method for a memory driving display device, which comprises a light emitting panel provided with a memory driving means for performing light emission based on a current output from the memory driving means, and displays an image by light emission of each pixel. Then, during the selection period, an erase control signal for erasing the brightness data stored in the storage drive unit is generated as the control signal for the selected pixel, A data erasing procedure that causes the generated erasing control signal to be output and causes the storage driving unit to erase the brightness data stored therein based on the output erasing control signal; Data writing for generating a light emission control signal designating the brightness of the light, causing the selection unit to output the generated light emission control signal, and writing the brightness data to the storage drive unit based on the output light emission control signal. The procedure and are sequentially executed, and in the non-selected period, in the non-selected pixel, the memory drive unit is caused to output a current corresponding to the luminance data written in the data write procedure, and the memory drive is performed. A method of driving a memory drive type display device, characterized in that a data reading procedure for causing light emission is executed based on the current output from the means. 2. The method for driving a memory drive type display device according to claim 1, wherein the selection and the non-selection are alternately and repeatedly executed. 3. The drive method for a memory drive type display device according to claim 1, wherein the selection is executed when the light emission control signal is changed. 4. The light emission control signal is a signal for designating an arbitrary brightness of the light emitting means, and the brightness data is data for designating an arbitrary brightness. Alternatively, the method of driving the memory-driven display device according to the above item 3. 5. After the execution of the data writing procedure, if the next data writing procedure can be continued, the execution of the data erasing procedure executed before the next data writing procedure is omitted. A method for driving a memory-driven display device according to claim 1, 2, 3, or 4. 6. A control signal generation means for generating a control signal for controlling the luminance of light emission of each pixel in a plurality of pixels arranged in a matrix, and a selection signal generation for generating a selection signal designating selection of the pixel. Means and a light-emitting panel consisting of the plurality of pixels, the storage drive type display device for displaying an image by the light emission of each pixel, each pixel according to the selection signal output from the selection signal generation means. A selection unit that outputs the control signal output from the control signal generation unit during the selection period of its own pixel, and an electrical signal corresponding to the control signal output from the selection unit during the selection period. A storage drive unit that stores the emission brightness data for a long time so that it can be erased and written, and outputs a current based on the stored brightness data during a non-selected period, and an output from the storage drive unit. A memory drive type display device comprising: a light emitting unit that emits light based on the generated current. 7. The selection signal generating means alternately and repeatedly generates the selection signal indicating the selection and the selection signal indicating the non-selection, and the control signal generating means controls during the selection period. 7. The memory drive type display device according to claim 6, wherein an erase control signal for erasing the brightness data and a light emission signal for writing the brightness data are sequentially generated as signals. 8. The selection signal generating means generates a selection signal indicating the selection when the luminance of the light emission of the light emitting means of each pixel is changed.
The memory-driven display device described. 9. The control signal generating means generates a light emission control signal for designating the luminance of arbitrary light emission of the light emitting means of each of the pixels during the selection period, and the storage driving means controls the light emission control. 9. The storage drive type display device according to claim 6, wherein brightness data for designating an arbitrary brightness of light emission is stored in correspondence with a signal. 10. In each of the pixels, the selection means is provided with a first gate and first and second terminals, the first gate is connected to the selection signal generation means, and the first signal is connected to the selection signal generation means. Has a terminal connected to the control signal generation means, and corresponds to the selection signal input to the first gate and the control signal input to the first terminal,
It is a TFT which forms a channel between the first terminal and the second terminal, wherein the memory driving means is provided with second and third gates, and third and fourth terminals, The gate is connected to the second terminal of the TFT, the third gate and the third terminal are connected to a power supply that supplies a predetermined voltage, the fourth terminal is connected to the light emitting means, and The brightness data is stored in correspondence with the control signal input to the second gate, and the brightness data is stored in correspondence with the stored brightness data.
7. A DG memory TFT that forms a channel between the third terminal and the fourth terminal,
The memory-driven display device according to item 7, 8 or 9. 11. The second and third gates of the DG memory TFT are arranged so as to be vertically overlapped with each other, and the DG memory TFT traps electrons between the second and third gates. The memory drive type display device according to claim 10, further comprising an insulating layer in which a trap is formed.