JP2003209181A - Method for manufacturing semiconductor chip - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a rewiring layer-integral type semiconductor chip capable of preventing a maloperation by noise or the deterioration of communication characteristics. <P>SOLUTION: A rewiring layer comprising a metallic spatter layer 34 and a metallic plating layer 39 is formed on an insulating surface protecting layer 33 formed on the circuit formed surface of a complete wafer 31. The rewiring layer is formed around the periphery of an analog circuit formed on the circuit formed surface. The analog circuit may be formed by collecting all analog circuits to be formed in the semiconductor chip, for example, may be one of the particularily noise-susceptible analog circuits such as a power circuit, a calculating amplifier, a comparison amplifier, an RF receiving part, an RF transmitting part, an RF synthesizer, and a voltage build-up circuit or an amplifying circuit forming a part of a memory. After the rewiring layer is formed, the complete wafer 31 is scribed so that a desired semiconductor chip can be obtained. <P>COPYRIGHT: (C)2003,JPO

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention
In particular, it is formed on the circuit formation surface via an insulating layer.
The present invention relates to a method for forming a rewiring layer. 2. Description of the Related Art A card type, tag on which a semiconductor chip is mounted.
A semiconductor device such as a G-shaped or coin-shaped
Due to its high security performance, traffic, flow
It is spreading in the fields of communications and information communications. Above all,
Non-contact communication type semiconductor devices developed in recent years are
Power supply from the reader / writer and lead
Sending and receiving signals to and from the writer by radio
So, like the contact type semiconductor device, the damage of the external terminal
Inherently, it is easy to handle and preserve for a long time
Can withstand the use of data and is difficult to tamper with data
It has the feature that it is more excellent in security performance.
Therefore, it is expected to spread to a wider range of fields in the future. Conventionally, in this kind of non-contact type semiconductor device,
As a semiconductor chip to be mounted, power from an external device
Receiving and sending / receiving signals to / from external devices
Without an antenna coil for non-contact communication
In recent years, it has been shown in FIG. 16 and FIG.
Thus, the rewiring layer 3 is formed on the circuit formation surface via the insulating layer 2.
The antenna coil 4 is formed with the rewiring layer 3.
Coil-on-chip type semiconductor chip formed on the body
1 has been proposed. Coil-on-chip type semiconductor chip 1
The antenna coil does not need to be prepared separately.
Connection between the antenna coil and the semiconductor chip and the connection
Non-contact type semiconductor device
Can be manufactured easily and its cost can be reduced.
The Also, in recent years, non-contact type or contact type
Regardless of the type, the semiconductor chip mounted on the semiconductor device
As shown in FIG. 18 and FIG.
Semiconductor chip on which input / output terminals (pads) 5 are formed
The rewiring layer 3 is formed on the circuit forming surface of the substrate with the insulating layer 2 interposed therebetween.
With the rewiring layer 3, one end is the input / output terminal 5.
Bump 7 is formed at the other end, and the semiconductor chip
Bump setting wiring 6 is formed on the entire surface of the substrate.
Chip scale package (hereinafter abbreviated as “CSP”)
Called. ) Type semiconductor chip 8 has been proposed. Using the CSP type semiconductor chip 8
Then, the bumps 7 are freely laid out on the entire surface of the semiconductor chip 8.
Formed along the outer periphery so it can be out
Bump compared to the case where bump 7 is formed on input / output terminal 5
7 by increasing the array pitch and bump size.
Multiple input / output terminals 5 and semiconductor chip flip
It is possible to facilitate chip mounting. [0007] By the way, a semiconductor device.
As shown in FIG.
And a power supply circuit 11 and an operational amplifier as shown in FIG.
(Op-amp) 12 and comparison amplifier (comparator) 1
3, RF receiver 14, RF transmitter 15, RF thin
A synthesizer unit 16, a logic unit 17, a memory unit 18, etc.
It is divided into blocks and has higher security.
If a high level of performance is required, the microprocessor
Sometimes stored. The power supply circuit 11 and the operational amplifier 1
2, comparison amplifier 13, RF receiving unit 14, RF transmitting unit 15
And the RF synthesizer 16 are mostly analog
The memory unit 18 is also an EEP as a memory element.
When using a ROM, etc., part of the voltage booster circuit and
There are analog circuits such as width circuits. On the other hand,
The processing unit 17 is mostly composed of a digital circuit. Na
Conventionally known semiconductor chips for mounting semiconductor devices
The coil is provided with a coil portion in a part of the analog circuit.
There are also things. Coil-on in which the rewiring layer 3 is integrally formed
Chip type semiconductor chip 1 and CSP type semiconductor
In the body chip 8, insulation having a relatively high dielectric constant
Circuit formation surface of semiconductor chips 1 and 8 and rewiring through layer 2
Since the layer 3 is disposed close to the layer 3, it is schematically shown in FIG.
The circuit formed on the circuit forming surface and the rewiring layer 3
A parasitic capacitance C is formed between the two. However, the conventional coil-on-chip type
In semiconductor chip 1 and CSP type semiconductor chip 8
In this case, the parasitic capacitance C is generated in the formation part of the analog circuit.
No consideration has been given to the adverse effects of
As shown in FIGS. 16 to 19, the antenna coil 4 or
The bump setting wiring 5 faces the analog circuit forming portion.
The position is also formed. Therefore, the conventional coil-on-chip type
Semiconductor chip 1 and CSP type semiconductor chip 8
The analog circuit formed on the circuit forming surface and the rewiring layer 3
And a parasitic capacitance C is generated between the two and the rewiring layer 3.
Electromotive force (alternating current) and parasitic capacitance C combine to generate electrostatic induction noise
Furthermore, the noise is further reduced due to the electrostatic induction noise.
Lost talk noise, ringing (LC resonance shift) and electricity
Source noise, etc., resulting in malfunctions and poor communication characteristics
There is a problem that it tends to occur. In addition, the conventional coil-on-chip type half
The conductor chip 1 and the CSP type semiconductor chip 8 are
The path forming surface and the rewiring layer 3 are arranged opposite to each other with the insulating layer 2 interposed therebetween.
Since each circuit formed on the circuit forming surface is electromagnetic
Inductive noise is also likely to occur.
Degradation of communication characteristics is also likely to occur. The electrostatic induction noise or electromagnetic induction noise
Crosstalk noise, ringing and power noise caused by
The noise such as the power supply circuit 11, the operational amplifier 12,
Comparative amplifier 13, RF receiver 14, RF transmitter 15 and
Analog circuit such as RF synthesizer 16
Operational amplifier 12 and comparison amplifier for handling small voltage waveforms
13 and a memory unit 18 that handles minute signals.
Large voltage booster circuit and amplifier circuit, and coil etc.
Influence. In addition, these noises are voltage handled
Circuits with higher waveforms and signal frequencies have a greater negative effect
Therefore, for example, it is a high frequency
Especially in the case of conductor chips, the generation of the noise is suppressed.
It is necessary to The present invention has been made to solve such problems.
The problem is that rewiring
Layer-integrated semiconductor chip that malfunctions due to noise
For manufacturing semiconductor chips that are less susceptible to degradation of communication characteristics
Is to provide. The present invention solves the above-mentioned problems.
In order to determine the semiconductor chip manufacturing method,
Completed wafer on which circuits for many semiconductor chips are formed
Using an insulating layer on the circuit forming surface of the finished wafer.
Of the analog circuit included in the circuit for the semiconductor chip.
Rewiring layer that does not overlap all or part of each other is formed
After that, the completed wafer on which the rewiring layer is formed
To obtain the required semiconductor chip
Made the configuration. Thus, on the circuit formation surface of the semiconductor chip,
The formed analog circuit and redistribution layer are connected via an insulating layer.
Arrange them so that they do not overlap.
No parasitic capacitance is formed between the line layer and the analog circuit.
It is possible to prevent the generation of capacitance noise to be used.
Also, the analog circuit and the rewiring layer are not placed opposite to each other
Therefore, the generation of electromagnetic induction noise acting on the analog circuit
Can be prevented. Therefore, these electrostatic induction noise
Or crosstalk noise caused by electromagnetic induction noise,
Occurrence of ringing and power supply noise is prevented, and
Also suitable for rewiring layer integrated semiconductor chip
It is possible to eliminate malfunctions and communication characteristics deterioration
The Further, a necessary rewiring layer is formed on the completed wafer.
After that, scribing the completed wafer
When obtaining a semiconductor chip, redistribution layer on each semiconductor chip
Compared to the case of forming a coil-on-chip or CSP
Type semiconductor chips can be manufactured with high efficiency.
Chip manufacturing costs can be reduced. Also complete
Uniform for all semiconductor chips formed on the wafer
A rewiring layer with a sufficient thickness can be formed with high accuracy.
Thus, the variation in communication characteristics can be reduced. The
Furthermore, sputtering or vacuum is applied to individual semiconductor chips.
When the rewiring layer is formed using vapor deposition and plating,
Unnecessary conductors adhere to the outer periphery of the conductor chip, resulting in a semiconductor chip.
Insulation of the substrate becomes a problem, but a rewiring layer is formed on the finished wafer.
If completed, remove the wafer from the finished wafer during sputtering.
Even if an unnecessary conductor adheres to the peripheral part, the part is regarded as an unnecessary part.
Since it is a part that should be disposed of originally, individual semiconductors
There is no adverse effect on the insulation of the chip. DESCRIPTION OF THE PREFERRED EMBODIMENTS <First Example of Semiconductor Chip> The Present Invention
A first example of a semiconductor chip according to FIG.
I will explain. FIG. 1 shows a semiconductor chip according to the first embodiment.
1A is a plan view, and FIG. 2 is a cross-sectional view taken along the line AA in FIG.
The The semiconductor chip 1A of this example has a coil on-chip.
Type semiconductor chip, as shown in FIG. 1 and FIG.
Rewiring on the circuit forming surface 1a through the insulating layer 2
The layer 3 is formed and the rewiring layer 3 is used to
Are integrally formed. And the semiconductor chip of this example
In 1A, it is formed at the center of the circuit forming surface 1a.
Avoid the analog circuit 21 and square around it
A spiral antenna coil 4 is formed. The analog circuit 21 includes the semiconductor chip 1.
All analog circuits that should be formed in A
For example, the power supply circuit 11, the calculation increase
Width 12, comparison amplifier 13, RF receiver 14, RF transmission
Unit 15 and RF synthesizer unit 16 and the memory
Such as a voltage booster circuit and an amplifier circuit constituting a part of the unit 18
Of analog circuits that are particularly susceptible to noise
It may be one. Furthermore, it is formed on the semiconductor chip 1A.
A coil provided in a part of the analog circuit
Also good. The semiconductor chip 1A of this example is based on a semiconductor
Body chips (more practically, cut into individual semiconductor chips
Insulation on the circuit forming surface 1a of the completed wafer)
Produced by forming a rewiring layer 3 via layer 2
It is. Semiconductor chip that is the basis of the semiconductor chip 1A of this example
For example, any semiconductor chip belonging to the public domain may be used.
However, the final product, non-contact semiconductor device, is thin.
For the purpose of shaping, the non-formed surface 1b of the circuit is chemically polished or machined.
Thin by mechanical polishing or a combination of these means
It is particularly preferable to use a structured bare chip. That
The thickness is preferably 300 μm or less, especially a thin card.
About 50 μm to 150 μm
Preferably. In addition, CMOS technology
A wireless communication circuit formed on the road forming surface or an external device
Send and receive signals with a frequency of 800 MHz or higher
Or a wireless communication circuit for transmitting and receiving was formed on the circuit forming surface
Things can also be used. In the example of FIG. 1, the antenna coil 4 is
The antenna coil 4 is wound by a plurality of turns.
The number of turns is not limited to this.
The number of turns can be any number of turns. More
In addition, regarding the planar shape of the antenna coil 4, FIG.
It is not limited to the example of FIG.
To reduce communication characteristics degradation due to shape effects
It can also be made into a shape. Insulating layer 2 and rewiring layer 3
Is stacked in multiple stages to increase the number of turns of the antenna coil 4
You can also The semiconductor chip 1A of this example has a circuit forming surface 1
Avoid the analog circuit 21 formed at the center of a.
The antenna coil 4 is formed, the analog circuit 21 and the antenna
The coils 4 were arranged so as not to overlap each other
In the parasitic circuit between the analog circuit 21 and the antenna coil 4
Capacitance that does not form capacitance and acts on the analog circuit 21
Generation of quantity noise can be prevented. Also analog
Circuit 21 and antenna coil 4 are not arranged opposite to each other
Therefore, the generation of electromagnetic induction noise acting on the analog circuit 21
Can prevent life. Therefore, these electrostatic induction nodes
Crosstalk noise caused by noise or electromagnetic induction noise
Noise, ringing and power supply noise are prevented.
Frequency-related coil-on-chip is also caused by noise
Malfunctions and deterioration of communication characteristics can be eliminated. In particular, the semiconductor on which the semiconductor chip 1A is based
As a chip, wireless communication is possible on the circuit formation surface by CMOS technology.
When a circuit in which a communication circuit is formed is used, the rewiring layer 3
This type of antenna is particularly susceptible to (antenna coil 4)
Degradation of communication characteristics of semiconductor chips can be prevented
The Also, the semiconductor chip that is the basis of the semiconductor chip 1A and
Then, a signal with a frequency of 800 MHz or more is exchanged with an external device.
A wireless communication circuit that transmits, receives, or transmits signals
If the one formed on the surface is used, the rewiring layer 3 (A
This type of semiconductor that is particularly susceptible to antenna coils 4)
It is possible to prevent the deterioration of the communication characteristics of the body chip. <Second Example of Semiconductor Chip> A half of the present invention
A second example of the conductor chip will be described with reference to FIG. FIG.
These are the top views of the semiconductor chip 1B which concerns on 2nd Embodiment.
The The semiconductor chip 1B of this example also has a coil on-chip.
As shown in FIG.
In addition, the rewiring layer 3 is formed on the circuit forming surface 1a via the insulating layer 2.
The antenna coil 4 is formed with the rewiring layer 3 formed.
It is integrally formed. And the semiconductor chip 1 of this example
In B, an antenna formed at one corner of the circuit forming surface 1a.
Avoid the analog circuit 21 and deform spira in the surrounding area.
A ruby antenna coil 4 is formed. Other
The semiconductor chip 1A according to the first embodiment and
Since it is the same, explanation is omitted. The semiconductor chip 1B of this example also has a circuit forming surface 1
a avoiding the analog circuit 21 formed at one corner
The tena coil 4 is formed, and the analog circuit 21 and the antenna connector are formed.
Because I arranged so that Iru 4 does not overlap each other,
Eliminate the effects of noise on the analog circuit 21
The semiconductor chip 1A according to the first embodiment can be
The same effect can be obtained. <Third Example of Semiconductor Chip> A half of the present invention
A third example of the conductor chip will be described with reference to FIGS.
The FIG. 4 is a plan view of a semiconductor chip 1C according to the third embodiment.
FIG. 5 is a sectional view taken along line BB in FIG. The semiconductor chip 1C of this example is a CSP type.
As shown in FIG. 4 and FIG.
Rewiring layer 3 is formed on circuit forming surface 1a through insulating layer 2
With the rewiring layer 3, one end is connected to the input / output terminal 5.
The other end is laid out on the entire surface of the semiconductor chip 1C.
The bump setting wiring 6 is formed and the bump setting
A bump 7 is formed on the other end of the fixed wiring 6. And
In the semiconductor chip 1C of this example, the circuit forming surface 1
avoid the analog circuit 21 formed in a part of a
Bump setting wiring 6 is routed around the side and
Bump 7 only on the side of the road 21 as a boundary
Are arranged. For the other, the first embodiment
Since it is the same as the semiconductor chip 1A according to the example, the explanation is as follows.
Omitted. The semiconductor chip 1C of this example also has a circuit forming surface 1
Bump avoiding the analog circuit 21 formed in part of a
The setting wiring 6 and the bump 7 are formed, and the analog circuit 21 is formed.
These bump setting wiring 6 and bump 7 overlap each other.
Since they are arranged so that they do not match each other,
The influence of the acting noise can be eliminated, and the first
Effects similar to those of the semiconductor chip 1A according to the embodiment are obtained.
be able to. <Fourth Example of Semiconductor Chip> Half of the present invention
A fourth example of the conductor chip will be described with reference to FIG. FIG.
These are the top views of semiconductor chip 1D which concerns on 4th Embodiment.
The The semiconductor chip 1D of this example is also a CSP type.
As shown in FIG. 6, the insulating layer 2
The rewiring layer 3 is formed on the circuit forming surface 1a via
With the rewiring layer 3, one end is connected to the input / output terminal 5.
The other end is laid out on the entire surface of the semiconductor chip 1D.
Bump setting wiring 6 is formed, and the bump setting wiring
Bumps 7 are formed on the other end of 6. And this example
In the semiconductor chip 1D, a part of the circuit formation surface 1a
Avoid the analog circuit 21 that has been formed,
The amplifier setting wiring 6 is routed to form the analog circuit 21.
Bumps 7 are arranged above and to the side of the formation part.
Has been. Others are the same as in the third embodiment.
Since this is the same as the semiconductor chip 1C, the description is omitted.
The The semiconductor chip 1C of this example also has a circuit forming surface 1
Bump avoiding the analog circuit 21 formed in part of a
The setting wiring 6 and the bump 7 are formed, and the analog circuit 21 is formed.
These bump setting wiring 6 and bump 7 overlap each other.
Since the arrangement is made so that they do not lie, the third embodiment example
The same effect as the semiconductor chip 1C according to the present invention can be obtained.
The <Fifth Example of Semiconductor Chip> Half of the present invention
A fifth example of the conductor chip will be described with reference to FIG. FIG.
These are the top views of the semiconductor chip 1E which concerns on 5th Embodiment.
The The semiconductor chip 1E of this example is also a CSP type.
As shown in FIG. 7, the insulating layer 2
The rewiring layer 3 is formed on the circuit forming surface 1a via
With the rewiring layer 3, one end is connected to the input / output terminal 5.
And the other end is laid out on the entire surface of the semiconductor chip 1E.
Bump setting wiring 6 is formed, and the bump setting wiring
Bumps 7 are formed on the other end of 6. And this example
In the semiconductor chip 1E, two locations on the circuit forming surface 1a
Avoid the analog circuit 21 formed in the
The wiring 6 for bump setting is routed and the analog circuit 21
Bumps 7 are arranged on the front, rear, left and right sides of the formation portion. That
As for the rest, the semiconductor chip according to the third embodiment example
Since it is the same as 1C, the description is omitted. The semiconductor chip 1E of this example also has a circuit forming surface 1
Bump avoiding the analog circuit 21 formed in part of a
The setting wiring 6 and the bump 7 are formed, and the analog circuit 21 is formed.
These bump setting wiring 6 and bump 7 overlap each other.
Since the arrangement is made so that they do not lie, the third embodiment example
The same effect as the semiconductor chip 1C according to the present invention can be obtained.
The <First Example of Rewiring Layer Formation Method>
The antenna coil 4 or the bump setting wiring 6 is configured.
A first example of the method of forming the rewiring layer 3 is based on FIGS.
This will be explained. Figure 8 is completed through a predetermined process
FIG. 9 is a plan view of a so-called completed wafer, and FIG.
FIG. 10 is a process diagram showing a first example of the formation method of the rewiring layer 3.
It is a top view of the completed wafer in which is formed. As shown in FIG. 8, the completed wafer 31 includes
Many semiconductor chips are used in the inner periphery except the outermost periphery.
The paths 32 are formed at equal intervals, and on the circuit forming surface side
The required surface protective film 33 (see FIG. 9) is formed.
The In the first example of the method for forming the rewiring layer shown in FIG.
First, as shown in FIG.
On the surface protective film 33 formed on the path forming surface, aluminum
Or aluminum alloy or copper or copper alloy
Thus, the metal sputter layer or the metal vapor deposition layer 34 is uniformly formed.
The Next, as shown in FIG.
A photoresist layer 35 is applied on the metal layer or the metal deposition layer 34.
The photoresist layer 35 thus formed is
Required pattern including nacoil 4 or bump setting wiring 6
A mask 36 with a cover is formed on the outside of the mask 36.
The photoresist layer 35 is irradiated with light 37 having a predetermined wavelength.
Exposure. After that, the exposed photoresist layer 35
As shown in FIG.
The exposed portion of the resist layer 35 is removed and the metal sputter is removed.
Portion corresponding to the exposure pattern of the layer or metal vapor deposition layer 34
Expose minutes. Of the metal sputter layer or metal vapor deposition layer 34
As shown in FIG.
Formed on the portion excluding the pole portion 37 and the analog circuit 21
Antenna coil 4 or bump setting wiring 6 and
For electrode setting 37 and each antenna coil 4 or each bump setting
A lead portion 38 that connects the wiring 6 is included. Next
Then, using the electrode portion 37 as one electrode, metal sputtering
Electroplating or precision on the exposed portion of the layer or metallized layer 34
Electroformed, and sputtered metal layer as shown in FIG. 9 (d)
Alternatively, the metal plating layer 39 is stacked on the exposed portion of the metal deposition layer 34.
Layer. Next, the photo adheres to the surface of the completed wafer 31.
The resist layer 35 is removed by ashing or the like,
As shown in FIG. 9 (e), a uniform metal sputter layer or gold
The electrode portion 37 and the antenna coil 4 or the bar are formed on the metal deposition layer 34.
Metal plating having amplifier setting wiring 6 and lead portion 38
A completed wafer 31 on which the layer 39 is formed is obtained. Then gold
A metal sputter layer or metal vapor exposed from the metal plating layer 39
The deposited layer 34 is selectively etched and shown in FIG.
In other words, the metal sputtered layer exposed from the metal plating layer 39 or
Removes the deposited metal layer 34. This makes the metal spa
A layer or metal vapor deposition layer 34 and a metal plating layer 39 are formed.
A completed wafer 31 is obtained. Finally, the completed
Scribing Eha 31 to the location shown in FIGS.
The essential semiconductor chip IC elements 1A to 1E are obtained. In this example, the metal plating layer 39 is used.
The electroplating method or precision electroforming method was used as the forming means
However, instead of such a configuration, the electroless plating method is used.
A metal plating layer 39 can also be formed. In this case
Does not require an electrode to form the metal plating layer 39
In the exposure of the photoresist layer 35, the electrode portion 37
And the formation of the lead portion 38 become unnecessary. Electroless plating is also called chemical plating,
Immerse the base metal in the metal salt solution of the plating metal and
With a relatively simple facility.
A plating layer with strong and uniform adhesion and sufficient thickness is obtained.
There is a feature that. The metal salt is a metal to be plated
When plating copper, which is a source of ions
For example, a solution of copper sulfate, cupric chloride, copper nitrate, etc.
Used as Metal ions such as copper are the basis
Deposited only on the metal sputter layer or metal deposition layer 34,
It does not deposit on the insulating surface protective layer 33. The base material is
Is the ionization tendency smaller than the plating metal ion?
It must be capable of catalyzing the deposition of plated metal ions.
There is a point. For this reason, a metal sputter made of aluminum is used.
When plating copper on the metal layer or metal vapor deposition layer 6,
Shape nickel to a thickness of several μm or less on the surface of the ruminium layer
And pre-treatment of substituting with zinc nitrate solution for several seconds.
It is preferable to apply. On the other hand, the electroplating method and the precision electroforming method are
A sputtered metal layer or plating in a plating bath containing plated metal ions.
Is the finished wafer 31 on which the metal vapor deposition layer 34 is formed and plating.
A metal electrode is dipped and formed on the finished wafer 31.
The sputtered metal sputtered layer or metal deposited layer 34 is cathode and plated
A voltage was applied using the electrode immersed in the bath as the anode, and
Metal ions in the bath are sputtered or deposited metal layer 3
4 is deposited on the surface. Electroplating and precision
In the case of electroplating, copper sulfate, copper chloride
A solution of cupric, copper nitrate or the like is used as the plating solution. The method of forming the rewiring layer 3 in this example is a completed wafer.
Required antenna coil 4 or bump setting wiring on C31
Form the required conductive pattern including 6 and then complete
The required semiconductor chip 1 is scribed by scribing the wafer 31.
Since it is configured to obtain A to 1E, individual semiconductor chips
Antenna coil 4 or bump setting wiring 6 is formed on the top
Compared to the case of coil-on-chip or CSP type
Semiconductor chips can be manufactured with high efficiency and low manufacturing costs
Can be reduced. Further, all the wafers 31 formed on the wafer 31
Antenna coil with uniform thickness for all semiconductor chips
4 or bump setting wiring 6 can be formed with high accuracy.
As a result, variations in communication characteristics can be reduced.
The Further, the individual semiconductor chips 1A to 1E are scanned.
Antenna using the putter method or vacuum deposition method and plating method
When the coil 4 or the bump setting wiring 6 is formed, the semiconductor
An unnecessary conductor adheres to the outer periphery of the chips 1A to 1E and is semiconductive
Insulation of the body chip is a problem,
The required leads including the antenna coil 4 or the bump setting wiring 6
When an electric pattern is formed, during sputtering, etc.
Even if an unnecessary conductor adheres to the outer periphery of the completed wafer 31, the
Department is part that should be disposed of as an unnecessary part
Therefore, it adversely affects the insulation properties of the individual semiconductor chips 1A to 1E
Never give. In addition, formation of the rewiring layer 3 of this example
The method is metal plating with a photoresist layer 35 present.
The layer 39 is formed and then a metal sputter layer or gold
The portion of the metal vapor deposition layer 34 where the metal plating layer 39 is not laminated
Since the portion was removed by etching, FIG.
As shown in (e), the metal plating layer 39 is formed by metal sputtering.
Is laminated only on the upper surface of the layer or metal vapor deposition layer 34, and in the width direction
Precise antenna coil 4 or bump installation
The fixed wiring 6 can be formed, and the number of turns can be reduced within a small area.
Many antenna coils 4 or many bump setting wirings 6
Can be formed. <Second Example of Rewiring Layer Formation Method>
A second example of the method for forming the rewiring layer 3 will be described with reference to FIG.
Light up. FIG. 11 shows a second example of the method for forming the rewiring layer 3.
It is process drawing. In the method of forming the rewiring layer 3 of this example, FIG.
The surface formed on the finished wafer 31 as shown in FIG.
A photoresist layer 35 is uniformly formed on the protective film 33,
On the formed photoresist layer 35, the antenna coil 4 or
The required pattern including the bump setting wiring 6 is formed.
A predetermined wavelength from the outside of the mask 36.
The photoresist layer 35 is exposed by irradiating light 37. Shi
Thereafter, the exposed photoresist layer 35 is developed.
And a photoresist layer as shown in FIG.
The exposed portion of the surface protective film 33 is removed by removing the exposed portion 35.
The part corresponding to the pattern is exposed. Photoresist
The exposure pattern of the layer 35 is shown in FIG.
37 and the analog circuit 21 formed on the portion excluding the analog circuit 21.
Antenna coil 4 or bump setting wiring 6 and lead portion 38
The shape including Then after development processing
The completed wafer 31 is mounted on a sputtering device or a vacuum deposition device.
As shown in FIG. 11C, the surface protective film 33
A metal sputter layer or metal vapor deposition layer 34 is formed on the exposed portion of
To do. Next, as shown in FIG.
Ashing treatment of the photoresist layer 35 adhering to 31
After removing by such as the electrode portion 37 as one electrode
Electroplating the metal sputtered layer or metal deposited layer 34
As shown in FIG. 11 (e), a metal sputter layer or
A metal plating layer 39 is laminated on the exposed portion of the metal deposition layer 34.
The Finally, the finished wafer 31 is scribed.
The required semiconductor chip IC element 1 shown in FIGS.
A to 1E are obtained. Incidentally, in the method of forming the rewiring layer 3 of this example,
However, as a means for forming the metal plating layer 39, an electroplating method is used.
However, instead of this configuration, use electroless plating.
The metal plating layer 39 can also be formed. This
In this case, an electrode is required to form the metal plating layer 39.
When exposing the photoresist layer 35, there is no electrode
The formation of the part 37 and the formation of the lead part 38 become unnecessary. The method of forming the rewiring layer 3 of this example is the first method.
It has the same effect as the method of forming the rewiring layer 3 according to the example.
Or a process for forming a conductive pattern on the finished wafer 31.
Since the number can be reduced, coil-on-chip or CSP
Type semiconductor chips can be manufactured more efficiently.
Yes. <First Example of Semiconductor Device> Next, the present invention relates to
A first example of a semiconductor device will be described with reference to FIG.
FIG. 12 is a sectional view of the semiconductor device 40 according to the first embodiment.
It is. The semiconductor device 40 according to the first embodiment is as follows.
As shown in FIG. 12, the coil-on-chip type half
Conductor chip 1A or 1B is bonded to adhesive layer 41 and two covers.
-Casing in a base made of sheet 42
Features. As an adhesive constituting the adhesive layer 41,
Any known one that has the required adhesive strength
Can be used, but is excellent in mass productivity
It is especially preferred to use hot melt adhesives
Yes. The cover sheet 42 has a required strength and mark.
Any sheet material that is publicly known as long as it has printability
For example, polyethylene terf
High generation of harmful substances even when incinerated like tarate
It is particularly preferable to use a molecular sheet or paper. Half of this example
The conductor device 40 is a first device in which an adhesive layer 41 is formed on one side.
On the adhesive layer 41 of the cover sheet 42 of the semiconductor chip 1
A or 1B is fixed, and then the first cover sheet
An adhesive layer 41 is formed on one side of the semiconductor chip bonding surface of 42.
Bonding the adhesive layer 41 of the formed second cover sheet 42
Can be formed. The semiconductor device 40 of this example includes an analog circuit 2
1 and antenna coil 4 overlap with each other through insulating layer 2
Equipped with semiconductor chips 1A or 1B arranged so as not to
Therefore, between the analog circuit 21 and the antenna coil 4
Parasitic capacitance is not formed in the analog circuit 21 and acts on the analog circuit 21
Generation of capacitance noise can be prevented. Also,
The analog circuit 21 and the antenna coil 4 are arranged opposite to each other.
Electromagnetic induction noise acting on the analog circuit 21
Can be prevented. Therefore, these electrostatic
Crosstalk caused by inductive noise or electromagnetic induction noise
Noise, ringing and power supply noise are prevented.
Coil-on-chip type semiconductor chip 1A or 1
Can improve communication characteristics of non-contact semiconductor devices equipped with B
The In addition, the required semiconductor chip 1A or 1B is transferred to two sheets.
It can be manufactured simply by casing with the bar sheet 42.
Therefore, it can be manufactured at a low cost and in a very small size. <Second Example of Semiconductor Device> Next, the present invention relates to the present invention.
A second example of a semiconductor device based on FIG. 13 and FIG.
explain. FIG. 13 shows a semiconductor device according to the second embodiment.
FIG. 14 is a cross-sectional view of the semiconductor device according to the second embodiment.
It is a top view of the booster coil obtained. The semiconductor device 50 according to the second embodiment is as follows.
As shown in FIG. 13, the coil-on-chip type half
Conductor chip 1A or 1B and these semiconductor chips 1A
Or antenna coil 4 integrally formed on 1B
Electromagnetic coupling with the antenna coil provided in the reader / writer
The booster coil 51 for strengthening the joint is formed.
The edge substrate 52, the adhesive layer 41, the cover sheet 42, etc.
It is characterized by being casing in a substrate. The booster coil 51 is as shown in FIG.
In addition, the first coil 51a having a small winding diameter and the second coil having a large winding diameter.
The coil 51b and are electrically connected to each other.
The The first coil 51a is connected to the semiconductor chip 1A or 1B.
Mainly electromagnetically coupled to the integrally formed antenna coil 4
It is a coil, its planar shape and dimensions are semiconductor chips
Same as antenna coil 4 formed integrally with 1A or 1B
Or it is formed in a similar shape. On the other hand, the second coil 51b is
Mainly electromagnetic connection with the antenna coil provided in the reader / writer
The planar shape and dimensions of the coil
In the substrate constituted by the layer 41 and the cover sheet 42
It is formed as large as possible within a range that fits within the range. Note that FIG.
In the example of 4, the first coil 51a and the second coil 51b are
Both are formed in a rectangular spiral shape with multiple turns
The number of turns and the plane of each coil 51a, 51b
The shape is not limited to this, and is arbitrarily formed
be able to. This booster coil 51 is connected to the insulating substrate 5
Etch the conductive metal layer of uniform thickness formed on one side of 2.
Etching to form the required coil pattern
Or using conductive ink on one side of the insulating substrate 52.
Formed by a printing method that prints the essential coil pattern
can do. It should be noted that the type of adhesive constituting the adhesive layer 41
Types of sheet materials constituting the cover sheet 42
Is the same as the semiconductor device 40 according to the first embodiment.
Since there is, the description is omitted to avoid duplication. The semiconductor device 50 of this example is the first embodiment example.
In addition to having the same effect as the semiconductor device 40 according to FIG.
Since a static coil is provided, the semiconductor chip 1A or 1B
An integrally formed antenna coil 4 and a reader (not shown)
By strengthening the electromagnetic coupling with the antenna coil
There is an effect that can. <Third Example of Semiconductor Device> Next, the present invention relates to
A second example of the semiconductor device will be described with reference to FIG.
FIG. 15 is a cross-sectional view of a principal part of a semiconductor device according to the third embodiment.
It is. The semiconductor device 60 according to the third embodiment is as follows.
As shown in FIG. 15, the first wiring layer 61 and the first insulating layer 6
2, second wiring layer 63, first wiring layer 61 and second wiring layer 63
Connecting portion 63a, second insulating layer 64, semiconductor chip
1C, other mounting components 66, the second wiring layer 63 and the semiconductor
Conductor 67 connecting the chip 1C, the second wiring layer 63 and others
Conductor 68 for connecting the mounting component 66 of the semiconductor chip 1
C, other mounting parts 66 and conductors 67 and 68 are sealed together.
Mold resin 69 and locally on the outer surface of the first wiring layer 61
The formed nickel layer (metal film) 70, first wiring layer 61
Formed on the protective resin layer 71 and the nickel layer 70 covering the outer surface of
The external terminal 72 is configured. First wiring layer 61, second wiring layer 63 and connection
The part 63a is formed by electroplating (electroforming) copper or a copper alloy.
And formed by. Copper alloys include corrosion resistance and dense
Copper-nickel alloy or copper-
Nickel-silver alloys are particularly suitable. The connection part 63a is the first
Formed in the first opening 62a provided in the insulating layer 62.
Electrically connecting the first wiring layer 61 and the second wiring layer 63.
To do. First insulating layer 62, second insulating layer 64 and protection
The resin layer 71 is made of an insulating resin. In addition,
As the insulating resin, the first insulating layer 62 and the second insulating layer are used.
In order to facilitate the formation of the layer 64 and the protective resin layer 71,
A light-sensitive resin can also be used. The first insulating layer 62 includes
The first opening 62a for forming the connection part 63a is required.
The second insulating layer 64 includes conductors 67 and 6.
The second openings 64a for penetrating 8 are formed in the required arrangement
Made. Another mounted component 66 is a transistor.
Diode, resistor, inductor, capacitor, crystal
Oscillator, filter, balun, antenna, functional module
Such as chip parts and external connection connectors
You can. The functional module includes a VCO,
A PLL or a power supply regulator is included. The other mounting component 66 and the second wiring layer 63 are in contact with each other.
As the conductor 68 to be continued, a conductive paste or anisotropic conductive contact is used.
Adhesives can be used, but they are inexpensive and reliable.
Solder is particularly suitable because of the high connection possible. Mold resin 69 is used for the semiconductor chip 1.
C, other mounted components 66, and these mounted components 1C, 6
6 and the connection portion of the second wiring layer 63 are integrally resin-sealed.
Conventionally applied to resin sealing of semiconductor chips
It can be formed using various resin materials
The The nickel layer 70 forms the external terminals 72.
To facilitate forming the external terminal 72
Formed in the terminal portion of the first wiring layer 61. The external terminal 72 is a semiconductor according to this embodiment.
Connecting body device 60 to an external device such as a printed wiring board
Used to make it cheap and reliable
Because it is easy to make a high connection, it is formed with solder
It is particularly preferred. The semiconductor device 60 of this example is related to the first embodiment.
In addition to the same effects as the semiconductor device 40, the mounted components
1C, 66 wiring means 61, 63 and protective resin layer
62, 64, so the core of the conventional multilayer substrate
The part corresponding to the material can be omitted, and it is thin and safe.
Inexpensive semiconductor device can be obtained. Also, the wiring layer 6
1 and 63 were used, so lead frame and metal foil etching
Wiring layer formed by printing or conductive paste printing
High-density wiring pattern compared to using a printed circuit board
, High precision, miniaturization and homogenization
To obtain a high-frequency compatible semiconductor module
You can. Furthermore, the first wiring layer 61 and the electrical connection therewith
Since the second wiring layer 63 connected to is formed in two layers,
The formation area of the wiring layers 61 and 63 can be reduced, and half
The conductor device can be miniaturized. In the above embodiment, two wiring layers are used.
Of course, it is possible to form more than three layers.
is there. In the embodiment, as a semiconductor chip
CSP type semiconductor chip 1C was used, but other CS
P type semiconductor chips 1D and 1E can also be used.
The As described above, according to the present invention,
An analog circuit formed on the circuit forming surface of the semiconductor chip;
Arrangement so that the rewiring layer does not overlap with the insulating layer
Therefore, there is a parasitic capacitance between the analog circuit and the redistribution layer.
Capacitive noise that does not form and acts on analog circuits
Occurrence can be prevented. Also, analog circuit and re-
Since it is not placed opposite to the wiring layer,
Generation of electromagnetic induction noise to be used can be prevented.
Therefore, it is caused by these electrostatic induction noise or electromagnetic induction noise.
Crosstalk noise, ringing and power supply noise
Etc., and re-wiring layer integrated semiconductor for high frequency
For body chips, malfunctions and communication characteristics caused by noise
The deterioration of sex can be eliminated. In addition, according to the present invention, it is necessary for a completed wafer.
Scribing the finished wafer after forming the rewiring layer
Each semiconductor chip to obtain the required semiconductor chip.
Compared to the case where a rewiring layer is formed on the coil
Or manufacture CSP type semiconductor chips with high efficiency.
Can reduce the manufacturing cost of semiconductor chips.
it can. Also, all semiconductor chips formed on the finished wafer
Rewiring layer with uniform thickness is formed with high accuracy to the
Therefore, it is possible to reduce the variation in communication characteristics.
You can. In addition, individual semiconductor chips
The rewiring layer is formed by using the sputtering method, vacuum deposition method or plating method.
Once formed, unnecessary conductors adhere to the outer periphery of the semiconductor chip.
However, the insulation of the semiconductor chip becomes a problem, but the finished wafer
When a rewiring layer is formed on the
Even if unnecessary conductors adhere to the outer periphery of the finished wafer,
It is a part that should be disposed of as an unnecessary part
Adversely affect the insulation of individual semiconductor chips.
Nor.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a plan view of a semiconductor chip 1A according to a first embodiment. FIG. 2 is a cross-sectional view taken along the line AA of FIG. FIG. 3 is a plan view of a semiconductor chip 1B according to a second embodiment. FIG. 4 is a plan view of a semiconductor chip 1C according to a third embodiment. 5 is a cross-sectional view taken along the line BB in FIG. FIG. 6 is a plan view of a semiconductor chip 1D according to a fourth embodiment. FIG. 7 is a plan view of a semiconductor chip 1E according to a fifth embodiment. FIG. 8 is a plan view of a so-called completed wafer completed through a predetermined process. FIG. 9 is a process diagram showing a first example of a method for forming a rewiring layer. FIG. 10 is a plan view of a completed wafer on which a rewiring layer 3 is formed. FIG. 11 is a process diagram showing a second example of a method for forming a rewiring layer. FIG. 12 is a cross-sectional view of the semiconductor device according to the first embodiment. FIG. 13 is a cross-sectional view of a semiconductor device according to a second embodiment. FIG. 14 is a plan view of a booster coil provided in the semiconductor device according to the second embodiment. FIG. 15 is a fragmentary cross-sectional view of a semiconductor device according to a third embodiment; FIG. 16 is a plan view of a conventional coil-on-chip type semiconductor chip. FIG. 17 is a cross-sectional view of a conventional coil-on-chip type semiconductor chip. FIG. 18 is a plan view of a conventional CSP type semiconductor chip. FIG. 19 is a cross-sectional view of a conventional CSP type semiconductor chip. FIG. 20 is an explanatory diagram of parasitic capacitance formed between a circuit portion of a semiconductor chip and an antenna coil. [Description of Symbols] 1A to 1E Semiconductor chip 2 Insulating layer 3 Redistribution layer 4 Antenna coil 6 Bump formation wiring 11 Power supply circuit 12 Operational amplifier 13 Comparison amplifier 14 RF reception unit 15 RF transmission unit 16 RF synthesizer unit 21 Analog circuit 40 , 50, 60 Semiconductor devices

──────────────────────────────────────────────────── ─── Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme code (reference) G06K 19/00 H M H01L 27/04 E (72) Inventor Kazunari Nakagawa 1-chome, Ibaraki-shi, Osaka 1 No. 88 Hitachi Maxell Co., Ltd. (72) Inventor Yoshiharu Hino 1-88 Sakai 1-chome, Ibaraki-shi, Osaka No. 88 Hitachi Maxell Co., Ltd. F-term (reference) 5B035 AA11 BA03 BA05 BB09 CA01 CA08 CA23 CA31 5F033 HH07 HH08 HH09 HH11 HH12 JJ01 JJ07 JJ08 JJ09 JJ11 JJ12 MM08 MM21 NN06 PP15 PP19 PP27 PP28 QQ08 UU03 VV00 VV07 VV08 XX24 5F038 AZ04 AZ05 BH19 CA03 CA05 CA10 DF12 EZ20

Claims (1)

1. A semiconductor device comprising: a completed wafer having a plurality of semiconductor chip circuits formed on a circuit forming surface; and an insulating layer on the circuit forming surface of the completed wafer. Forming a rewiring layer that does not overlap with all or part of the analog circuit included in the circuit, and then scribing the completed wafer on which the rewiring layer is formed to obtain a required semiconductor chip. A method for manufacturing a semiconductor chip.