JP2003209093A - Substrate treatment method and substrate treatment device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a substrate treatment method and a substrate treatment device in which the line width or the like of a resist pattern really formed in a photo-lithography process can be precisely measured and a desired circuit pattern can be finally formed after etching. <P>SOLUTION: After the line width or the like of the resist pattern is measured (step 11) by recognizing the pattern after developing (step 10), the measured result is fed forward to etching (step 13) to be performed later and by performing etching in optimal treatment conditions, the precise circuit pattern can be finally formed. Besides, by using an optical observation apparatus utilizing the interference and refraction of light, without shrinking the resist pattern like the conventional case of recognizing the resist pattern by using an electron microscope, the line width can be precisely measured in a nondestructive manner. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a substrate processing method and a substrate processing apparatus for forming a desired circuit pattern on a semiconductor substrate in manufacturing a semiconductor device, particularly in a photolithography process and an etching process.

[0002]

2. Description of the Related Art In a photolithography process in the manufacture of semiconductor devices, a resist film is formed on the surface of a semiconductor wafer (hereinafter referred to as "wafer"), which is then exposed to a predetermined pattern and further developed. As a result, a desired resist pattern is formed. Also,
After this photolithography process, an etching process is performed to form a desired circuit pattern. Then, after the etching process, the circuit wiring is formed by peeling off the resist on the pattern.

The photolithography process has conventionally been provided integrally with a coating and developing treatment apparatus having a resist coating treatment unit and a developing treatment unit for supplying a developing solution to a wafer to perform development treatment, and to this apparatus. The exposure device is used. The coating and developing treatment apparatus is also integrally provided with a heat treatment unit, a cooling treatment unit, and the like for thermally treating the wafer. On the other hand, the etching process is performed by an etching device different from the coating and developing treatment device. The etching apparatus and the coating / development processing apparatus are not integrated with each other. For example, a worker carries a wafer after the photolithography process to the etching apparatus and performs the etching processing.

By the way, in recent years, the miniaturization of circuit patterns has been further advanced, and for example, the line width of patterns has been required to be managed more precisely.
Therefore, in the coating and developing treatment apparatus, in order to obtain a desired resist pattern line width, the processing conditions of the development processing unit and the heat treatment unit, which may affect the variation of the pattern line width, are strictly regulated for each unit. Manage.

[0005]

However, the desired line width may not be obtained even under such strict control, and in such a case, the desired circuit pattern may be obtained in the subsequent etching step. I can't.

Further, in order to solve such a problem,
The resist pattern of the wafer that has undergone the photolithography process in the coating / developing apparatus is observed by an observing apparatus such as an SEM (scanning electron microscope), and the observation result is fed back to the coating / developing apparatus to obtain the line width and the like. Are in control. However, in an observation apparatus such as an electron microscope, an electron beam is used, and the pattern width is contracted by irradiating the resist pattern with the electron beam. Therefore, the actually formed line width cannot be measured. Therefore, even if this measurement result is fed back, it is not easy to form a resist pattern having a desired line width.

In view of the above circumstances, an object of the present invention is to accurately measure the line width and the like of a resist pattern actually formed in a photolithography process, and finally obtain a desired circuit pattern after etching. It is to provide a substrate processing method and a substrate processing apparatus that can be formed.

[0008]

In order to achieve the above object, the substrate processing method according to the first aspect of the present invention comprises forming a resist pattern on a substrate and then performing an etching process to obtain a desired circuit pattern. The substrate processing method for forming a substrate includes the steps of (a) recognizing the resist pattern and (b) controlling the etching processing conditions based on the recognition result.

In the present invention, the resist pattern is recognized and the line width of the pattern is measured. Then, this measurement result is fed forward to the etching process to be performed thereafter, and the etching process is performed under the optimum processing condition, whereby a precise circuit pattern can be finally formed. In this case, the etching processing conditions include at least one of etching time, etching gas composition ratio, and etching power. In particular, regarding the etching time, it is known that there is a clear correlation that the line width can be reduced as the time is longer. Therefore, the circuit pattern having a desired line width can be easily formed by controlling the etching time.
Further, the present invention can be carried out both in the actual product manufacturing stage and in the initial setting stage before the product manufacturing by using the substrate for inspection.

Further, the step (a) does not cause shrinkage of the resist pattern as in the case of recognizing the resist pattern using an electron microscope by using an optical observation device, and is nondestructive. The line width can be measured with. As a result, the line width of the actual resist pattern can be accurately measured and the etching processing conditions can be accurately grasped, which contributes to the formation of a desired circuit pattern.

According to one aspect of the present invention, the step (a) includes the step (c) of recognizing a grating pattern formed in a region other than the product region on the substrate by the optical observation device. (D) a step of recognizing the grating pattern and the resist pattern formed in the product area with an electron microscope, and obtaining a correlation between the grating pattern and the resist pattern, and (e)
A step of obtaining a correlation between the grating patterns recognized in the step (c) and the step (d), and (f) recognizing the resist pattern based on the respective correlations obtained in the steps (d) and (e). And a process.

In the present invention, for example, when the actually formed resist pattern has a complicated shape, light interference does not occur and the line width cannot be measured by the above optical observation apparatus. Electron microscope. In this case, for example, first, a substrate for inspection is used, and a grating pattern formed in a region other than the product region of the substrate is recognized by the optical observation device. For this, it is preferable to form a pattern having a size large enough to cause optical interference in a region other than the product region in advance, for example, during the exposure process. Next, the grating pattern and the actual resist pattern formed in the product area are recognized by an electron microscope, and the correlation between them is obtained. Then, by obtaining the correlation between the grating patterns respectively recognized by the optical observation device and the electron microscope, the resist pattern is recognized based on each obtained correlation.

Thus, for example, the correlation between grating patterns is obtained for a plurality of substrates or a plurality of chips, a database of these is constructed, and only the optical observation device is used based on this database to determine the grating pattern. By recognizing only this, the line width of the actual resist pattern can be accurately measured nondestructively. The database is preferably constructed, for example, by using an inspection board.

A substrate processing method according to a second aspect of the present invention is the substrate processing method for forming a desired circuit pattern by forming a resist pattern on a substrate and then performing an etching process. Recognizing the pattern with the first optical observation device; (b) controlling the etching processing conditions based on the recognition result; and (c) a circuit on the substrate that has been etched under the control. Recognizing the pattern with the second optical observation device.

In the present invention, by recognizing the resist pattern with the first optical observation device and measuring the line width of the pattern, the resist pattern can be recognized nondestructively and the line width can be precisely measured. it can. Next, this measurement result is fed forward to an etching process to be performed thereafter, and the etching process is performed under optimum processing conditions, whereby a precise circuit pattern can be finally formed.

Further, the formed circuit pattern is second
By recognizing with the optical observation device of, it can be used as a common database between the first and second optical observation devices, and the inspection efficiency can be improved. For example, by recognizing the circuit pattern after the etching process based on the database of the grating pattern recognized by the first optical observation device, the circuit pattern can be recognized efficiently, non-destructively, and precisely.

A substrate processing apparatus according to a first aspect of the present invention recognizes the resist pattern in the substrate processing apparatus which forms a resist pattern on a substrate and transfers the substrate to an etching apparatus to form a desired circuit pattern. And a means for controlling the etching processing conditions based on the recognition result.

A substrate processing apparatus according to a second aspect of the present invention recognizes the resist pattern in the substrate processing apparatus which forms a resist pattern on a substrate and transfers the substrate to an etching apparatus to form a desired circuit pattern. A first optical observation apparatus for controlling the processing conditions of the etching based on the recognition result, and a second optical observation apparatus for recognizing a circuit pattern on the substrate etched under the control. And.

Further features and advantages of the present invention will become more apparent with reference to the accompanying drawings and the description of the embodiments of the invention.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

1 to 3 are views showing the overall construction of a coating and developing treatment apparatus and an etching apparatus according to the first embodiment of the present invention. FIG. 1 is a plan view thereof, and FIGS. 2 and 3 show coating. FIG. 3 is a front view and a rear view of the development processing apparatus.

In the coating and developing treatment apparatus 1, a plurality of semiconductor wafers W as substrates to be treated are loaded into or out of the apparatus 1 from the outside in units of a plurality of wafer cassettes CR, for example, 25 wafers. Cassette station 10 for loading and unloading wafers W
Further, a processing station 12 in which various single-wafer processing units that perform a predetermined process on the wafer W one by one in the coating and developing process are arranged in multiple stages at predetermined positions, and is provided adjacent to the processing station 12. The interface unit 14 for transferring the wafer W to and from the exposure apparatus 100 is integrally connected.

In the cassette station 10, as shown in FIG. 1, a plurality of wafer cassettes CR, for example, five wafer cassettes CR are located at the positions of the projections 20a on the cassette mounting table 20, with their respective wafer entrances / outlets facing the processing station 12 side in the X direction. The wafer carriers 22 placed in a row and movable in the cassette arrangement direction (X direction) and in the wafer arrangement direction (Z direction) of the wafers stored in the wafer cassette CR selectively access each wafer cassette CR. It is like this.
Further, the wafer carrier 22 is configured to be rotatable in the θ direction so that it can also access a heat treatment system unit belonging to the third processing unit section G3 having a multi-stage configuration described later as shown in FIG. It has become.

As shown in FIG. 1, the processing station 12
The third processing unit section G3, the fourth processing unit section G4, and the fifth processing unit section G5 are arranged from the cassette station 10 side on the rear side of the apparatus (upper side in the drawing). Unit part G3 and 4th
The first main wafer transfer device A1 is provided between the first main wafer transfer device A1 and the processing unit part G4. As will be described later, in the first main wafer transfer device A1, the first main wafer transfer body 16 includes a first processing unit section G1, a third processing unit section G3, a fourth processing unit section G4, and the like. Are installed to allow selective access to. Further, a second main wafer transfer apparatus A2 is provided between the fourth processing unit section G4 and the fifth processing unit section G5, and the second main wafer transfer apparatus A2 is the same as the first main wafer transfer apparatus A2. The second main wafer carrier 17 is installed so as to selectively access the second processing unit section G2, the fourth processing unit section G4, the fifth processing unit section G5, and the like.

Further, a heat treatment unit is installed on the back side of the first main wafer transfer device A1, and, for example, an adhesion unit (A) for hydrophobizing the wafer W.
D) 110, a heating unit (HP) for heating the wafer W
As shown in FIG. 3, 113 is superposed in two stages in order from the bottom. The adhesion unit (AD) may be configured to further have a mechanism for controlling the temperature of the wafer W.
On the back side of the second main wafer transfer device A2, there is a peripheral exposure device (WE) that selectively exposes only the edge portion of the wafer W.
E) 120, a film thickness inspection device 119 for inspecting the resist film thickness applied on the wafer W, and an optical observation device (OCD) 40 according to the present invention are provided in multiple stages.

The optical observation device 40 recognizes a resist pattern by, for example, diffraction and interference of light, performs pattern matching with a calculation pattern (library), and sets the coincident calculation pattern as an actual pattern. It is a thing. A heat treatment unit (HP) 113 may be arranged on the back side of the second main wafer transfer apparatus A2 as in the back side of the first main wafer transfer apparatus A1.

As shown in FIG. 3, in the third processing unit section G3, an oven type processing unit for carrying out a predetermined processing by placing the wafer W on a mounting table, for example, a high temperature for carrying out a predetermined heating processing on the wafer W A heating processing unit (BAKE), a cooling processing unit (CPL) for performing cooling processing on the wafer W with accurate temperature control, and a transition unit (transfer unit for transferring the wafer W from the wafer carrier 22 to the main wafer carrier 16). TRS), and a transfer / cooling processing unit (TCP), which is separately arranged in the upper and lower two stages of the transfer part and the cooling part, is stacked in order from the top, for example, in ten stages. In the third processing unit section G3,
In this embodiment, the third stage from the bottom is provided as a spare space. Also in the fourth processing unit section G4, for example, a post-baking unit (POST), a transition unit (TRS) that serves as a wafer transfer section, a pre-baking unit (PAB) that heat-treats the wafer W after the resist film formation, and a cooling processing unit. (CPL) are stacked, for example, in 10 steps from the top. Further, in the fifth processing unit section G5, for example, a post-exposure baking unit (PEB) for performing a heating process on the exposed wafer W, a cooling processing unit (CPL), and a transition unit (TRS) serving as a transfer section for the wafer W. )
Are stacked in 10 layers in order from the top.

In FIG. 1, a first processing unit section G1 and a second processing unit section G2 are provided side by side in the Y direction on the front side (downward in the figure) of the processing station 12. Between the first processing unit section G1 and the cassette station 10 and between the second processing unit section G2 and the interface section 14, as shown in FIG. 2, the respective processing unit sections G1 and G2 supply. Liquid temperature control pumps 24 and 25 used for temperature control of the processing liquid are provided respectively, and further, clean air from an air conditioner (not shown) provided outside the coating and developing processing apparatus 1 is supplied to each processing unit section. G
1 to G5 are provided with ducts and the like (not shown) for supplying the inside.

As shown in FIG. 2, in the first processing unit section G1, five spinner type processing units for placing the wafer W on the spin chuck in the cup CP and performing a predetermined processing,
For example, a resist coating processing unit (COT) that forms a resist film on a wafer has three stages, and a bottom coating unit (BARC) that forms an antireflection film to prevent reflection of light at the time of exposure has two stages from below. They are stacked in five steps in order. Similarly, in the second processing unit section G2, five spinner type processing units, for example, development processing units (DEV) are stacked in five stages. In the resist coating processing unit (COT), draining of the resist solution is troublesome both mechanically and in terms of maintenance. Therefore, it is preferable to arrange the resist solution in the lower stage. However, it is also possible to arrange them in the upper stage if necessary.

Further, the first and second processing unit sections G1
At the bottom of G2 and G2, there are processing unit sections G1 and G2.
The chemical chamber (CH
M) 26 and 27 are provided respectively.

A portable pickup cassette CR and a stationary buffer cassette BR are arranged in two stages on the front surface of the interface unit 14, and the wafer carrier 2 is arranged in the central portion.
7 is provided. This wafer carrier 27 is composed of X, Z
By moving in the direction, both cassettes CR and BR can be accessed. Further, the wafer carrier 27 is configured to be rotatable in the θ direction so that it can also access the fifth processing unit section G5. Further, as shown in FIG. 3, a plurality of high-precision cooling processing units (CPL) are provided on the back surface of the interface section 14, for example, two upper and lower stages. The wafer transfer body 27 can also access this cooling processing unit (CPL).

Referring to FIG. 1, the second processing unit section G
An etching device 50 according to the present invention is arranged on the front side of the second unit 2. A wafer transfer device 30 that transfers a wafer to the etching processing device 50 and the development processing unit (DEV) in the processing unit part G2 is provided between the etching device 50 and the second processing unit part G2. . This wafer transfer device 30 can access the inside of the development processing unit by opening the shutter 49 provided in the development processing unit (DEV), and can take out the wafer subjected to the development processing. Since the shutter 49 as described above is also provided in each of the other processing units, the inside of the processing chamber is sealed during the processing of the wafer in each unit, and the shutter is opened. As a result, the wafer carriers 22 and 27 and the main wafer carriers A1 and A2 can access the respective predetermined units. Further, the etching device 50 may be configured in multiple stages in accordance with the multi-stage development processing unit (DEV). In this case, it is preferable that the wafer transfer device 30 be configured to be vertically movable in the Z direction.

FIG. 4 is a perspective view showing the first main wafer transfer device A1. Since the second main wafer transfer device A2 is the same as the first main wafer transfer device A1, its description is omitted.

As shown in FIG. 1, the main wafer transfer device A1
Is surrounded by the housing 41 to prevent particles from entering. In FIG. 4, the illustration of the housing 41 is partially omitted for clarity of explanation.

As shown in FIG. 4, poles 33 are vertically provided at both ends of the main wafer transfer device A1, and the main wafer transfer body 16 (17) extends vertically (Z direction) along the poles 33. It is arranged to be movable. The wafer W is held on the carrier base 55 of the main wafer carrier 16 3
Two tweezers 7a to 7c are provided, and these tweezers 7a to 7c are configured to be movable in the horizontal direction by a drive mechanism (not shown) built in the transport base 55. Below the transport base 55, a support member 45 that supports the transport base 55 is provided with a rotating member 46 that is rotatable in the θ direction.
Connected through. As a result, the wafer carrier 1
6 is rotatable in the θ direction. A flange portion 45a is formed on the support body 45, and the flange portion 45a is slidably engaged with a groove 33a provided in the pole 33, and is slidable by a belt drive mechanism incorporated in the pole 33. It is provided. As a result, the main wafer carrier 16 can move vertically along the pole 33.

At the bottom of the main wafer transfer device A1,
For example, four fans 36 for controlling the atmospheric pressure and temperature / humidity inside the transport device A1 are provided.

The etching apparatus 50 is, for example, a parallel plate type plasma etching apparatus, and FIG. 5 shows a sectional view of the etching apparatus 50. A pair of electrode plates 43 and 44 is arranged in the chamber 37, a radio frequency (RF) power source 48 is connected to the upper electrode 44, and the lower electrode 43 is grounded. Below the lower electrode 43, for example, three support pins 47 that support the substrate are arranged so that they can be moved up and down by an up-and-down drive motor 42. The chamber 37 is provided with a supply port 38 for supplying the gas from the gas supply source 34 into the chamber 37.
A vacuum pump 28 that vacuums the inside of the chamber 37 is provided in the lower part of the. An opening 37a for transferring a substrate to and from the wafer transfer device 30 is formed on a side surface of the chamber 37, and the opening 36a is configured to be opened and closed by a shutter member 39.

Here, with reference to FIG.
Etching time of this etching device 50, etching
At least 1 of gas composition ratio and etching power
It is designed to control one. Used for this etching
The gas species used is, for example, CF _Four, O_Two, N_Two, Ar, C
HF_Three, SF₆Gases such as etc. are mixed and used in combination
It is possible. These etching times,
Each processing such as etching gas composition ratio and etching power
The conditions are the resist pattern recognized by the optical observation device 40.
It is designed to be controlled based on the line width of the turn.

FIG. 6 is a conceptual block diagram of the optical observation device 40. The optical observation device 40 includes an optical system 61 indicated by a broken line. The optical system 61 is arranged so as to reflect, for example, a xenon lamp 62 that emits white light and the light from the xenon lamp 62 in a downward right direction. The half mirror 56, the lens 54 that guides the light reflected by the half mirror 56 to the resist pattern formed on the surface of the wafer W, and the detector 57 that detects the reflected diffracted light from the wafer W. Further, the optical observation device 40 is provided with a stage 53 on which the wafer W is placed, and is also connected with a processing unit 11 for processing the detection result of the detector 57. The optical system 61 is configured to be movable in a direction parallel to the surface direction of the wafer W (X-Y direction) by a drive mechanism (not shown), and irradiates light on each chip formed on the wafer W for observation. You can do it.

The processing section 11 derives a diffraction pattern corresponding to the detection result 32 by the detector 57 and the state of the resist pattern (for example, line width, pitch between patterns, height, etc.) by calculation (simulation). The calculation unit 59, the storage unit 58 that stores the plurality of diffraction patterns derived by the calculation unit 59, and the detection result 32 and the plurality of diffraction patterns stored in the storage unit 58 are compared, and the comparison is performed. Of the plurality of diffraction patterns, one diffraction pattern corresponding to the detection result 32 is stored as the measurement result in the storage unit 5.
8 and the analysis part 52 which extracts from 8. As a result, the optical observation device 40 can detect the detection result 32 and the storage unit 5.
It is possible to perform pattern matching with the calculated pattern (library) stored in 8, and regard the matched calculated pattern as an actual pattern. As a more specific example, in the present embodiment, for example, scatterometry (Sc
The pattern matching is performed by the technique of “atterometry”.

Next, a series of processing steps of the coating and developing processing apparatus 1 described above will be described with reference to the flow shown in FIG.

First, in the cassette station 10, the wafer carrier 22 accesses the cassette CR which contains the unprocessed wafer W on the cassette mounting table 20, and takes out one wafer W from the cassette CR.
Then, the wafer W is then transferred to the first main wafer transfer device A1 via the transfer / cooling processing unit (TCP) and transferred to the bottom coating unit (BARC). Then, here, an antireflection film is formed to prevent reflection of exposure light from the wafer during exposure (step 1).

Next, the wafer W is transferred to the baking processing unit in the third processing unit section G3 and subjected to a predetermined heat treatment at 120 ° C. (step 2), for example.
After a predetermined cooling process is performed in the cooling process unit (CPL) (step 3), a desired resist film is formed on the wafer W in the resist coating process unit (COT) (step 4).

When the resist film is formed, the wafer W is transferred to the pre-baking unit (PAB) by the first main wafer transfer device A1 and subjected to predetermined heat treatment and temperature control treatment at, for example, about 100 ° C. ( Step 5).

Next, the wafer W is cooled by the cooling processing unit (CP
L) is cooled at a predetermined temperature (step 6). After that, the wafer W may be taken out by the second main transfer device A2 and transferred to the film thickness inspection device 119 to measure the resist film thickness. The wafer W is then transferred to the transition unit (T
The exposure apparatus 1 via the RS) and the interface unit 14.
00, and exposure processing is performed there (step 7).

Next, the wafer W has the interface section 14
And, after being transferred to the second main transfer device A2 via the transition unit (TRS) in the fifth processing unit section G5, they are transferred to the post-exposure baking unit (PEB), where a predetermined heat treatment and temperature are applied. Toning processing is performed (step 8). Thereafter, a predetermined cooling process is performed in the cooling process unit (CPL) (step 9). After the exposure process is completed, the wafer W may be temporarily stored in the buffer cassette BR in the interface section 14. Then, the wafer W is processed by the development processing unit (DE
V) and development processing is performed (step 10).

Next, the wafer W is carried into the optical observation device 40 via the second main wafer transfer device A2, where the resist pattern is recognized and the line width of the resist pattern is measured (step 11). . Here, as described above, based on the measured line width, for example, the etching device 50
Etching processing conditions such as the etching time in step 2 are set (step 12). The wafer W is, for example, the second
The wafer is carried into the etching apparatus 50 through the processing unit section G2 and the wafer transfer apparatus 30 and etched under the processing conditions set above (step 13).

FIG. 8 shows the relationship between the etching time and the line width of the circuit pattern formed by etching. Thus, it is known that the line width becomes smaller as the etching time becomes longer. Therefore, when the line width measured by the optical observation device 40 is larger than a predetermined value, by performing control such as making the etching time longer than the predetermined time,
A circuit pattern having a desired line width can be easily formed.

FIG. 9 shows the relationship between the etching power and the line width of the circuit pattern formed by etching. Also in this case, it is known that the line width becomes smaller as the etching power becomes larger, like the etching time.
By controlling this etching power, it is possible to easily form a circuit pattern having a desired line width. However, if necessary, the composition ratio of the etching gas may also be controlled in a composite manner.

When the etching is completed, the wafer W is taken out by the second main carrier A2 via the wafer carrier 30 and the second processing unit G2. Then, the transition unit (TRS) in the fourth processing unit section G4, the first main wafer transfer device A1, the third
Of the transition unit (T
It is returned to the wafer cassette CR in the cassette station 10 via RS) and the wafer carrier 22.

After the development processing, a predetermined heat treatment may be performed by a post baking unit (POST).

As described above, in this embodiment, after the resist pattern after development is recognized and the line width of the pattern is measured, the measurement result is fed forward to the etching process to be performed thereafter, and the optimum process is performed. By performing the etching process under the conditions, a precise circuit pattern can be finally formed.

Further, regarding the relationship between the etching time and the line width, it is known that there is a clear correlation as shown in FIG. 8. Therefore, the desired line width can be easily controlled by controlling the etching time. A circuit pattern having the same can be formed. Further, the present embodiment can be executed both in the case of manufacturing using an actual product wafer and in the case of initial setting before manufacturing a product using an inspection wafer.

Further, in the present embodiment, by using the optical observation device 40 utilizing the interference and diffraction of light, the contraction of the resist pattern is reduced as in the conventional case where the resist pattern is recognized by using an electron microscope. The line width can be measured non-destructively without being generated. As a result, the line width of the actual resist pattern can be accurately measured and the etching processing conditions can be accurately grasped, which contributes to the formation of a desired circuit pattern.

Further, the optical observation device 40 is smaller in size than an electron microscope such as an SEM and does not require vacuum processing or the like unlike the electron microscope, so that it can be easily installed inline as in the present embodiment. You can Further, the optical observation device 40 has an advantage that the device cost is lower than that of the electron microscope, and the throughput is higher than that of the electron microscope.

FIG. 10 is a plan view of a coating and developing treatment apparatus, an etching apparatus and the like according to the second embodiment of the present invention. In FIG. 10, the same components as those in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted. Further, in the present embodiment, since the formed resist pattern has a complicated shape, when the line width or the like cannot be measured, the resist pattern is formed using the inspection wafer, and the line width or the like is measured by an SEM or the like. The case of recognizing with a microscope will be described.

In this embodiment, the same two optical observation and observation devices as in the first embodiment are provided. The first optical observation device 40A is arranged on the back side of the second main wafer transfer device A2 as in the first embodiment, and the second optical observation device 40A is provided.
B is connected to the etching apparatus 50 via the wafer transfer device 64. The wafer transfer device 64 is configured to transfer a wafer between the etching device 50 and the second optical observation device 40B.

An electron microscope device 70 such as an SEM is provided on the back side of the first optical observation device 40A.
A wafer transfer device 63 that transfers a wafer between the electron microscope device 70 and the first optical observation device 40A is arranged between them. The electron microscope device 70 does not have to be connected in-line by the transport device 63 as described above and may be a stand-alone device.

With reference to the flow shown in FIG. 11, in this embodiment, for example, a resist pattern is formed on a wafer as in the first embodiment. The wafer on which the resist pattern is formed is carried into the optical observation device 40A. Here, referring to FIGS. 12 and 13, first, the grating pattern P formed outside the plurality of chips 65 on the wafer W, that is, outside the product region is recognized, and the line width of the grating pattern P is measured ( Step 11). The line width of the grating pattern P measured by the optical observation device 40A is x. In this case, the grating pitch of the grating pattern P is set to a size that can be optically recognized.
Can be transferred onto the wafer W along with the actual resist pattern Q which is a chip pattern in the exposure process on a mask (reticle) in the exposure process.

Next, the wafer W is transferred to the electron microscope device 70, where the grating pattern P and the resist pattern Q are recognized, and the line width of each is measured (step 12). The line width of the grating pattern P measured by the electron microscope device 70 is a, and the line width of the resist pattern Q is b. Since the electron microscope apparatus 70 uses an electron beam, the resist contracts, and the measured line widths are slightly smaller than the actual line widths.

The data of the line widths x, a, b obtained as described above is sent to the control unit 60 (see FIG. 10). 14
Shows line widths x, a, and b measured by the optical observation device 40A and the electron microscope device 70, respectively. Here, the line width to be finally obtained is the line width y of the actual resist pattern Q.
Is. However, since this y has a complicated shape and cannot be observed by the optical observation device 40A, this y is controlled by the control unit 6.
At 0, it is calculated as follows.

First, the inspection result a by the electron microscope,
Based on b, the correlation b = f ₁ (a) between a and b is obtained (step 13-1). Next, based on the line widths x and a of the grating pattern P, the correlation x = f ₂ (a) between these x and a is obtained (step 13-2). Then, a correlation y = f ₃ (x) between x and y can be obtained based on these correlations f ₁ and f ₂ . As a result, the line width y of the actual resist pattern Q to be finally obtained is obtained (step 13-3).

The process of obtaining such correlations f ₁ and f ₂ is performed for a plurality of chips on which a plurality of different patterns are formed, or for a plurality of inspection wafers, and a plurality of data are obtained. It is preferable to collect and obtain. Accordingly, the line width of the resist pattern Q can be measured with higher accuracy. Regarding the order of obtaining the correlations f ₁ and f ₂ , f ₁ may be obtained after obtaining f ₂ .

When a product wafer is actually manufactured, only the optical observation apparatus 40A is used based on the above database to recognize, for example, only the grating pattern, thereby nondestructively determining the actual resist pattern. The line width can be measured accurately.

Then, for example, based on the line width of the resist pattern obtained as described above, optimum etching processing conditions are set as in the first embodiment (step 14).
Etching is performed under these processing conditions (step 1)
5).

Next, the case of inspecting the line width of the circuit pattern formed after the etching process will be described. The wafer W that has been subjected to the etching process in step 15 is carried into the second optical observation device 40B. In the second optical observation device 40B, the based on the correlation between f ₃ obtained by the measurement of the first optical observation device 40A, the resist on the actual circuit pattern just recognize grating pattern (Step 16) It is possible to predict the line width of (step 17). In this way, by using the same optical observation devices 40A and 40B, the database can be shared, so that the line width after etching can be measured efficiently and nondestructively.

The present invention is not limited to the embodiments described above, and various modifications are possible.

For example, in the above embodiment, the etching time, the gas composition ratio, and the power are controlled as the etching processing conditions, but the present invention is not limited to these, and influences on the variation of the line width such as the degree of vacuum in the chamber. It is also possible to control all the parameters that are considered to affect.

Further, in the above embodiment, the etching device 50 and the coating and developing treatment device 1 are integrally provided to be in-line, but the etching device is made to be a stand-alone device.
The wafer may be carried by a worker. In this case, the etching device 50 and the coating and developing treatment device 1 are set to L
Connection is made with communication wiring such as AN, and step 13 is performed based on step 12 shown in FIG. Step 12 may be performed by the controller on the side of the etching apparatus, or may be performed by the side of the coating and developing treatment apparatus as in the above embodiment. Further, a control device including a calculation unit, a storage unit, an analysis unit, etc. may be provided separately. Further, the etching device is arranged on the back side of the cassette station 10 shown in FIG.
The wafer may be loaded into and unloaded from the etching apparatus by the wafer carrier 22.

Further, in the above embodiment, only the line width of the pattern has been described, but the present invention is not limited to this, and the pitch between patterns, the height, the angle of sidewalls, etc. can also be measured using an optical observation device. It is possible.

Further, in the above embodiment, the case where the semiconductor wafer is used has been described, but the present invention is not limited to this and the present invention can be applied to a glass substrate used for a liquid crystal display or the like.

[0072]

As described above, according to the present invention,
The line width and the like of the resist pattern actually formed in the photolithography process can be accurately measured, and a desired circuit pattern can be finally formed in the etching process. This contributes to improvement in yield.

[Brief description of drawings]

FIG. 1 is a plan view of a coating and developing treatment apparatus according to an embodiment of the present invention.

FIG. 2 is a front view of the coating and developing treatment apparatus shown in FIG.

FIG. 3 is a rear view of the coating and developing treatment apparatus shown in FIG.

FIG. 4 is a perspective view showing a main wafer transfer device according to one embodiment.

FIG. 5 is a sectional view of an etching apparatus according to an embodiment.

FIG. 6 is a configuration diagram of an optical observation apparatus according to an embodiment.

FIG. 7 is a flowchart showing a series of processing steps in a coating and developing processing apparatus.

FIG. 8 is a diagram showing a relationship between etching time and line width.

FIG. 9 is a diagram showing a relationship between etching power and line width.

FIG. 10 is a plan view of a coating and developing treatment apparatus, an etching apparatus and the like according to a second embodiment of the present invention.

FIG. 11 is a flowchart showing a series of processing steps according to the second embodiment.

FIG. 12 is a plan view showing a wafer having a resist pattern formed on a chip.

13 is an enlarged plan view of the chip shown in FIG.

FIG. 14 is a diagram showing line widths measured by an optical observation device and an electron microscope device, respectively.

[Explanation of symbols]

W ... Semiconductor wafer P ... Grating pattern Q ... Resist pattern line width ... x, y, a, b f ₁ , f ₂ , f ₃ ... Correlation 1 ... Coating and developing treatment apparatus 40 ... Optical observation apparatus 40A ... First Optical observation device 40B ... Second optical observation device 50 ... Etching device 60 ... Control unit 70 ... Electron microscope device

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Shuji Iwanaga             TBS release, 5-3-6 Akasaka, Minato-ku, Tokyo             Sending Center Tokyo Electron Limited (72) Inventor Michio Tanaka             TBS release, 5-3-6 Akasaka, Minato-ku, Tokyo             Sending Center Tokyo Electron Limited F term (reference) 5F004 BB01 CA03 CA08 CB02 CB05                       CB09

Claims (16)

[Claims] 1. A substrate processing method for forming a desired circuit pattern by performing an etching process after forming a resist pattern on a substrate, comprising: (a) recognizing the resist pattern; and (b) recognizing the resist pattern. Controlling the processing conditions of the etching based on the result. 2. The substrate processing method according to claim 1, wherein the etching processing conditions include at least one of an etching time, an etching gas composition ratio, and an etching power. 3. The substrate processing method according to claim 1, wherein the step (a) uses an optical observation device. 4. The substrate processing method according to claim 3, wherein in the step (a), (c) the grating pattern formed in a region other than the product region on the substrate is recognized by the optical observation device. And (d) a step of recognizing the grating pattern and the resist pattern formed in the product region with an electron microscope to obtain a correlation between the grating pattern and the resist pattern, and (e) the step (c) And a step of obtaining a correlation between the grating patterns recognized in the step (d), and (f) a step of recognizing the resist pattern based on the respective correlations obtained in the steps (d) and (e). A substrate processing method characterized by the above. 5. A substrate processing method for forming a desired circuit pattern by forming a resist pattern on a substrate and then performing an etching process, comprising: (a) recognizing the resist pattern by a first optical observation device. And (b) controlling the etching processing conditions based on the recognition result, and (c) recognizing the circuit pattern on the substrate that has been etched under the control with the second optical observation device. A substrate processing method comprising the steps of: 6. The substrate processing method according to claim 5, wherein the etching processing conditions include at least one of etching time, etching gas composition ratio, and etching power. 7. The substrate processing method according to claim 5, wherein in the step (a), (c) the grating pattern formed in a region other than a product region on the substrate is formed into the first pattern. A step of recognizing with an optical observation device, and (d) a step of recognizing the grating pattern and the resist pattern formed in the product region with an electron microscope and obtaining a correlation between the grating pattern and the resist pattern. e) the step of obtaining the correlation between the grating patterns recognized in the step (c) and the step (d), and (f) the resist pattern based on the correlations obtained in the steps (d) and (e). And a step of recognizing the substrate. 8. The substrate processing method according to claim 5 or 6, wherein data of the substrates recognized by the first optical observation device is accumulated to create a database, and the database is used as the second database. The method for processing a substrate, further comprising the step of utilizing the data of the substrate recognized by the optical observation apparatus of 1. 9. The substrate processing method according to claim 8, wherein in the step (c), the circuit pattern after the etching processing is performed based on a database of grating patterns recognized by the first optical observation apparatus. A substrate processing method comprising a step of recognizing. 10. A substrate processing apparatus for forming a resist pattern on a substrate and transferring the substrate to an etching apparatus to form a desired circuit pattern, a recognition means for recognizing the resist pattern, and the etching based on the recognition result. And a means for controlling the processing conditions of 1. 11. The substrate processing apparatus according to claim 10, wherein the etching processing conditions include at least one of an etching time, an etching gas composition ratio, and an etching power. 12. The substrate processing apparatus according to claim 10, wherein the recognition unit includes an optical observation device. 13. The substrate processing apparatus according to claim 12, wherein the recognizing unit recognizes (a) the grating pattern formed in a region other than the product region on the substrate by the optical observation device. A means for recognizing the grating pattern and the resist pattern formed in the product area with an electron microscope, and obtaining a correlation between the grating pattern and the resist pattern, and (b) using the optical observation device and the electron microscope, respectively. It is characterized by comprising means for obtaining the correlation between the recognized grating patterns, and (c) means for recognizing the resist pattern based on the respective correlations obtained by the means (a) and the means (b). Substrate processing equipment. 14. A substrate processing apparatus for forming a resist pattern on a substrate and transferring the substrate to an etching apparatus to form a desired circuit pattern, comprising: a first optical observation apparatus for recognizing the resist pattern; A substrate processing apparatus comprising: a means for controlling the etching processing conditions based on a result; and a second optical observation apparatus for recognizing a circuit pattern on the substrate that has been etched under the control. . 15. The substrate processing apparatus according to claim 13, wherein the etching processing conditions include at least one of an etching time, an etching gas composition ratio, and an etching power. 16. The substrate processing apparatus according to claim 14 or 15, wherein data of substrates recognized by the first optical observation apparatus is accumulated to create a database, and the database is used as the second database. The substrate processing apparatus further comprising means used when analyzing the data of the substrate recognized by the optical observation apparatus.