JP2003208608A - Image processing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image processing device capable of performing a variable power processing and a half tone processing in parallel at a high speed without interrupting the reading processing of image data and suppressing the memory cost to achieve a high speed processing. <P>SOLUTION: This image processing device has a memory arbiter I/F performing arbitration of demand for a memory arbiter performing image reading processing, reading processing of dither data, and writing processing after processing, a data conversion processing means for performing image processing for image data on a horizontal line from the memory arbiter I/F, a half tone processing means for performing half tone processing for dither data by the number of lines after changing power of each line in the vertical direction from the memory arbiter I/F and data per horizontal line after image processing from the data conversion processing means, and a data conversion means. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing device, and more particularly to a halftone processing device and a halftone processing method for converting multi-valued image data into a binary image,
In particular, it relates to a method of increasing the speed on the controller side of a printer or the like.

[0002]

2. Description of the Related Art Conventionally, in page printers and the like, it has been difficult to meet the demand only by the performance of the CPU due to the demand for increasing the resolution and increasing the speed. In particular, a color printer requires various kinds of image processing, and various processing such as C, M, Y, and K plate image scaling processing, dither processing, and color conversion processing.

In recent years, with the development of semiconductor technology, it has become possible to carry out part of the processing performed by the CPU by hardware. And this hardware xcelerator
Japanese Patent Laid-Open No. 2000-90237 proposes a system in which the function can be changed by implementing the GA. The image scaling technique is a technique required to obtain an output image of the same size as the input image when the resolutions of the images handled by the input device and the output device are different. As a method of this scaling processing, a side method, a bilinear interpolation method, a cubic interpolation method, etc. are known. The nearest neighbor method is an algorithm for interpolating to a pixel closest to a point to be interpolated, and the bilinear interpolation method is a method to obtain interpolated data from four points around the point to be interpolated by linear interpolation. The points J, I, G, and H are expressed by the following equations.

F (Z) = f (J) (1-α) (1-β) + f (I) (α) (1-β) + f
(G) (1-α) (β) + f (H) (α) (β) The cubic interpolation method is expressed by the following arithmetic expression from 16 points around the point Z. Here, C (t) is an approximate expression of the function SinπX / πX that constitutes the sampling theorem.

F (Z) = f (G) C (Xg-Xz) C (Yg-Yz) + f (H) C (X
h-Xz) C (Yh-Yz) + ... + f (V) C (Xv-Xz) C (Yv-Yz) C (t) = 1-2t ² + | t | ³ (0 ≦ | t | < 1) C (t) = 4-8 | t | +5 | t | 2- | t | 3 (1 ≦ | t | <2) C (0) = 0 (2 ≦ | t |)

When these processing methods are compared, the nearest neighbor method is light in processing, but the image quality is not so good. The processing in the bilinear interpolation method is normal, and the image quality is normal. Three
It is known that the processing in the secondary interpolation method is heavy, but the image quality is good.

As a conventional example for generating halftone data at high speed, there is Japanese Patent Laid-Open No. 6-6606 (hereinafter referred to as Conventional Example 1). In this conventional example 1, one line of the threshold matrix is alternately transferred to a plurality of high-speed memories separately from the memory of the threshold matrix data, and the halftone process is executed by reading the threshold data from the high-speed memory.

[0008]

However, the above-mentioned conventional example 1 aims at performing halftone generation at high speed with a small amount of high-speed memory, and basically expects a dramatic increase in processing speed. I can't.

In Japanese Unexamined Patent Publication No. 2000-92321 (hereinafter referred to as Conventional Example 2) and Japanese Unexamined Patent Publication No. 2000-165672 (hereinafter referred to as Conventional Example 3), the threshold value data read from the threshold value matrix memory until one scanning line is completed. , All the threshold value data to be applied to the process so as to be reusable are fetched into a register, which is selectively output to a plurality of comparison means to execute parallel comparison processes. The threshold data set in the register is sequentially shifted and repeatedly used. However, in this system, in a system having one main memory (a system that does not have a separate memory for storing dither), a dither pattern for each scanning line is used in a system that processes the scaling process and the halftone process in parallel. It is conceivable to stop the image data reading process necessary for the scaling process or the halftone process to read the image data, and ultimately the system cannot speed up the process.

Further, in Japanese Unexamined Patent Publication No. 2001-150739 (hereinafter referred to as Conventional Example 4), a scaling processing apparatus and a halftone processing apparatus using the nearest neighbor method are provided, and the halftone processing apparatus uses a dither memory. Is disclosed. For example, when a 16 * 16 matrix dither pattern is adopted, the data amount of dither data is 16 lines. It is uneconomical to provide a memory in which all such a large amount of threshold values are stored. In this case, it is advisable to store the dither data in the RAM and to provide a direct memory access circuit as shown by the broken line in FIG. In addition, 4 for data of 1 pixel
It is also possible to supply four threshold values in order and control four binary data. The data transfer clock after the binarization process may be quadrupled to the data transfer clock before the binarization process.

Further, as described above, the nearest neighbor method, the bilinear interpolation method, the cubic interpolation method and the like are known as the scaling processing methods. Conventionally, the source image is processed in the work area of the CPU and the scaling processing is performed. What was done was developed, then halftone processed, and the band buffer was written. However, in this method, the work area of the CPU must be used largely, and moreover, the work area of the same size as the band memory which is the size of the image MAX must be provided.

The present invention is intended to solve these problems, in which the dither data necessary for reading the number of lines after vertical scaling is read in batch, and the data after image processing is read in a line memory. The number of lines after scaling in the vertical direction is stored in, and then the data is collectively written in the memory, so that scaling processing and halftone processing are performed in parallel at high speed without interrupting the reading processing of image data. Accordingly, it is an object of the present invention to provide an image processing apparatus that can reduce the memory cost and realize high speed. Further, since pixels for the number of parallel processing pixels of the halftone processing device are always supplied, an image processing device capable of speeding up the processing by performing parallel processing for the same parallel processing pixels in the scaling processing. The purpose is to provide.

[0013]

In order to solve the above-mentioned problems, the image processing apparatus of the present invention arbitrates a request to a memory arbiter which performs an image reading process, a dither data reading process and a post-processing writing process. The memory arbiter I / F to be performed, data conversion processing means for performing image processing from the memory arbiter I / F to image data of horizontal lines, and the number of lines after scaling of each vertical line from the memory arbiter I / F. The dither data and the halftone processing means for performing halftone processing on the data for each horizontal line after the image processing from the data conversion processing means, and the data conversion means. Therefore, the image data reading process and the image processing can be performed in parallel without interrupting the image data reading process, and the speed can be increased.

Further, the memory arbiter I / F means performs a scaling process in the vertical direction, selects necessary dither data according to the scaling factor in the vertical direction, and reads it.
Can speed up.

Further, the data conversion means has a scaling processing means for performing scaling processing by the nearest neighbor method. Therefore, it is possible to perform high-speed processing without needing an unnecessary work memory area for performing the halftone processing directly after scaling the image.

Further, the data conversion means has a scaling processing means for performing scaling processing by the bilinear interpolation method. Therefore, it is possible to perform high-speed processing without needing an unnecessary work memory area for performing the halftone processing directly after scaling the image.

Further, the scaling processing means has a scaling pixel coefficient generation means capable of scaling processing the same number of pixels in parallel as the pixels to be processed in parallel by the halftone processing means, and the image data Performs halftone processing directly. Therefore, it is possible to perform high-speed processing without needing a useless work memory area, and it is possible for the scaling processing unit to constantly generate pixels for the number of parallel processings of the halftone processing unit. It can be processed at high speed.

Further, the scaled pixel coefficient generation means receives parallel X width generation means capable of obtaining the X width of the same number of pixels as the number of parallel processings of the halftone processing means, and the plurality of X widths, And an output X width generation means for dividing and outputting the number of parallel processings of the halftone processing means. Therefore, since the scaling processing is performed in parallel in the horizontal direction, the processing can be performed at high speed.

Further, the halftone processing means includes a parallel comparison means for comparing a plurality of pixels in a horizontal direction in parallel, and a plurality of horizontal threshold values received from the dither pattern memory in a horizontal direction from a pixel for current comparison. And a comparison pattern cutout unit that cuts out a plurality of threshold matrices. Therefore, since the halftone processing is performed in parallel in the horizontal direction, the processing can be performed at high speed.

Further, the comparison pattern cutting-out means is configured to make a plurality of horizontal threshold matrixes received from the dither pattern memory from the effective pixel number received from the scaling processing means, and a plurality of horizontal threshold matrixes from the current pixel to be compared. Cut out. Therefore, since the halftone processing is performed in parallel in the horizontal direction, the processing can be performed at high speed.

Further, the halftone processing means includes a parallel comparing means for comparing a plurality of pixels in the horizontal direction in parallel and a plurality of threshold matrixes in the horizontal direction received from the dither pattern memory from the pixel to be currently compared in the horizontal direction. A plurality of pixels in the horizontal direction received from the comparison pattern cutout unit and the parallel comparison unit that cuts out a plurality of threshold matrices,
It has a fixed length generation means for inserting into the fixed length data by the number of effective pixels received from the scaling processing means. Therefore, since the halftone processing is performed in parallel in the horizontal direction, the processing can be performed at high speed.

Further, the scaling processing means is arranged to MAX in the horizontal direction.
Pixels are obtained in parallel for the magnification of, and pixels are obtained in parallel for the magnification of MAX in the horizontal direction. Therefore, since the scaling processing is performed in parallel in the horizontal direction, the processing can be performed at high speed.

Further, the scaling processing means is arranged to MAX in the horizontal direction.
It has a horizontal interpolation means for calculating in parallel the pixels for the magnification and the effective number counting means for obtaining the effective number of the pixels.
Therefore, since the scaling processing is performed in parallel in the horizontal direction, the processing can be performed at high speed.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION An image processing apparatus according to the present invention comprises a memory arbiter I / F for arbitrating requests to a memory arbiter which performs an image reading process, a dither data reading process and a post-processing writing process, and a memory arbiter I. /
Data conversion processing means for performing image processing from F to horizontal line image data, dither data for the number of lines after scaling of each vertical line from the memory arbiter I / F, and after image processing from the data conversion processing means And half-tone processing means for performing half-tone processing on the data for each horizontal line and data conversion means.

[0025]

1 is a sectional view showing the structure of a multicolor image forming apparatus to which an image processing apparatus of the present invention is applied. According to the multicolor image forming apparatus shown in the figure, the belt-shaped photosensitive member 1 which is an image carrier is rotatably supported by rotating rollers 2 and 3,
The rotary rollers 2 and 3 are driven to rotate in the arrow A direction. A charging device 4, which is a charging unit, a charge eliminating lamp L, and a cleaning blade 15A for the photoconductor 1 are arranged on the outer peripheral portion of the photoconductor 1. At a position downstream of the charging device 4, there is an optical writing unit to which a laser beam emitted from a laser writing unit 5 which is an optical writing unit is irradiated. A multicolor developing device 6 in which a plurality of developing units (developing means) are switchably supported is arranged at a position downstream of the optical writing section. The multi-color developing device 6 includes a yellow developing unit, a magenta developing unit, and a cyan developing unit for each color of the toner contained therein. A black developing unit 7 containing black toner is provided above the multi-color developing device 6. Any one of these developing units moves to a developable position in synchronization with the developing timing of the corresponding color. The multicolor developing device 6 has a function of selecting one of the developing units by rotating 120 degrees on the circumference. Then, when these developing units operate, the black developing unit 7 moves to a position separated from the photoconductor 1. The movement is performed by the rotation of the cam 45. The laser writing unit 5 sequentially generates laser light according to image forming signals (writing information) of a plurality of colors from a laser light source (not shown), and the polygon mirror 5 is rotated by a polygon motor 5A.
The laser beam is periodically deflected by using B, and the charged photoconductor 1 is passed through the fθ lens 5C and the mirror 5D.
The surface of the is scanned to form an electrostatic latent image on the surface.

Then, the electrostatic latent image formed on the surface of the photoconductor 1 is developed with the toner from the corresponding developing unit, and a toner image is formed and held. The intermediate transfer belt 10 is adjacent to the photoconductor 1 and includes the rotating rollers 11 and
It is supported by 12 so as to be rotatable in the direction of arrow B. The toner image on the photoconductor 1 is transferred onto the surface of the intermediate transfer belt 10 by a transfer brush (first transfer means) 13 on the back side of the intermediate transfer belt 10. The surface of the photoconductor 1 is cleaned by the cleaning blade 15A for each color, and a toner image of a predetermined color is formed on the surface. Then, each time the intermediate transfer belt 10 rotates, the toner images on the photoconductor 1 are transferred to the same position on the surface thereof, and the toner images of a plurality of colors are superposed and held on the intermediate transfer belt 10. It Then, the toner image is transferred to a recording medium such as paper or plastic. At the time of transfer onto a sheet, the sheet stored in the sheet feeding device (sheet feeding cassette) 17 is unwound by the sheet feeding roller 18 and conveyed by the conveying roller 19, and the registration roller pair 2
After being temporarily stopped in the state of being abutted with 0, the toner image is transferred to the nip between the intermediate transfer belt 10 and the transfer roller (second transfer means) 14 at a timing so that the transfer position of the toner image becomes normal. Re-transported. Then, after the toner images of a plurality of colors on the intermediate transfer belt 10 are collectively transferred by the action of the transfer roller 14 to the sheet, the sheet is sent to the fixing device 50, where the toner images are fixed, and then the discharge roller pair 51. The upper stack 52 of the main body frame 9
Is discharged to.

The intermediate transfer belt 10 includes a rotating roller 11
Cleaning device 16 for the intermediate transfer belt 10
Is provided, and the cleaning blade 16A is configured to be freely contactable and separable via the cleaning blade contacting / separating arm 16C. In the process of receiving the toner image from the photoconductor 1, the cleaning blade 16A separates from the intermediate transfer belt 10 and comes into contact with the sheet after the toner image is transferred from the intermediate transfer belt 10 to the sheet. Scrape off the residual toner after being transferred. The cleaning blade 16A, as described above,
There are one for the photoreceptor 1 and one for the intermediate transfer belt 10. The waste toner scraped by these blades is stored in the collection container 15. The recovery container 15 is replaced appropriately. An auger 16B provided inside the cleaning device 16 for the intermediate transfer belt 10 conveys the waste toner scraped by the cleaning blade 16A and feeds it to the collecting container 15 by a conveying means (not shown).

Unitized process cartridge 3
The apparatus 1 is configured so that the photoconductor 1, the charging device 4, the intermediate transfer belt 10, the cleaning device 16, and a conveyance guide 30 that forms a sheet conveyance path are integrally incorporated and can be replaced at the end of their life. In addition to the replacement of the process cartridge 31, the multi-color developing device 6, the black developing unit 7, etc. are also replaced at the end of their life. However, in order to facilitate the replacement and jam paper processing, a part of the front frame 8 of the main body is replaced. Has a structure that can be opened and closed about the support shaft 9A.

On the left side of FIG. 1, the electrical equipment / control device 6
0 is stored. A fan 58 is provided above the fan 58 and exhausts air to prevent excessive temperature rise inside the machine. On the right side of the drawing, another relatively small paper feeding device 59 is provided. Although the intermediate transfer belt 10 is used as the intermediate transfer member in this embodiment, an intermediate transfer drum may be used.

FIG. 2 is a block diagram showing the configuration of the electrical equipment / control device shown in FIG. In the figure, the electrical equipment / control device is
It mainly has an image memory accelerator 101 for operating the image memory 109, is controlled by the CPU 107, receives image data from a host computer (not shown) via a network, transfers the image data to the memory 109, and transfers the image data to the engine controller. 113
Transfer to and print out. At this time, communication with each host, control of the image memory 108, information obtained by operating from the panel 16 and bus control with peripherals such as the printer engine controller are performed. The bus controller 101 arbitrates the bus with each peripheral controller connected to the bus 117. The memory arbiter 103 arbitrates between the memory 109 and various controllers. The local I / F 104 is the ROM 10
5 and other interfaces. The ROM 105 stores various programs and font information such as characters. The CPU I / F 106 is an interface of the CPU 107. The CPU 107 controls the entire printer device. The memory controller 108 controls the memory 109 and is connected to various controllers and the CPU 107 via the memory arbiter 108. The memory 109 stores image data, its code data, and CP.
The U107 program and the like are stored. The communication controller 110 is connected to the network, receives various data and commands from the network, and is connected to various controllers via the memory arbiter 103. The image processing apparatus 112 reads an image from the memory 109 according to a command from the CPU 107, and writes the image after the image processing to the memory 109 after the image processing.
The engine controller 113 is connected to the bus 117 and controls the printer engine 114.
The panel controller 115 controls the panel 116. The panel 116 is a display device that informs the printer device of an operation from the user. Bus 117
The image memory accelerator 101 and various peripheral controllers are connected. The DMA 111 performs direct memory access between the memory controller 108 and the engine controller 113 connected to the bus 117.

FIG. 3 is a block diagram showing the arrangement of an image processing apparatus according to an embodiment of the present invention. In the figure, the image processing device 112 includes a memory arbiter I / F 201, a data conversion processing device 202, and a halftone processing device 203.
And a parameter storage device 204.

The memory arbiter I / F 201
Arbitrates the request to the memory arbiter 103 for the image reading process of the image processing device 112, the reading process of the dither data, and the writing process of the processed image, and the image data to the data conversion processing device 202 and the halftone processing device 203. To transfer the dither data to or receive the image-processed data from the halftone processing device 203,
Transfer to the memory arbiter 103. It also manages the scaling process in the vertical direction, requests the image data and dither data necessary for the scaling process via the memory arbiter 103, and transfers the processed image to the memory arbiter 103.

Further, the data conversion processing device 202 receives the image data of the horizontal line from the memory arbiter I / F 201, and performs the scaling processing in the horizontal direction, the color conversion processing, the filter processing, and the image data when the image data is a code. After decoding the code and converting it to image data, execute the above scaling processing, color conversion processing, filter processing, etc.
The processing result is transferred to the halftone processing device 203. Here, the detailed configuration of the data conversion processing device 202 is shown in FIG.

Further, the halftone processing device 203 receives the dither data of the number of lines after scaling of each line in the vertical direction from the memory arbiter I / F 201, and the data after the image processing is received from the data conversion processing device 202. Receives each horizontal line and executes halftone processing.

The parameter storage device 204 is a CP
Memory arbiter I / F 201 set from U, etc.
Data conversion processing device 202, halftone processing device 20
Store the required parameters in 3.

Next, the operation of the data conversion processing device 202 shown in FIG. 3 when the scaling processing is the nearest neighbor method will be described with reference to FIG. 5, which shows an operation flow. First, the memory arbiter I / F 201 of FIG. 3 performs a process of obtaining a scaling factor in the vertical direction (step S101). The memory arbiter I / F 201 reads the image data of one line from the memory 109 of FIG. 2 via the memory arbiter 103 of FIG. 2 and sends it to the data conversion processing device 202 of FIG. 3 (step S102). The memory arbiter I / F 201 reads dither data for the number of lines after scaling in the vertical direction,
Send to the halftone processing device 203 of FIG. 3 (step S
103). The memory arbiter I / F 201 obtains the Y start point YS and the Y end point YE after scaling by the vertical scaling DDA (digital differential analysis) from the determined vertical scaling factor and the coordinate Y start point DYS of the destination image. S104). And memory arbiter I / F201
Sets the obtained YS value in the vertical line counter after scaling (step S105). After that, the data conversion processing device 202 performs one-line image processing (magnification, color conversion, filter processing, etc.) (step S10).
6). The halftone processing device 203 performs halftone processing on the image data after the image processing for one line (step S107). Then, the halftone processing device 20
3 writes the 1-line data after the halftone processing in the internal line memory (step S108). The memory arbiter I / F 101 counts up the vertical line counter after scaling (step S109). Further, the memory arbiter I / F 201 checks whether or not the Y end point YE after scaling in the vertical direction obtained by the vertical line counter is exceeded, and if not, the process proceeds to step S106 (step S110). ; YES),
Memory arbiter I / F 20 when equal or exceeding
The image-processed data is written from the built-in line memory written in step 1 into the memory 109 via the memory arbiter 103 (step S11).
0; NO, step S111). Then, the memory arbiter I / F 201 determines the calculated Y end point Y after scaling in the vertical direction.
It is checked whether or not E exceeds the coordinate Y end point DYE of the day-station image, and if it exceeds, the process proceeds to step S102 (step S112; YES),
If they are equal to or more than the above, the processing is terminated (step S).
112; NO).

FIG. 6 is a diagram showing a timing example in the case of reducing in the vertical direction. The example shown in (a) of the figure is an example in which the reduction ratio is 0.5 times, in which one line of the image data before the image processing is skipped (only the odd line) is read, and the dither pattern data is sequentially set to one line. This is an example in which each line is read, and data after image processing is sequentially written line by line. Further, in this example, the image data reading processing and the image processing are processed in parallel. The example shown in (b) of the figure is an example of 0.6666 times, in which the image data before the image processing is read by skipping one line every three lines, and the dither pattern data is sequentially read every line, Then, the data after the image processing is sequentially written line by line. Also in this example, the image data reading process and the image processing are performed in parallel.

FIG. 7 is a diagram showing a timing example in the case of equal magnification and enlargement in the vertical direction. The example shown in (a) of FIG.
In this example, the image data before image processing is sequentially read line by line, the dither pattern data is sequentially read line by line, and the image processed data is written line by line. Further, in this example, the image data reading processing and the image processing are processed in parallel. The example shown in (b) of the figure is an example of 1.5 times, in which image data before image processing is sequentially read line by line, dither pattern data is sometimes read every two lines, and data after image processing is performed. Is an example in which is written every two lines from time to time. Further, in this example, the image data reading process and the image processing are performed in parallel, and sometimes the image processing of two lines is performed. The example of (c) in the figure is a double example, in which the image data before the image processing is sequentially read line by line, the dither pattern data is sequentially read every two lines, and the data after the image process is sequentially read. This is an example of writing each line. Further, in this example, the image data read processing and the image processing are processed in parallel, and two-line image processing is performed.

Next, FIG. 8 shows the memory arbiter I / of FIG.
It is a block diagram which shows the detailed peripheral structure of F. The memory arbiter I / F 201 is connected to the memory arbiter 103, and the memory arbiter 103 is the CPU I / F 1 of FIG.
When the memory access from the CPU and the memory access such as the memory access from the local I / F 104 in FIG. , The memory access is performed, and the standby processing is performed on another medium. The memory arbiter I / F 201 is connected to the memory arbiter 103 as the image processing device 112 of FIG. 2, and requests the memory arbiter 103 access right to the memory 109 of FIG. A request for reading is issued to the memory arbiter 103, image data is read, and the data conversion processing device 20
Transfer to 2. When the data conversion processing device 202 has a decoding processing device for image code, the image data is subjected to the above processing as coded data. Further, the memory arbiter 103 is requested to read the dither data, the dither data is read and transferred to the halftone processing device 203, and the memory arbiter 103 is requested to write the image data after the image processing of the halftone processing device 203 is performed. The subsequent data is transferred to the memory arbiter 103.

FIG. 9 is a block diagram showing the configuration of the memory arbiter I / F of FIG. In the figure, the memory arbiter I / F 201 is a scaling factor generator 301, Y D
The DA processing device 302, the IY counter device 303, the memory address generation device 304, the MUX 305, and the controller 306 are included. Scale factor generator 30
1 is the coordinate Y start point SY of the source image of the image to be scaled
The scaling factor RATEY in the Y direction is obtained from S, the Y end point SYE, and the coordinates Y start point DYS, Y end point DYE of the destained image after scaling, and transferred to the Y DDA processing device 302. Further, the Y DDA processing device 302 receives the scaling factor in the Y direction and the coordinate Y start point DYS of the destination image from the scaling factor generating device 301, and looks like an enlarged pixel indicated by a circle in the vertical direction of FIG. 61. Then, the Y coordinate of the input image after scaling is calculated by DDA (digital differential analysis) to obtain the Y start point YS and the Y end point YE, and the difference (the number of lines after scaling) DY is calculated, and the IY count processing device 303
And is transferred to the memory address generation device 304. Further, the IY counting device 303 is the Y DDA processing device 30.
2, the Y start point YS and the Y end point YE after scaling are received, and the data conversion processing device 2 receives from the Y start point to the Y end point after scaling.
02, each time the processing of one line of the halftone processing device 203 is completed, the line is counted, controlled, and compared with the coordinate Y end point of the destination image.
Controls the end of image processing. Further, the memory address generation device 304 has an image data loading address which is an address of a memory for accessing the memory 109 of FIG. 2 via the memory arbiter 103, a dither data reading address, and an image data writing address after image processing. To calculate. At this time, the number of lines after scaling is received from the Y DDA processor 302, the number of lines of dither data to be read (the number of data) and the number of lines to write the processed image (the number of data) are calculated, and a memory address is generated. To go. Further, the MUX 305 switches the transfer of the data read from the memory arbiter 103 to the data conversion processing device 202 and the halftone processing device 203 depending on the type of data. Also, the controller 3
Reference numeral 06 controls the memory arbiter I / F 201 and the image processing device 112 in FIG.

FIG. 10 is a block diagram showing the configuration of the scaling factor generator of FIG. The scaling factor generating apparatus shown in the figure includes subtractors 401 and 402, a divider 403, and a register 404.
It is configured to include. According to the scaling factor generator having such a configuration, the coordinates Y start point SYS and Y end point SYE of the source image of the image to be scaled, and the coordinate Y start point DYS and Y end point DYE of the scaled date image.
The scaling factor RATEY in the Y direction is calculated from Y DD of FIG.
A is transferred to the processing device 302. As shown in FIG.
By the calculation of Y = (SYE-SYS) / (DYE-DYS),
The scaling factor (RATEY) in the Y direction is obtained, and the coordinate Y start point SYS and Y end point SYE of the source image and the coordinate Y start point DYS and Y end point DYE of the destination image are obtained.

FIG. 11 is a block diagram showing the configuration of the Y DDA processing device shown in FIG. The Y DDA processing device shown in the figure includes a MUX 501, a register 502 for storing the Y value currently being processed, a register 503 for storing the Y-direction scaling factor RATEY, an adder 504, and a register for storing the Y end point after scaling. 505, register 5 for storing Y start point after scaling
06, a subtracter 5 for subtracting the positive part of the Y start point from the positive part of the Y end point of the register 505 to obtain the number of lines DY after scaling
07 are included. According to the Y DDA processing device having such a configuration, the scaling factor generating device 3 of FIG.
The scaling factor in the Y direction from 01 and the coordinate Y start point DYS of the destination image are received, and the scaling factor of the input image after scaling of the input image is increased as indicated by the enlarged pixel indicated by ◯ in the vertical direction of FIG. Y coordinate by DDA (digital differential analysis)
The Y start point YS and the Y end point YE are obtained, the difference (the number of lines after scaling) DY is obtained, and the IY count processing device 30 of FIG.
3 and the memory address generator 304.

FIG. 12 is a block diagram showing the configuration of the IY counter device of FIG. The IY counting device shown in the figure is the Y DDA processing device 302 of FIG.
The end point and the coordinate Y end point DYE of the destination image are compared, and the result YENDFL is compared with the controller 306 of FIG.
MUX 602 which sends the output of the adder 604 which is sequentially added to the comparator 601 which is transferred to the first, the Y start point after the scaling from the Y DDA processing device 302 of FIG. Register 603 for storing the Y value of, the adder 604 that counts the line each time the data conversion processing device 202 of FIG. 3 and the halftone processing device 203 of FIG. 9 is compared with the Y end point after scaling from the Y DDA processing device 302 in FIG. 9, and a comparator 605 that transfers the result IYENDFL to the controller 306 in FIG. 9 is configured. According to the IY counter device having such a configuration, the Y start point YS and the Y end point YE after the scaling are received from the Y DDA processing device 302 in FIG. 9, and the Y start point to the Y end point after the scaling are performed in FIG. Each time the data conversion processing device 202 and the halftone processing device 203 in FIG. 3 finish processing one line, the line is counted, controlled, and compared with the coordinate Y end point of the destination image, and the image processing ends. Control.

FIG. 13 is a block diagram showing the configuration of the memory address generation device of FIG. In the memory address generation device shown in the figure, the image start address is set from the parameter storage device 204 of FIG. 3 as an initial value, and thereafter, as shown in FIG. 6, the address of the image data before the image processing is read line by line and the address is set. An image data address generation device 701 for generation, a dither start address is set as an initial value from the parameter storage device 204 of FIG. 3, and the number of lines after scaling is received from the Y DDA processing device 302 of FIG. 9 and read dither data. Number of lines (data volume)
And a day data address generator 70 for generating an address for reading the dither data, as shown in FIG.
2. As the initial value, the processed image start address is set from the parameter storage device 204 of FIG.
A post-processing image that receives the number of lines after scaling from the processing device 302, calculates the number of lines (data amount) of post-processing image data to be written, and generates an address for writing post-image processing data as shown in FIG. Data address generator 70
3 and MUX 704. According to the memory address generation device having such a configuration, the image data loading address, which is the address of the memory for accessing the memory 109 of FIG. 2 via the memory arbiter 103 of FIG. 2, and the dither data read address, The image data write address after image processing is calculated. At this time, the number of lines after scaling is received from the Y DDA processor 302 in FIG. 3, the number of lines of dither data to be read (the number of data) and the number of lines to write the processed image (the number of data) are calculated, and the memory address is calculated. Will be generated.

FIG. 14 is a block diagram showing the configuration of a scaling processing apparatus of the nearest neighbor method. The scaling processing device shown in the figure includes an original pixel storage device 801, a scaling factor generation device 802, a DDA processing device 803, an IX counting device 804, a scaling pixel coefficient generation device 805, a scaling pixel conversion device 806, and a controller 807. It is configured to include.

Further, the original pixel storage device 801 stores pixels to be processed in parallel by the halftone processing device and transfers them to the scaling pixel conversion device 806. The scaling factor generator 802
Coordinate X of the source image of the image to be scaled, start point SXS, X end point SSX, coordinate X of the day-change image after scaling
RATE from the start point DXS, X end point DXE in the X direction
X is obtained and transferred to the DDA processor 803. The DDA processing device 803 uses the scaling factor in the X direction from the scaling factor generator 802 and the coordinate X start point DXS of the destination image.
61, the coordinate of the input image after scaling is calculated by DDA (digital differential analysis) at any time, as in the enlarged pixel indicated by ◯ in FIG. In this example, the X start point XS and the X end point XE that are interpolated for interpolation as shown in FIG.
Is transferred to the IX count processing device 804 and the scaling pixel coefficient generation device 805. The IX counting device 804 receives the start point and end point in the Y direction from the DDA processing device 803, generates the Y coordinate of the interpolated pixel indicated by Δ in the drawing of FIG. Notify by the XENDFL signal. The scaling pixel coefficient generation device 805 receives the start point XS in the direction of interpolation from the DDA processing device 803 and the scaling factor RATEX from the scaling factor generation device 802, and outputs the width of each pixel output by the scaling pixel generation device. The scaling pixel conversion device 806 performs scaling processing on the pixels. At this time, the variable pixel conversion device 80
The MAX number output by 6 is up to the MAX pixel value that can be processed by the halftone processing device. Moreover, since the scaling factor is 1, the output of the scaling pixel generation device corresponds to the pixel value of MAX that can be processed by the halftone processing device. Therefore, when the scaling factor is 1 or more, it is necessary to output each MAX pixel value that can be processed by the halftone processing device over a plurality of clocks. Variable Pixel Converter 8
06 receives a pixel to be scaled from the scaled pixel generation device, receives the width of each pixel output from the scaled pixel generation device from the scaled pixel coefficient generation device 805, and as shown in FIG.
The scaling process is executed by changing the pixel to be scaled to the width from the scaled pixel generation device. Controller 807
Controls the entire variable power processor.

FIG. 16 is a flow chart showing the operation of the scaling processing device of FIG. In the figure, first, the scaling factor is obtained by the scaling factor generator 802 of FIG. 14 (step S201). The DDA in the X direction is initialized (step S202). By the DDA processing device 803 of FIG.
The DDA process in the direction (horizontal direction) is performed to obtain the X start point XS and the X end point XE to be processed (step S203). The scaled data is read from the internal line memory (step S2
04). The scaled pixel coefficient generation device 805 of FIG.
The width of the read pixel to be subjected to the scaling processing is obtained (step S205). By the variable-magnification pixel conversion device 806 in FIG.
The scaled pixel is converted into the obtained width, and output according to the number of MAX parallel processing pixels of the halftone processing device (step S206). If XE does not exceed the coordinate X end point DXE of the scaled date image, the process returns to step S203 (step S207; YE).
S). If it is equal to or exceeds DXE, the process ends (step S207; NO).

FIG. 17 is a block diagram showing the configuration of the original pixel storage device of FIG. In the figure, a register 901
908 stores the data sequentially, and stores the pixels for the MAX parallel processing pixels of the halftone processing device. The line memory 909 connects the stored image data by the registers 901 to 908 and stores them in parallel, so that the reading of the image data from the main memory and the image processing can be performed in parallel, and the contents of the registers 901 to 908 at the time of reading Enable to read in parallel. The line memory controller 910 generates an address of the line memory and controls the entire original pixel storage device.

FIG. 18 is a block diagram showing the configuration of the scaling factor generator of FIG. The scaling factor generator shown in FIG.
It is configured to include subtractors 1001 and 1002, a divider 1003, and a register 1004. According to the scaling factor generator having such a configuration, the coordinates X start point SXS and X end point SXE of the source image of the image to be scaled as described above.
And the coordinate X start point DX of the day-change image after scaling
The scaling ratio RATEX in the X direction is obtained from the S and X end points DXE and transferred to the DDA processing device 803 in FIG. That is, as shown in FIG. 17, RATEX = (SXE-SXS) / (D
XE-DXS) is used to calculate the scaling factor (RATE) in the X direction.
X) is obtained, and the coordinate X start point SXS and X end point SSX of the source image and the coordinate X start point DXS of the destination image are obtained.
And X end point DXE.

FIG. 19 is a block diagram showing the structure of the DDA processing apparatus shown in FIG. The DDA processing device shown in FIG.
Only for the first time, the MUX 110 that transfers the output X of the coordinate X start point DXS of the initial value destination image to the register 1102 and then sends the output of the adder 1104 that is sequentially added
1, a register 1102 for storing the currently processed X value,
MA in X-direction scaling ratio RATEX and halftone processor
Multiplier 1103 for multiplying the number of parallel pixels of X to obtain a fine difference for a plurality of pixels, a register 1104 for storing the value obtained by the multiplier 1103, an adder 1105, a register 1106 for storing an X end point to be interpolated, and an interpolation Register 1107 for storing the X start point. 14
The scaling factors in the X and Y directions and the coordinates X start point DXS and Y start point DYS of the destination image are received from the scaling factor generator 802 and are input as an enlarged pixel indicated by a circle in FIG. 61. The coordinate of the image after scaling is DDA
Calculated at any time by (digital differential analysis). In this example, the X start point and the X end point to be interpolated for interpolation as shown in FIG. 14 are obtained and transferred to the IX count processing device 804 and the scaled pixel coefficient generation device 805 of FIG. At this time, X
In the direction, DDA for MAX parallel processing pixels of the halftone processing device is performed. Therefore, DDA in the X direction
As shown in FIG. 19, the processing device has a structure in which the value obtained by multiplying the current X coordinate by the X-direction scaling factor RATEX obtained by the scaling factor generating device by the MAX parallel processing pixel number of the halftone processing device is sequentially added. .

FIG. 20 is a block diagram showing the structure of the IX counting device shown in FIG. The IX counter device shown in the figure has a comparator 1201, and the DDA processing device 8 of FIG.
XE value from 03 and coordinate X of day-station image
The end point DXE is compared to generate an XENDFL signal indicating that the X coordinate is equal to the X end point DXE.

FIG. 21 is a block diagram showing the configuration of the variable-magnification pixel coefficient generator of FIG. The scaled pixel coefficient generation device shown in the figure includes a parallel X width generation device 1301 and an output X width generation device 1302. The parallel X width generation device 1301 obtains the X coordinate of each pixel by DDA for the number of pixels output by the original image storage device 801 in FIG.
The X width between each pixel is obtained from the X coordinate and is sent to the X width generation device output by the output X width generation device 1302. Further, the output X width generation device 1302 performs processing for separately outputting according to the number of parallel processings of the halftone processing device output by the scaled pixel coefficient generation device 806 in FIG. 14, and outputs the X width of each pixel. The cumulative addition value and the number of pixels thereof are sent to the scaled pixel coefficient generation device 806 in FIG. The scaled pixel coefficient generation device having such a configuration uses the start point XS in the X direction from the DDA processing device 804 of FIG. The width generation device 1301 obtains the X coordinate of each pixel by DDA for the number of pixels output from the original image storage device, obtains the X width between each pixel from the X coordinate, and outputs the output X width generation device 130.
2, the variable pixel coefficient generation device 806 of FIG. 14 performs a process for outputting separately according to the number of parallel processes of the halftone processing device, and outputs the cumulative addition value of the X width of each pixel and that pixel. The scaled pixel coefficient generation device 806 of FIG.
Send to.

FIG. 22 is a diagram showing the configuration of the parallel X width generation device of FIG. The parallel X width generation device shown in the figure includes adders 1401 to 1408 and subtractors 1409 to 1416. The adders 1401 to 1408 receive the X start point obtained by the DDA processing device 803 in FIG. 14 and the X-direction scaling factor RATEX obtained by the scaling factor generation device 802 in FIG. 14, and obtain X values of a plurality of pixels. Subtractors 1409 to 1416 find the width between each pixel.

FIG. 23 is a block diagram showing the structure of the output X width generation device of FIG. The output X width generation device shown in the figure has MUXs 1501 to 1508 and registers 1509 to 1
516, cumulative addition processing device 1517, XWIDTH update processing device 1518, output XWIDTH generation processing device 1
519 and a cumulative addition processing device 1520. According to the output X width generation device having such a configuration, the X width of each pixel from the parallel X width generation device 1301 of FIG. 21 is received, stored in the register, and processed until all the received pixels are processed. Hold. And XWID
The X width of each pixel corresponding to the pixel output by the TH update processing device 1518 is subtracted from the register with a small pixel number, and M
Registers 1509 to 15 through UX 1501 to 1508
Update 16. The cumulative addition processing device 1517 cumulatively adds the X widths stored in the registers 1509 to 1516, and the XWIDTH update processing device 1518 receives the cumulative addition value output from the cumulative addition device 1517 and performs cumulative addition at each pixel point. The first cumulative addition point that exceeds the MAX parallel processing number of the halftone processing device is obtained from the value, an updated value up to that pixel is generated, and through MUX 1501 to 1508,
The values of the corresponding registers 1509 to 1516 are updated.
The output XWIDTH generation processing device 1519 receives the cumulative addition value output from the cumulative addition device 1517, and obtains the first cumulative addition point exceeding the MAX parallel processing number of the halftone processing device from the cumulative addition value at each pixel point, The output X width up to that pixel is obtained and transferred to the cumulative addition processing device 1520. The cumulative addition processing device 1520 performs cumulative addition necessary for the processing of the variable-magnification pixel conversion device 806 in FIG.

FIG. 24 is a block diagram showing the structure of the cumulative addition processing device of FIG. The cumulative addition processing device shown in the figure has adders 1601 to 1601 that obtain cumulative added values up to each pixel.
It has 1607.

FIG. 25 is a flow chart showing the processing of the XWIDTH update processing device of FIG. In the figure,
First, it is checked whether the X width of the 0th pixel is equal to or larger than the number of parallel processings of the halftone processing device (in this example, "8"), and if there is, the parallel processing number of the halftone processing device is calculated from the 0th X width. Subtraction is performed to obtain a new 0th X width value (step S301; YES, step S302). Then 0-
It is checked whether or not the cumulative X width up to the first is equal to or more than the number of parallel processings of the halftone processing device (in this example, it is “8”), and if there is, the 0th X width is set to “0” and the first X width is set. Then, the value obtained by subtracting the 0th X width from the parallel processing number of the halftone processing device is subtracted to obtain a new first X width value (step S303; YES, step S304). Thereafter, similar processing is performed in steps S305 to S317.

FIG. 26 is a flow chart showing the processing of the output XWIDTH generation processing device of FIG. First,
The X width of each pixel to be output is initialized (step S40).
1). Then, it is checked whether or not the X width of the 0th pixel is equal to or more than the number of parallel processings of the halftone processing device (in this example, "8"), and if there is more, it is parallel to the 0th output X width of the halftone processing device. Number of pixels to be processed by setting the number of processing PN
The parallel processing number of the halftone processing device is set in UM (step S402; YES, step S403). Further, it is checked whether or not the cumulative X widths from 0 to 1 are equal to or more than the number of parallel processings of the halftone processing device (in this example, "8"), and if there is, the 0th X width to the 0th output X width. Width X
Set WIDTH0, set the value of the first output X width to the value obtained by subtracting the 0th X width from the number of parallel processings of the halftone processing device, and set the number of pixels to process PNUM to the number of parallel processings of the halftone processing device. Is set (step S40
4; YES, step S405). Then, it is checked whether or not the cumulative X widths from 0 to 2 are equal to or more than the number of parallel processings of the halftone processing device (in this example, "8"), and if there is, the 0th X width to the 0th output X width. Width XWIDTH0
Is set to the first output X width and the first X width XW
IDTH1 is set, a value obtained by subtracting the cumulative addition value up to the first X width from the parallel processing number of the halftone processing device is set to the second output X width, and the number of pixels P to be processed is set.
The number of parallel processings of the halftone processing device is set to NUM (step S406; YES, step S407).
Thereafter, the same processing is performed in steps S408 to S417, and in step S418, the sum of the X widths of all pixels is less than or equal to the number of parallel processings of the halftone processing device.
The X widths of the pixels output by all the pixels have been updated.
The number of pixels PNUM for setting the X width value of the registers 1509 to 1516 of 3 and processing the sum of the X widths of all pixels
Set to.

FIG. 27 is a block diagram showing the structure of the cumulative addition processing device shown in FIG. The cumulative addition processing device shown in FIG.
707.

FIG. 28 is a flow chart showing the 0th processing of the output pixel of the variable pixel conversion apparatus of FIG. In the figure, first, the X width “DXWIDTH0” of the 0th pixel from the variable pixel coefficient generation device 805 of FIG. 14 is “0”.
If it is larger, the 0th output pixel is set to the value of DATA0 of the original pixel storage device 801 of FIG. 14 (step S
501; YES, step S502). And in FIG.
When the accumulated “DXWIDTH1” of the X-width of the 0th to 1st pixels from the variable pixel coefficient generation device 805 is larger than “0”, the 0th output pixel is the original pixel storage device 8
The value of DATA1 of 01 is set (step S50).
3; YES, step S504). Next, if the accumulated "DXWIDTH2" of the X width of the 0th to 2nd pixels from the scaled pixel coefficient generation device 805 of FIG. 14 is larger than "0", the output pixel 0th is the original pixel storage of FIG. Device 801
Value of DATA2 is set (step S505; Y
ES, step S506). Further, when the accumulated “DXWIDTH3” of the X widths of the 0th to 3rd pixels from the scaled pixel coefficient generation device 805 in FIG. 14 is larger than “0”,
The 0th output pixel is the DA of the original pixel storage device 801 in FIG.
The value of TA3 is set (step S507; YES,
Step S508). Further, when the accumulated “DXWIDTH4” of the X widths of the 0th to 4th pixels from the scaling pixel coefficient generation device 805 of FIG. 14 is larger than “0”, the 0th output pixel is the original pixel storage device of FIG. 801 DATA4
Is set (step S509; YES, step S510). Then, the accumulated "D" of the X width of the 0th to 5th pixels from the variable pixel coefficient generation device 805 of FIG.
If XWIDTH5 "is larger than" 0 ", output pixel 0
For the second, the value of DATA5 of the original pixel storage device 801 of FIG. 14 is set (step S511; YES, step S511).
512). Further, the scaled pixel coefficient generation device 805 in FIG.
The accumulated X-width of the 0th to 6th pixels from "DXWI"
When DTH6 "is larger than" 0 ", the 0th output pixel sets the value of DATA6 of the original pixel storage device 801 of FIG. 14 (step S513; YES, step S51).
4). Further, the accumulated "DXWIDT" of the X width of the 0th to 7th pixels from the scaling pixel coefficient generation device 805 in FIG.
When H7 "is larger than" 0 ", the 0th output pixel is shown in FIG.
The value of DATA7 of the original pixel storage device 801 of No. 4 is set (step S515; YES, step S516).

FIG. 29 is a flow chart showing the first processing of the output pixels of the variable pixel conversion apparatus of FIG. In the figure, first, the X width “DXWIDTH0” of the 0th pixel from the variable pixel coefficient generation device 805 of FIG. 14 is “1”.
If it is larger, the value of DATA0 of the original pixel storage device 801 of FIG. 14 is set as the first output pixel (step S).
601; YES, step S602). And in FIG.
When the accumulated “DXWIDTH1” of the X width of the 0th to 1st pixels from the variable pixel coefficient generation device 805 is larger than “1”, the first output pixel corresponds to DATA1 of the original pixel storage device 801 in FIG. Set the value (step S60
3; YES, step S604). When the accumulated “DXWIDTH2” of the X width of the 0th to 2nd pixels from the scaled pixel coefficient generation device 805 of FIG. 14 is larger than “1”, the first output pixel is the original pixel storage device of FIG. 801
The value of DATA2 of is set (step S605; Y).
ES, step S606). Further, when the accumulated “DXWIDTH3” of the X widths of the 0th to 3rd pixels from the scaled pixel coefficient generation device 805 in FIG. 14 is larger than “1”,
The first output pixel is the DA of the original pixel storage device 801 in FIG.
The value of TA3 is set (step S607; YES,
Step S608). When the accumulated X-width “DXWIDTH4” of the 0th to 4th pixels from the scaling pixel coefficient generation device 805 of FIG. 14 is larger than “1”, the first output pixel is the original pixel storage device of FIG. 801 DATA4
Is set (step S609; YES, step S610). Further, the scaled pixel coefficient generation device 8 of FIG.
The accumulated "DX" of the X width of the 0th to 5th pixels from 05.
When WIDTH5 "is larger than" 1 ", the value of DATA5 of the original pixel storage device 801 in FIG. 14 is set as the first output pixel (step S611; YES, step S6).
12). Then, the scaled pixel coefficient generation device 805 in FIG.
The accumulated X-width of the 0th to 6th pixels from "DXWI"
When DTH6 "is larger than" 1 ", the first output pixel sets the value of DATA6 of the original pixel storage device 801 of FIG. 14 (step S613; YES, step S61).
4). “DXWIDTH7”, which is the cumulative X width of the 0th to 7th pixels from the variable pixel coefficient generator 805 in FIG.
When is larger than “1”, the value of DATA7 of the original pixel storage device 801 of FIG. 14 is set for the first output pixel (step S615; YES, step S616).

30 to 35 show the second to seventh processing flows of the output pixels of the variable-magnification pixel conversion apparatus of FIG. 14, the 0th and 1st processings shown in FIGS. Since it is similar to the above, the description is omitted here.

As described above, in the variable-magnification pixel conversion device, the pixels for the parallel processing pixels of the halftone processing device must be obtained, and in this example, it is "8".

Next, the halftone processing device will be described in detail with reference to FIG. The halftone processing device shown in FIG.
1, dither pattern storage device 1802, MUX 180
3, dither pattern address generation device 1804, comparison pattern cutout device 1805, parallel comparison device 1806,
Fixed-length data generation device 1807, line memory 180
8, a line memory address generator 1809, and a controller 1810. In addition, the write address generation device 1801 uses the memory arbiter I of FIG.
An address for storing the dither data received from the / F201 in the dither pattern storage device 1802 is generated. The dither pattern storage device 1802 stores the dither data received from the memory arbiter I / F 201 of FIG. Note that FIG. 41, which will be described later, shows an example of the 32 * 8 size of the dither pattern memory of the dither pattern storage device. As described above, the memory arbiter I / F of FIG.
A dither pattern 201 is transferred for each number of lines that are scaled in the vertical direction and stored in the dither pattern storage device 1802. As in the format of FIG. 41, it is possible to store a dither pattern having only a vertical scaling factor.
Since the example shown in FIG. 41 is an example up to 8 times in the vertical direction, it is possible to store dither patterns for 8 lines in this way. The number of dither patterns in the horizontal direction is MAX 32 dots in this example. MU
X1803 is a dither pattern storage device 1 when transferring dither data from the memory arbiter I / F 201 of FIG.
The address of 802 is passed to the write address generation device 1801. The dither pattern address generation device 1804 receives the size of the dither pattern from the parameter storage device 204 of FIG. 3 and generates a dither pattern memory address. The comparison pattern cutout device 1805 is a data conversion processing device 20 of FIG.
2, the threshold matrix of a plurality of pixels is read in the horizontal direction, the number of pixels currently processed is received from the controller 1810, and the effective pattern is read from the head of the dither pattern memory in the horizontal direction of the data conversion processing device 202 in FIG. A plurality of data are transferred to the parallel comparison device 1806. The parallel comparison device 1806 is the data conversion processing device 20 of FIG.
The plurality of pixel values after scaling in the horizontal direction obtained in 2 are compared in parallel with the threshold value matrix from the comparison pattern cutout device 1805. The fixed length data generation device 1807
Fixed-length data is generated by adding the 1/0 value obtained by the parallel comparison device 1806 to the fixed-length data by the effective number indicated by the controller 1810. The line memory 1808 stores the fixed-length data generated by the fixed-length data generation device 1807 as data for the number of lines after scaling in the vertical direction. In the example of the line memory format shown in FIG. 43, which will be described later, data of 8 lines is stored because it is an example of a processing device up to 8 times in the vertical direction. The line memory address generator 1809 uses the data from the fixed-length data generator 1807 as the line memory 18
The address for storing in 08 is generated. The controller 1810 receives the effective number of horizontally interpolated pixels from the scaling processing device 202 of FIG. 3, and controls the halftone processing device of FIG. 36 according to the flow shown in FIG. 40 described later.

Next, FIG. 37 is a block diagram showing the structure of the comparative pattern cutting device of FIG. The comparison pattern cutout device shown in FIG.
2, 1904, 1906, shifter 1903, adder 1
Has 905. In addition, the register 1901 is shown in FIG.
The value from the dither pattern storage device 1802 of No. 6 is stored. In this example, eight data are processed in the horizontal direction of the data conversion processing device 202 of FIG. The register 1902 stores the value from the register 1901. These registers 1901 and 1902 generate a double pattern in the horizontal direction of the data conversion processing device, and the shifter 1
Transfer to 903. The shifter 1903 is provided in the register 19
01, 1902 to the data conversion processing device 202 of FIG.
From the current start value obtained from the effective number of horizontally interpolated pixels from the variable-magnification pixel conversion device 806 of FIG. Is output after shifting. The register 1904 stores the value of the shifter 1903. The adder 1905 receives the effective number from the data conversion processing device 202 of FIG. 3 and performs addition processing with the current shift value to obtain the next head value. The register 1906 is an adder 1
The value obtained in 905 is stored.

FIG. 38 is a block diagram showing the structure of the parallel comparator of FIG. In the example shown in the figure, since the number of processes in the horizontal direction of the data conversion processing device 202 of FIG. 3 is “8”, there are eight comparison devices. Comparators 2001-20
In 08, a plurality of thresholds are compared with each pixel in the horizontal direction of the data conversion processing device 202 of FIG. 3 which is cut out by the comparison pattern cutting device 1805 of FIG.

FIG. 39 is a block diagram showing the structure of the fixed length data generation device of FIG. The fixed-length data generation device shown in the figure includes a shifter 2101, an OR device 2102, registers 2103, 2104, 2106, and an adder 2105.
have. The shifter 2101 receives a plurality of “1/0” data in the horizontal direction of the data conversion processing device 202 of FIG. 3 from the parallel comparison device 1806 of FIG. 36 and adjusts to the final value of the fixed length data currently being created. Shift processing for The OR device 2102 inserts the value shifted by the shifter 2101 by OR processing with the value currently being created. The register 2103 stores the fixed length data currently being created and is updated by storing the newly inserted value of the OR device 2102. Register 2104
Stores the data generated by the OR device 2102 that satisfies the fixed length data width, and stores the data in the line memory 18 of FIG.
08 is transferred. The adder 2105 receives the effective number from the scaling pixel converting apparatus 806 of FIG. 14, and performs addition processing with the final value of the current fixed length data of the scaling pixel converting apparatus 806 in order to obtain the start value of the next shifter. . Register 21
06 stores the final value of the fixed length data, and the shifter 21
Control the shifter of 01.

FIG. 40 is a flow chart showing the processing of the halftone processing apparatus of FIG. In FIG.
The data for the horizontal MAX magnification is read in parallel from the dither pattern memory indicated by the dither pattern address generator 1804 of No. 6 (step S1301). Then, a dither pattern is cut out from the address indicated by the SHFT value for the horizontal MAX magnification to be compared by the comparison pattern cutting device 1805 in FIG. 36 (step S1302). Next, the parallel comparison device 1806 of FIG.
The magnifications are compared in parallel (step S1303). The fixed length data generator 1807 of FIG. 36 adds only the effective dots to the fixed length data as the comparison result (step S1304). Then, in the line memory address generation of FIG. 36, the address of the line memory 1808 of FIG. 36 is generated, and the data of the fixed length data generation device 1807 is written to the line memory 1808 (step S1305).
Then, the comparative pattern cutting device 1805 shown in FIG.
Adds the number of effective dots to the SHFT value and prepares for the next processing (step S1306). Whether or not the processing has been completed for all dither patterns is checked, and if not completed, then the SHFT value is checked to see if it is greater than or equal to the horizontal MAX magnification. If not, the process returns to step S1302. If there is, the value obtained by subtracting the horizontal MAX magnification from the SHFT value is set as the SHFT value, and the process returns to step S1301 to repeat the processing.

FIG. 41 shows an example of the 32 * 8 size of the dither pattern storage device of FIG. In addition, FIG.
An example of the transition of processing using the dither table of is shown. Further, FIG. 43 shows an example of the line memory of FIG.

FIG. 44 shows an overall flow when the scaling processing of the data conversion processing device 202 of FIG. 3 is the bilinear method. In the figure, first, the memory arbiter I / F 201 of FIG. 3 performs a process of obtaining a scaling factor in the vertical direction (step S1401). Memory Arbiter I in Figure 3
The / F 201 reads the image data of one line from the memory 109 of FIG. 2 via the memory arbiter 103 of FIG. 2 and sends it to the data conversion processing device 202 of FIG. 3 (step S1402). Further, similarly to step S1402, the memory arbiter I / F 201 of FIG. 3 reads one line of image data from the memory 109 of FIG. 2 via the memory arbiter 103 of FIG. 2, and transfers it to the data conversion processing device 202 of FIG. Send (step S1403). Since the bilinear interpolation method interpolates from four points A, B, C, and D as shown in FIG. 50 described later, a line memory for storing A and B and a line memory for storing C and D are required. , First read 2 lines, then C, D lines A,
The line B is read, and one line C and D is read.
Next, the memory arbiter I / F 201 of FIG. 3 reads the dither data for the number of lines after scaling in the vertical direction and sends it to the halftone processing device 203 of FIG. 3 (step S1).
404). The memory arbiter I / F 201 shown in FIG. 3 uses the vertical scaling factor obtained in step S1401 and the coordinate Y start point DYS of the destination image to determine the vertical direction D.
By DA (digital differential analysis), Y start point YS after scaling
And Y end point YE is obtained (step S1405). Then, the memory arbiter I / F 201 of FIG. 3 sets the YS value obtained in step S1404 in the vertical line counter after scaling (step S1406). Image processing of one line (magnification,
Color conversion, filter processing, etc. are performed (step S14).
07). Next, the halftone processing device 203 of FIG. 3 performs halftone processing on the image data after the image processing of one line (step S1408). Further, the halftone processing device 203 of FIG. 3 writes the 1-line data after the halftone processing to the internal line memory (step S1).
409). Furthermore, the memory arbiter I / F 201 of FIG.
Counts up the vertical line counter after scaling (step S1410). Then, in the memory arbiter I / F 201 of FIG. 3, the vertical line counter obtains the Y end point Y after scaling in the vertical direction obtained in step S1404.
It is checked whether E is exceeded or not, and if it is not exceeded, the process proceeds to step S1407 (step S1).
411; YES), and when it exceeds, the process moves to step S1412 (step S1411; NO). The memory arbiter I / F 201 of FIG. 3 writes the image-processed data from the written in-line memory to the memory 109 of FIG. 2 via the memory arbiter 103 of FIG. 2 (step S1412). Then, the memory arbiter I / F 201 of FIG. 3 checks whether or not the obtained Y end point YE after scaling in the vertical direction exceeds the coordinate Y end point DYE of the day-station image, and if it does, step S1403. Flow (step S1413; YES), and if equal or over, the process ends (step S1413; NO).

FIG. 45 is a diagram showing a timing example in the case of reducing in the vertical direction. The example shown in (a) of the figure is an example in which the reduction ratio is 0.5 times, in which one line of the image data before the image processing is skipped (only the odd line) is read, and the dither pattern data is sequentially set to one line. Each line is read, and the image-processed data is sequentially written line by line. Here, as in the flow of FIG. 44, initially, two lines are continuously read. Further, in this example, the image data reading processing and the image processing are processed in parallel. The example shown in (b) of the figure is an example in which the reduction ratio is 0.6666 times.
The image data before the image processing is read by skipping every 3 lines, the dither pattern data is sequentially read by each line, and the data after the image processing is sequentially written by each line. Here again, as in the flow of FIG. 44, initially, two lines are continuously read. Also in this example, the image data reading process and the image processing are performed in parallel.

FIG. 46 is a diagram showing a timing example in the case of equal magnification and enlargement in the vertical direction. The example shown in (a) of the figure is a 1 × example, in which image data before image processing is sequentially read line by line, dither pattern data is sequentially read line by line, and data after image processing is read. Sequentially 1
Write in each line. Here again, as in the flow of FIG. 44, initially, two lines are continuously read. Further, in this example, the image data reading processing and the image processing are processed in parallel. The example shown in (b) of the figure is an example of 105 times, in which image data before image processing is sequentially read line by line, dither pattern data is sometimes read every two lines, and data after image processing is read. Sometimes I write every two lines. Here again, as in the flow of FIG. 44, initially, two lines are continuously read. Further, in this example, the image data reading process and the image processing are performed in parallel, and sometimes the image processing of two lines is performed. Further, the example shown in (c) of the figure is a double example, in which image data before image processing is sequentially read line by line, dither pattern data is sequentially read every two lines, and after image processing is performed. Data is written sequentially after 2 lines. Here again, as in the flow of FIG. 44, initially, two lines are continuously read. Further, in this example, the image data read processing and the image processing are processed in parallel, and two-line image processing is performed.

FIG. 47 is a block diagram showing the arrangement of a scaling processing apparatus using the bilinear interpolation method. The scaling processing device shown in the figure includes a parameter processing device 2201 and an enlargement ratio generating device 2.
202, a DDA processing device 2203, an IX / IY counter device 2204, an interpolation coefficient generating device 2205, and an interpolation processing device 2206. In addition, the parameter processing device 2201 sequentially stores the input image data in the line memory and stores two lines, and then transfers WCOLA, WCOLB, WCOLC, and WCOLD at four points to be linearly interpolated to the interpolation processing device 2206. Magnification ratio generator 2202
Is the coordinates X start point SXS and X end point SXE, Y start point SYS and Y end point SYE of the source image of the image to be scaled, and coordinates X start point DXS and X end point DXE, Y start point DYS and Y of the destination image after scaling. Y end point DYE to X,
Calculate the scaling factors RATEX and RATEY in the Y direction, and
Transfer to the processing device 2203. In addition, the DDA processing device 2
Reference numeral 203 denotes a scaling factor in the X and Y directions from the enlargement ratio generating device 2202 and the coordinate X start point DXS of the destination image.
And the Y start point DYS are received, and the scaled coordinates of the input image are calculated at any time by DDA (Digital Digital Differential Analysis) like the enlarged pixel indicated by the circle in FIG. 61. In this example, an X start point, an X end point, a Y start point, and a Y end point that are interpolated for interpolation as shown in FIG.
It is transferred to the IX, IY count processing device 2204 and the interpolation coefficient generation device 2205. IX, IY counting device 22
Reference numeral 04 receives the start point and end point in the direction of interpolation and the start point and end point in the Y direction from the DDA processing device 2203, generates the X and Y coordinates of the interpolated pixel indicated by Δ in the drawing of FIG. 61, and generates the interpolation coefficient. Transfer to device 2205. Further, the interpolation coefficient generation device 2205 receives the start point and end point in the interpolation direction and the start point and end point in the Y direction from the DDA processing device 2203, and from the X and Y coordinates of the pixel to be interpolated from the IX and IY counting device 2204, Interpolation coefficients in the X and Y directions (DRATEY, DRATEX) to be interpolated by the interpolation processing device 2206
Is calculated and sent to the interpolation processing device 2206. Further, the interpolation processing device 2206 receives the data to be interpolated from the parameter processing device 2201, and receives the coefficient to be interpolated from the interpolation coefficient generation device 2205 to interpolate the data from the parameter processing device 2201.
As described above, the scaling process is executed by generating an enlarged image by interpolating and filling the enlarged pixels.

FIG. 48 is a flow chart showing the processing of the scaling processing apparatus of FIG. In the figure, first, the enlargement ratio is generated by the enlargement ratio generation processing device (step S150).
1). Then, the DDA processing device performs the DDA processing in the Y direction (vertical direction) to obtain the Y start point YS and the Y end point YE to be processed (step S1502). The YS coordinate is designated as the Y coordinate (horizontal line) processed by the IX, IY count processing device (step S1503). The X coordinate processed by the IX, IY count processing device is initialized to the coordinate X start point DXS of the destination image (step S15).
04). The DDA processing device performs DDA processing in the X direction (horizontal direction), and obtains an X start point XS and an X end point XE to be processed (step S1505). Next, the interpolation coefficient generation processing device that reads the interpolation data obtains the interpolation coefficient at the coordinates currently processed (steps S1506 and S150).
7). The interpolating device interpolates between the enlarged pixels to generate a scaled image (step S150).
8). If XE does not exceed the coordinate X end point DXE of the scaled date image, step S150.
The process is returned to 5 (step S1509; YES). If it exceeds, the IX, IY count processing device obtains the Y coordinate to be interpolated next (step S1509; NO,
Step S1510). The Y value end point YE that the value interpolates
If it does not exceed, the process returns to step S1504 (step S1511; YES). If YE does not exceed the coordinate Y end point DYE of the scaled date image, the process returns to step S1502 (step S1512; YES).

FIG. 49 is a block diagram showing the structure of the parameter processing device shown in FIG. The parameter processing device shown in the figure includes a register 2301 for storing even-numbered pixels of input pixels, a register 2302 for storing odd-numbered pixels of input pixels, line memories 2303 to 2305 for storing pixels of lines, Line memory 2303-2
A selector 2306 for controlling and outputting the data stored in 305 and a controller 2307 are included. For example, when outputting the data of the line memory 2303 and the line memory 2304, the pixels A and B in which the line memory 2303 is interpolated and the pixels C and D in which the line memory 2304 is interpolated are output as follows.
The line memory 2305 stores the next pixel.

This parameter processing device stores image data sequentially input from the scan line direction for two lines as shown in FIG. 50, and sequentially stores four interpolated points in FIG. 51 in FIG.
To output. At this time (when outputting four interpolated pixels), the input pixels are sequentially received by the third line memory. When the third line memory is full and the vertical interpolation as shown in FIG. 52 is not completed, WAIT is applied to the device that sends the input pixel. Then, when all of the pixels accumulated in two lines in the vertical direction are completed as shown in FIG. 52, from the accumulated third pixel and the latter half one line of the previously processed two-line pixels,
New two lines of pixels are formed, and similarly to the above, as shown in FIG. 52, four interpolated pixels are sequentially output. Then, similarly to the above, the input pixels are sequentially stored in the vacant one-line memory as the third line memory.

FIG. 53 is a block diagram showing the structure of the enlargement ratio generating device of FIG. The enlargement factor generation device shown in FIG.
It is configured to include subtractors 2401, 402, 2405, 2406, dividers 2403, 2407, and registers 2404, 2408. The magnifying power generation device having such a configuration has the coordinates X start point SXS and X end point SXE of the source image of the image to be scaled, Y start point SYS and Y end point SY.
E and the coordinate X start point D of the day-change image after scaling
XS and X end point DXE, Y start point DYS and Y end point DYE
47, the scaling factors RATEX and RATEY in the X and Y directions are obtained and transferred to the DDA processing device 2203 in FIG. RA
The scaling factor (RATEX) in the X direction is obtained by the calculation of TEX = (SXE-SXS) / (DXE-DXS), and (the coordinate X start point SXS and X end point SSX of the source image, the coordinate X start point DXS of the destination image) And X end point DX
E), RATEY = (SYE-SYS) / (DYE-D
YS) is used to calculate the scaling factor (RATEY) in the Y direction, and the (source image coordinates Y start point SYS, Y end point SY) are calculated.
E, coordinate Y of day-station image Y start point DYS, Y
End point DYE).

FIG. 54 is a block diagram showing the structure of the DDA processing apparatus shown in FIG. The DDA processing device shown in FIG.
MUX 2501 and 2507, registers 2502 and 250
3,2505,2506,2508,2509,251
1 and 512, and adders 2504 and 2510. The MUX 2501 also transfers the initial value of the coordinate X start point DXS of the destination image to the register 2502 only, and then sends the output of the adder 2504 that is sequentially added. The register 2502 stores the X value currently being processed. The register 2503 stores the X-direction scaling ratio RATEX calculated by the scaling ratio generator. The register 2505 stores the X end point for interpolation.
The register 2506 stores the X start point for interpolation. MU
The X2507 transfers the initial value of the coordinate Y start point DYS of the destination image to the register 2508 only, and then sends the output of the adder 2510 that is sequentially added. The register 2508 stores the Y value currently being processed. The register 2509 stores Y obtained by the scaling ratio generator.
The direction scaling factor RATEY is stored. Register 2511
Stores the Y end point to be interpolated. Register 2512
The Y start point for interpolation is stored.

According to the DDA processing apparatus having such a configuration, X, Y from the enlargement factor generating apparatus 2201 of FIG.
The scaling factor in the direction and the coordinates X start point DXS and Y start point DYS of the destination image are received, and the scaled coordinates of the input image are set to DDA (, as in the enlarged pixel indicated by ◯ in FIG. 61). It is obtained at any time by digital differential analysis). In this example, the X start point, X end point, Y start point, and Y end point to be interpolated for interpolation as shown in FIG.
It is transferred to the X, IY count processing device 2204 and the interpolation coefficient generation device 2205. Further, the X-direction DDA processing device has a structure in which the X-direction scaling ratio RATEX obtained by the scaling ratio generating device is sequentially added to the current X coordinate as shown in FIG. 12, and the Y-direction DDA processing device is as shown in FIG. In addition, RATEY obtained by the scaling factor generator is sequentially added to the current Y coordinate.

FIG. 55 is a block diagram showing the structure of the interpolation coefficient generating device shown in FIG. The interpolation coefficient generation device shown in the figure includes subtracters 2601, 2602, 2605, 2606,
Dividers 2603, 2607, 2608, register 260
4, 2609 are included. The interpolation coefficient generation device having such a configuration receives the start point and end point in the X direction and the start point and end point in the Y direction to be interpolated from the DDA processing device 2203 of FIG. 47, and receives from the IX and IY counting device 2204 of FIG. From the X and Y coordinates of the pixel to be interpolated, as shown in FIG.
No. 7 interpolation processing device 2206 obtains interpolation coefficients (DRATEY, DRATEX) in the X and Y directions to be interpolated, and sends them to the interpolation processing device 2206. DRATEX = (IX-XS) /
By the calculation of (XE-XS), the interpolation coefficient (DRA
TEX), the start and end points (XS, XE) in the X direction obtained by the DDA processing device 2203, the X coordinate (IX) of the pixel to be interpolated from the IX, IY counting device 2204,
DRATEY = (IY-YS) / (YE-YS) is calculated to obtain the interpolation coefficient (DRATEY) in the Y direction, and DD
The start and end points (YS, YE) in the Y direction obtained by the A processing unit 2203, and the Y coordinate (IY) of the pixel to be interpolated from the IX, IY counting unit 2204 are obtained.

Further, at this time, since the present method sequentially obtains each horizontal line as shown in FIG. 52, the calculation of DRATEY is required only once for each line, and the amount of calculation is small. In addition, the amount of hardware is reduced and the speed is increased.

FIG. 56 is a block diagram showing the structure of the interpolation processing device shown in FIG. The interpolation processing device shown in the figure includes a vertical interpolation processing device 2701 and a horizontal interpolation coefficient generation device 270.
2. A horizontal interpolation processing device 2703 is included. Further, the vertical interpolation processing device 2701 uses the interpolation coefficient (DRATE) obtained by the interpolation coefficient generation device 2205 of FIG.
By Y), the difference value of the position of the current line (Y coordinate) from the Y start point can be obtained, and the vertically interpolated AV and BV in FIG. 51 can be obtained. Horizontal interpolation coefficient generator 2702
47, the interpolation coefficient (DRATEX, 1 / DX) obtained by the interpolation coefficient generation device 2205 in FIG. 47 is used to find the horizontal interpolation coefficient in parallel up to the horizontal MAX enlargement factor that can be processed by this scaling processing device. In this example, since the scaling processing device is up to eight times in the horizontal direction, eight interpolation coefficients in the horizontal direction are obtained in parallel. Horizontal interpolation processing device 270
3 receives the vertical interpolation points WCOLAV and WCOLBV obtained by the vertical interpolation processing device 2701, and the values of the plurality of interpolation points are calculated from the plurality of interpolation coefficients obtained by the horizontal interpolation coefficient generation device 2702 between these two points. Ask for. At this time, the actual number to be interpolated is counted by the effective number counting device.

The interpolation processing device having such a configuration is
By receiving the data to be interpolated from the parameter processing device 2201 of FIG. 47 and the coefficient to be interpolated from the interpolation coefficient generation device 2205, the parameter processing device 22
By interpolating the data from 01, the enlarged pixels are interpolated and filled as shown in FIG. 57 to generate an enlarged image, thereby executing the scaling process. As an interpolation method, a bilinear interpolation method will be shown here as an example. FIG. 51 shows an example of the bilinear interpolation method. Here, each line is sequentially interpolated in the horizontal direction as shown in FIG. 52. Therefore, as shown in FIG.
And B and D are vertically interpolated to obtain AV and BV, and thereafter, as shown in FIG. 51B, the AV and BV are horizontally interpolated to obtain P. In this case, depending on the hardware configuration, the obtained BV can be reused as the next AV, leading to a reduction in interpolation calculation, a reduction in the amount of hardware, and an increase in speed.

FIG. 58 is a block diagram showing the structure of the vertical interpolation processing device shown in FIG. Note that the processing here is as shown in FIG.
This corresponds to the processing of (a). The vertical interpolation processing device shown in the figure includes a subtracter 2801 for obtaining the difference between two left pixels of pixel data of four points obtained by the parameter processing device, a DRATEY value obtained by the interpolation coefficient generating device, and a subtracter 2801. An adder 2803 and an adder 2803 that obtain a value interpolated in the vertical direction at the left end by adding the obtained value and the start point by a multiplier 2802 and a multiplier 2082 that obtain a position without difference by multiplying the difference 2804, a subtracter 2805 that obtains the difference between the right two pixels of the pixel data of four points obtained by the parameter processing device, the DRATEY value obtained by the interpolation coefficient generation device and the subtractor 28
The multiplier 2806 that obtains the position without the difference by multiplying the difference of No. 05, and the adder 2807 that obtains the value interpolated in the vertical direction at the right end by adding the value obtained by the multiplier 2806 and the start point A register 2808 for storing the value of the container 2807 is included.

FIG. 59 is a block diagram showing the structure of the horizontal interpolation coefficient generating device shown in FIG. The horizontal interpolation coefficient generation device shown in the figure adds the value of DRATEX obtained by the interpolation coefficient generation device and 1 / DX to obtain a second interpolation in the horizontal direction next to the DRATEX obtained by the interpolation coefficient generation device. By adding the value of the second interpolation coefficient and 1 / DX in the horizontal direction obtained by the adder 2901 and the adder 2907 for obtaining the coefficient, there are three in the horizontal direction next to DRATEX obtained by the interpolation coefficient generation device An adder 2906 for obtaining an eye interpolation coefficient,
Addition for obtaining the fourth interpolation coefficient in the horizontal direction next to DRATEX obtained by the interpolation coefficient generation device by adding the value of the third interpolation coefficient obtained by the adder 2906 and 1 / DX in the horizontal direction By adding the value of the fourth interpolation coefficient and 1 / DX in the horizontal direction obtained by the adder 2905 and the adder 2905, the fifth interpolation coefficient in the horizontal direction next to DRATEX obtained by the interpolation coefficient generation device. Adder 290 for calculating
4, by adding the value of the fifth interpolation coefficient in the horizontal direction obtained by the adder 2904 and 1 / DX, the sixth interpolation coefficient in the horizontal direction next to DRATEX obtained by the interpolation coefficient generation device is obtained. The adder 2903 to be obtained, and the value of the sixth interpolation coefficient obtained by the adder 2903 in the horizontal direction and 1 / DX are added to obtain the DRATEX obtained by the interpolation coefficient generating device.
Adder 29 for obtaining the seventh interpolation coefficient in the horizontal direction next to
02, the value of the seventh interpolation coefficient obtained by the adder 2902 in the horizontal direction and 1 / DX are added to obtain the eighth interpolation coefficient in the horizontal direction next to DRATEX obtained by the interpolation coefficient generation device. An adder 2901 to be obtained, a register 2915 for storing the value of DRATEX obtained by the interpolation coefficient generation device,
A register 2914 for storing the value of the second interpolation coefficient in the horizontal direction obtained by the adder 2907, a register 2913 for storing the value of the third interpolation coefficient in the horizontal direction obtained by the adder 2906, and an adder 2905. A register 2912 for storing the obtained value of the fourth interpolation coefficient in the horizontal direction and an adder 29
A register 2911 for storing the value of the fifth interpolation coefficient in the horizontal direction obtained in 04, a register 2910 for storing the value of the sixth interpolation coefficient in the horizontal direction obtained by the adder 2903,
It is configured to include a register 2909 for storing the value of the seventh interpolation coefficient in the horizontal direction obtained by the adder 2902 and a register 2908 for storing the value of the eighth interpolation coefficient in the horizontal direction obtained by the adder 2901. ing.

FIG. 60 is a block diagram showing the structure of the horizontal interpolation processing apparatus shown in FIG. Note that the processing here is as shown in FIG.
This corresponds to the process (b) of The horizontal interpolation processing device shown in the figure is a subtractor 302 that calculates a horizontal difference between pixel data of two points interpolated in the vertical direction calculated by the vertical interpolation processing device.
5. Multiplier 3001 for finding the value to be complemented during the difference by multiplying the pixel difference found by the subtractor 3025 by the first interpolation coefficient in the horizontal direction found by the horizontal interpolation coefficient generator , The value obtained by the adder 3009 and the value obtained by the adder 3009 are stored by adding the value of WCOLAV that is the vertical interpolation result and the multiplication result of the multiplier 3001. Register 3017,
A multiplier 3002 that obtains a complemented value in the difference by multiplying the pixel difference obtained by the subtractor 3025 and the second interpolation coefficient in the horizontal direction obtained by the horizontal interpolation coefficient generation device. An adder 3010 for obtaining the second pixel value interpolated in the horizontal direction by adding the value of WCOLAV, which is the result of multiplication in the adder 3002, and the result of vertical interpolation, and a register 3018 for storing the value obtained by the adder 3010 , A multiplier 30 that obtains a value to be complemented during the difference by multiplying the pixel difference obtained by the subtractor 3025 by the third interpolation coefficient in the horizontal direction obtained by the horizontal interpolation coefficient generation device.
03, the adder 3011 and the adder 30 which obtain the third pixel value interpolated in the horizontal direction by adding the value of WCOLAV which is the vertical interpolation result to the multiplication result of the multiplier 3003
Register 3019 for storing the value obtained in 11 and subtractor 3
Multiplier 300 that obtains the value to be complemented during the difference by multiplying the pixel difference obtained in 025 by the fourth interpolation coefficient in the horizontal direction obtained by the horizontal interpolation coefficient generation device.
4, the result of multiplication by the multiplier 3004 and the result of vertical interpolation
An adder 3012 and an adder 301 that obtain the fourth pixel value interpolated in the horizontal direction by adding the WCOLAV values
Register 3020 for storing the value obtained in 2 and subtractor 30
Multiplier 3005 that obtains a complemented value in the difference by multiplying the pixel difference obtained in step 25 by the fifth interpolation coefficient in the horizontal direction obtained by the horizontal interpolation coefficient generation device.
WCOL which is the multiplication result and vertical interpolation result in the multiplier 3005
An adder 3013 that obtains the fifth pixel value horizontally interpolated by adding the AV values, a register 3021 that stores the value obtained by the adder 3013, and a subtractor 3025
By multiplying the difference between the pixels obtained in step 6 and the sixth interpolation coefficient in the horizontal direction obtained by the horizontal interpolation coefficient generation device,
Addition for obtaining the sixth pixel value interpolated in the horizontal direction by adding the multiplication result in the multiplication unit 3006 and the value of WCOLAV which is the vertical interpolation result for obtaining the complemented value in the difference By multiplying the pixel difference calculated by the register 3022 that stores the values calculated by the adder 3014 and the adder 3014 and the subtractor 3025 by the seventh interpolation coefficient in the horizontal direction calculated by the horizontal interpolation coefficient generation device. , Multiplier 3007 and Multiplier 3 for obtaining the complemented value in the difference minutes
An adder 3015 that obtains the seventh pixel value horizontally interpolated by adding the value of WCOLAV that is the result of multiplication and the result of vertical interpolation in 007, a register 3023 that stores the value obtained by the adder 3015, A multiplier 3008, which calculates a value to be complemented in the difference by multiplying the pixel difference calculated by the subtractor 3025 by the eighth interpolation coefficient in the horizontal direction calculated by the horizontal interpolation coefficient generation device, Bowl 300
8 by adding the value of WCOLAV which is the result of vertical interpolation and the result of vertical interpolation, adder 3016 that obtains the eighth pixel value interpolated in the horizontal direction, register 3024 that stores the value obtained by adder 3016, It is configured to include an effective number counting device 3026 that obtains an effective number by counting from a time point at which eight interpolation coefficients in the horizontal direction exceed “1.0” from the first coefficient.

It is needless to say that the present invention is not limited to the above embodiments, and various modifications and substitutions can be made within the scope of the claims.

[0087]

As described above, the image processing apparatus of the present invention includes a memory arbiter I / F that arbitrates requests to a memory arbiter that performs image reading processing, dither data reading processing, and post-processing writing processing. , Data conversion processing means for performing image processing from the memory arbiter I / F to horizontal line image data, and the memory arbiter I / F
Halftone processing means for performing halftone processing on dither data corresponding to the number of lines after scaling of each vertical line from F and data for each horizontal line after image processing from the data conversion processing means, and data conversion. It is characterized by having means. Therefore, the image data reading process and the image processing can be performed in parallel without interrupting the image data reading process, and the speed can be increased.

Further, the memory arbiter I / F means performs a scaling process in the vertical direction, selects necessary dither data according to the scaling factor in the vertical direction, and reads it.
Can speed up.

Further, the data conversion means has a scaling processing means for carrying out scaling processing by the nearest neighbor method. Therefore, it is possible to perform high-speed processing without needing an unnecessary work memory area for performing the halftone processing directly after scaling the image.

Further, the data conversion means has a scaling processing means for carrying out scaling processing by the bilinear interpolation method. Therefore, it is possible to perform high-speed processing without needing an unnecessary work memory area for performing the halftone processing directly after scaling the image.

Further, the scaling processing means has a scaling pixel coefficient generating means capable of scaling processing the same number of pixels in parallel as the halftone processing means in parallel, and outputs the image data. Performs halftone processing directly. Therefore, it is possible to perform high-speed processing without needing a useless work memory area, and it is possible for the scaling processing unit to constantly generate pixels for the number of parallel processings of the halftone processing unit. It can be processed at high speed.

The scaled pixel coefficient generation means receives parallel X width generation means capable of obtaining the X width of the same number of pixels as the number of parallel processings of the halftone processing means, and the plurality of X widths, And an output X width generating means for outputting the divided half-tone processing means in parallel. Therefore, since the scaling processing is performed in parallel in the horizontal direction, the processing can be performed at high speed.

Further, the halftone processing means includes parallel comparison means for comparing a plurality of pixels in the horizontal direction in parallel, and a plurality of threshold matrixes in the horizontal direction received from the dither pattern memory from the pixel to be currently compared in the horizontal direction. And a comparison pattern cutout unit that cuts out a plurality of threshold matrices. Therefore, since the halftone processing is performed in parallel in the horizontal direction, the processing can be performed at high speed.

Further, the comparison pattern cut-out means makes a plurality of horizontal threshold matrixes received from the dither pattern memory from the effective pixel number received from the scaling processing means and a plurality of horizontal threshold matrixes from the current pixel to be compared. Cut out. Therefore, since the halftone processing is performed in parallel in the horizontal direction, the processing can be performed at high speed.

Further, the halftone processing means includes a parallel comparing means for comparing a plurality of pixels in the horizontal direction in parallel and a plurality of threshold matrixes in the horizontal direction received from the dither pattern memory from the current pixel to be compared in the horizontal direction. A plurality of pixels in the horizontal direction received from the comparison pattern cutout unit and the parallel comparison unit that cuts out a plurality of threshold matrices,
It has a fixed length generation means for inserting into the fixed length data by the number of effective pixels received from the scaling processing means. Therefore, since the halftone processing is performed in parallel in the horizontal direction, the processing can be performed at high speed.

Further, the scaling processing means is capable of horizontally maximizing
Pixels are obtained in parallel for the magnification of, and pixels are obtained in parallel for the magnification of MAX in the horizontal direction. Therefore, since the scaling processing is performed in parallel in the horizontal direction, the processing can be performed at high speed.

Further, the scaling processing means is capable of maximizing in the horizontal direction.
It has a horizontal interpolation means for calculating in parallel the pixels for the magnification and the effective number counting means for obtaining the effective number of the pixels.
Therefore, since the scaling processing is performed in parallel in the horizontal direction, the processing can be performed at high speed.

[Brief description of drawings]

FIG. 1 is a sectional view showing a configuration of a multicolor image forming apparatus to which an image processing apparatus of the present invention is applied.

FIG. 2 is a block diagram showing a configuration of the electrical equipment / control device of FIG.

FIG. 3 is a block diagram showing a configuration of an image processing apparatus according to an embodiment of the present invention.

FIG. 4 is a diagram showing a configuration of the data conversion processing device of FIG.

5 is a flowchart showing the operation of the data conversion processing device 202 of FIG. 3 when the scaling processing is the nearest neighbor method.

FIG. 6 is a diagram showing a timing example in the case of reducing in the vertical direction.

FIG. 7 is a diagram showing a timing example in the case of equal magnification and enlargement in the vertical direction.

8 is a block diagram showing a detailed peripheral configuration of the memory arbiter I / F of FIG.

9 is a block diagram showing a configuration of a memory arbiter I / F of FIG.

FIG. 10 is a block diagram showing a configuration of the scaling factor generating apparatus of FIG.

11 is a block diagram showing the configuration of the Y DDA processing device of FIG. 9. FIG.

12 is a block diagram showing a configuration of the IY counter device of FIG.

13 is a block diagram showing the configuration of the memory address generation device of FIG. 9.

FIG. 14 is a block diagram showing a configuration of a scaling processing apparatus of a nearest neighbor method.

FIG. 15 is a diagram showing how a pixel to be scaled is changed to a width from a scaled pixel generation device.

16 is a flowchart showing the operation of the scaling processing device of FIG.

17 is a block diagram showing a configuration of the original pixel storage device of FIG. 14. FIG.

FIG. 18 is a block diagram showing the configuration of the scaling factor generating apparatus of FIG.

19 is a block diagram showing a configuration of the DDA processing device of FIG.

20 is a block diagram showing the configuration of the IX counting device of FIG.

21 is a block diagram showing a configuration of a variable pixel coefficient generation device of FIG. 14. FIG.

22 is a diagram showing the configuration of the parallel X width generation device in FIG. 21. FIG.

23 is a block diagram showing the configuration of the output X width generation device in FIG. 21. FIG.

FIG. 24 is a block diagram showing a configuration of a cumulative addition processing device of FIG. 23.

FIG. 25 is a flowchart showing a process of the XWIDTH update processing device of FIG. 23.

FIG. 26 is a flowchart showing processing of the output XWIDTH generation processing device of FIG. 23.

FIG. 27 is a block diagram showing the configuration of the cumulative addition processing device of FIG. 23.

28 is a flowchart showing the 0th processing of the output pixel of the variable-magnification pixel conversion apparatus of FIG.

29 is a flowchart showing a first process of output pixels of the variable-magnification pixel conversion apparatus of FIG.

FIG. 30 is a diagram showing a second processing flow of output pixels of the variable-magnification pixel conversion device of FIG. 14;

FIG. 31 is a diagram showing a third processing flow of output pixels of the variable-magnification pixel conversion device of FIG. 14;

FIG. 32 is a diagram showing a fourth processing flow of output pixels of the variable-magnification pixel conversion device of FIG. 14;

FIG. 33 is a diagram showing a fifth processing flow of output pixels of the variable-magnification pixel conversion device of FIG. 14;

FIG. 34 is a diagram showing a sixth processing flow of output pixels of the variable-magnification pixel conversion device of FIG. 14;

35 is a diagram showing a seventh processing flow of output pixels of the variable-magnification pixel conversion apparatus of FIG.

FIG. 36 is a diagram showing a configuration of a halftone processing device.

FIG. 37 is a block diagram showing a configuration of the comparative pattern cutout device of FIG. 36.

FIG. 38 is a block diagram showing the configuration of the parallel comparison device of FIG. 36.

FIG. 39 is a block diagram showing a configuration of the fixed-length data generation device of FIG. 36.

40 is a flowchart showing processing of the halftone processing apparatus of FIG. 36.

41 is 32 * 8 of the dither pattern storage device of FIG.
It is a figure which shows the example of the size of.

FIG. 42 is a diagram showing an example of transition of processing using the dither table of FIG. 41.

FIG. 43 is a diagram showing an example of the line memory of FIG. 36.

44 is a diagram showing an overall flow when the scaling processing of the data conversion processing device 202 of FIG. 3 is a bilinear method.

[Fig. 45] Fig. 45 is a diagram illustrating a timing example in the case of reducing in the vertical direction.

FIG. 46 is a diagram showing a timing example in the case of equal magnification and enlargement in the vertical direction.

[Fig. 47] Fig. 47 is a block diagram illustrating a configuration of a scaling processing device using a bilinear interpolation method.

48 is a flowchart showing the processing of the scaling processing device of FIG. 47. FIG.

49 is a block diagram showing the configuration of the parameter processing device of FIG. 47.

FIG. 50 is a diagram showing image data sequentially input from the scan line direction.

FIG. 51 is a diagram showing interpolated image data.

FIG. 52 is a diagram showing how interpolation is performed.

53 is a block diagram showing a configuration of the enlargement ratio generation device of FIG. 47.

54 is a block diagram showing a configuration of the DDA processing device of FIG. 47.

55 is a block diagram showing a configuration of the interpolation coefficient generation device in FIG. 47.

56 is a block diagram showing the configuration of the interpolation processing device in FIG. 47.

[Fig. 57] Fig. 57 is a diagram illustrating a state where interpolation is performed between enlarged pixels.

58 is a block diagram showing a configuration of the vertical interpolation processing device of FIG. 56.

59 is a block diagram showing the configuration of the horizontal interpolation coefficient generation device in FIG. 56.

FIG. 60 is a block diagram showing the configuration of the horizontal interpolation processing device in FIG. 56.

FIG. 61 is a diagram showing a state of a pixel stored in a direct memory access circuit.

[Explanation of symbols]

103; memory arbiter, 112; image processing device, 201; memory arbiter I / F, 202; data conversion processing device, 203; halftone processing device, 204; parameter storage device.

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[Procedure amendment]

[Submission date] January 18, 2002 (2002.1.1
8)

[Procedure Amendment 1]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 5

[Correction method] Change

[Correction content]

[Figure 5]

[Procedure Amendment 2]

[Document name to be corrected] Drawing

[Name of item to be corrected] Fig. 14

[Correction method] Change

[Correction content]

FIG. 14

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Claims (11)

[Claims] 1. A memory arbiter I / F that arbitrates a request to a memory arbiter that performs an image reading process, a dither data reading process, and a post-processing writing process, and horizontal line image data from the memory arbiter I / F. Data conversion processing means for performing image processing, dither data for the number of lines after scaling of each vertical line from the memory arbiter I / F, and data for each horizontal line after image processing from the data conversion processing means An image processing apparatus having a halftone processing means for performing a halftone processing on the above and a data conversion means. 2. The image processing apparatus according to claim 1, wherein the memory arbiter I / F means performs a scaling process in the vertical direction and selects and reads necessary dither data according to the scaling factor in the vertical direction. 3. The image processing apparatus according to claim 1, wherein the data conversion unit includes a scaling processing unit that performs scaling processing by a nearest neighbor method. 4. The data conversion means has a scaling processing means for performing scaling processing by a bilinear interpolation method.
The image processing device described. 5. The scaling processing means includes scaling pixel coefficient generation means capable of scaling processing the same number of pixels in parallel as the halftone processing means in parallel, 4. The data is directly halftoned.
The image processing device described. 6. The scaled pixel coefficient generation means is capable of calculating the X width of the same number of pixels as the number of parallel processings of the halftone processing means, and a plurality of X widths thereof.
The image processing apparatus according to claim 5, further comprising an output X-width generation unit that receives the width and outputs the divided width into the number of parallel processings of the halftone processing unit. 7. The halftone processing means includes a parallel comparing means for comparing a plurality of pixels in a horizontal direction in parallel, and a plurality of horizontal threshold values received from a dither pattern memory in a horizontal direction from a pixel for current comparison. The image processing apparatus according to claim 1, further comprising a comparison pattern cutout unit that cuts out a plurality of threshold matrixes in a direction. 8. The comparison pattern cut-out means outputs a plurality of threshold matrixes in the horizontal direction received from the dither pattern memory from the number of effective pixels received from the scaling processing means from the current pixel to be compared in the horizontal direction. The image processing device according to claim 7, wherein a threshold matrix is cut out. 9. The halftone processing means includes a parallel comparison means for comparing a plurality of pixels in a horizontal direction in parallel and a plurality of threshold matrixes in a horizontal direction received from a dither pattern memory from a pixel to be currently compared in the horizontal direction. A plurality of pixels in the horizontal direction received from the comparison pattern cutout means and the parallel comparison means for cutting out a plurality of threshold matrices into
2. The image processing apparatus according to claim 1, further comprising fixed length generation means for inserting into the fixed length data the number of effective pixels received from the scaling processing means. 10. The magnifying processing means is adapted to horizontally extend the MA.
5. The image processing apparatus according to claim 4, wherein pixels are calculated in parallel for the magnification of X and pixels are calculated in parallel for the magnification of MAX in the horizontal direction. 11. The magnifying processing means is configured to horizontally adjust the MA.
11. The image processing apparatus according to claim 10, further comprising a horizontal interpolation unit that calculates pixels for a magnification of X in parallel, and an effective number counting unit that obtains an effective number of the pixels.