JP2003197598A - Manufacturing method for semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a surface of a semiconductor wafer from occurrence of a water mark after the semiconductor wafer is cleaned and dried by using a single wafer process cleaning device. <P>SOLUTION: A tilt face 22 is formed on an upper face of a chuck pin 17 supporting a semiconductor substrate 1, a groove portion 23 is formed as surrounding a projection portion 18 formed on the upper face of the chuck pin 17, a groove portion 24 of a plane rectangular shape is formed on the upper face of the projection portion 18, and a groove portion 25 of a plane rectangular shape is formed on the tilt face 22. A part of the groove portion 23 is formed to reach the side face off the chuck pin 17, a lengthwise side of the groove portion 24 is formed to extend toward the center of the semiconductor substrate 1 and a lengthwise side of the groove portion 25 extends to the center direction of the semiconductor substrate 1 from the vicinity of the center of the plane face of the chuck pin 17 and is formed to communicate with the groove portion 23. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device manufacturing technique, and more particularly to a technique effectively applied to a semiconductor wafer cleaning process using a single wafer cleaning device.

[0002]

2. Description of the Related Art With the recent increase in the diameter of semiconductor wafers,
Since a cleaning apparatus used in a semiconductor wafer cleaning process also becomes large, a single-wafer cleaning apparatus that is smaller than a batch-type cleaning apparatus is drawing attention. A single-wafer type semiconductor wafer cleaning apparatus, for example, mounts a semiconductor wafer on a spin base and presses a rotating brush while moving a cleaning solution against the cleaning surface of the semiconductor wafer to move it to scrub and clean the semiconductor wafer. This is a method in which chemicals, pure water, etc. are wiped and cleaned while rotating one by one. Such a single-wafer cleaning apparatus is described in, for example, November 25, 1998, published by Kogyo Kogyo Kaisha, VLSI manufacturing / testing apparatus guidebook 1999 edition, p110 to p114.

[0003]

In the above-mentioned single-wafer cleaning apparatus, since the semiconductor wafer mounted on the spin base is rotated at high speed in the drying process, the chuck mechanism for fixing the semiconductor wafer to the spin base is provided. A plurality of semiconductor wafers are arranged along the outer circumference of the semiconductor wafer. However,
The present inventors have found that the chuck mechanism has the following problems.

That is, in the above chuck mechanism, since the contact portion with the semiconductor wafer is a flat surface, it is difficult to remove the water that has penetrated into the contact portion even by high speed rotation. The water content becomes a watermark after the drying step and remains on the surface of the semiconductor wafer. This watermark is an H ₂ O coagulation dry product (H ₂ S) due to Si (silicon) and moisture forming a semiconductor wafer.
iO ₃ hydrate), which involves the problems of short-circuiting the wiring and degrading the oxide film after the drying step.

An object of the present invention is to provide a technique capable of preventing generation of a watermark on the surface of a semiconductor wafer after cleaning and drying the semiconductor wafer using a single wafer cleaning apparatus. is there.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0007]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

That is, the present invention includes a step of cleaning a semiconductor substrate by using a single wafer cleaning device, the cleaning device having a plurality of chuck pins for supporting the semiconductor substrate, and an upper surface of the chuck pin. In, a protrusion, a first groove surrounding the protrusion and a second groove extending from the first groove are formed, and the upper surface of the chuck pin excluding the protrusion, the first groove and the second groove has an upper surface. An inclined surface is formed, and a third groove is formed on the upper surface of the protrusion,
Part of the first groove reaches the side surface of the chuck pin,
The second groove portion and the third groove portion extend from the plane center of the protrusion toward the center of the semiconductor substrate.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. In all the drawings for explaining the embodiments, members having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

(First Embodiment) A semiconductor integrated circuit device according to the first embodiment is, for example, a CMOS logic LSI. Regarding the manufacturing method of this CMOS logic LSI,
This will be described with reference to FIGS.

First, as shown in FIG. 1, the specific resistance is 10Ω.
A semiconductor substrate (semiconductor wafer) 1 having a diameter of about 6 inches (about 15.24 cm), which is made of single crystal silicon of about cm.
Is heat-treated at about 850 ° C., and its main surface has a film thickness of 10 nm.
A thin silicon oxide film (pad oxide film) is formed. In the first embodiment, the case where the diameter of the semiconductor substrate 1 is about 6 inches is used as an example.
It is not limited to this. Then, a silicon nitride film with a thickness of about 120 nm is formed on the silicon oxide film by C
After depositing by VD (Chemical Vapor Deposition) method,
The silicon nitride film and the silicon oxide film in the element isolation region are removed by dry etching using the photoresist film as a mask. The silicon oxide film is formed for the purpose of relieving stress applied to the substrate when the silicon oxide film embedded in the element isolation trench is densified (baked up) in a later step. In addition, since the silicon nitride film has a property of being hard to be oxidized, it is used as a mask for preventing the oxidation of the substrate surface below it (active region).

Then, the semiconductor substrate 1 in the element isolation region is formed to a depth of 3 by dry etching using a silicon nitride film as a mask.
After the element isolation trenches 2 having a thickness of about 50 nm are formed, the semiconductor substrate 1 is heat-treated at about 1000 ° C. to remove the damage layer generated on the inner walls of the element isolation trenches 2 by etching, and the film thickness on the inner walls of the trenches is about 10 nm. Forming a thin silicon oxide film.

Then, after depositing the silicon oxide film 3 on the semiconductor substrate 1 by the CVD method, the semiconductor substrate 1 is heat-treated to densify the silicon oxide film 3 in order to improve the quality of the silicon oxide film 3. (Bake down). After that, the silicon oxide film 3 is polished by a chemical mechanical polishing (CMP) method using a silicon nitride film as a stopper and left inside the element isolation trench 2 to flatten the surface of the device. Form isolation regions.

Subsequently, after removing the silicon nitride film remaining on the active region of the semiconductor substrate 1 by wet etching using hot phosphoric acid, the n-channel MISF of the semiconductor substrate 1 is removed.
B (boron) is ion-implanted into the region where ET is formed, and p
A mold well 4 is formed. Then, P (phosphorus) is ion-implanted into the region of the semiconductor substrate 1 where the p-channel type MISFET is to be formed to form the n-type well 5. Then, the semiconductor substrate 1 is heat-treated to form the p-type wells 4 and n.
A gate oxide film 6 is formed on the surface of the mold well 5.

Next, as shown in FIG. 2, a low resistance polycrystalline silicon film 7 doped with, for example, P is deposited. Next, after performing a visual inspection of the semiconductor substrate 1 on which the polycrystalline silicon film 7 is deposited, a cleaning process is performed on the semiconductor substrate 1. In this cleaning process, first, the semiconductor substrate 1 is cleaned by cleaning with a cleaning brush and a brush using a chemical solution. Then, after cleaning the back surface of the semiconductor substrate 1, for example, HF
The semiconductor substrate 1 is washed with (hydrofluoric acid). afterwards,
The cleaning process is completed by performing, for example, a pure water rinse process and a spin drying process on the semiconductor substrate 1 (see FIG. 3).

The above-mentioned cleaning process can be carried out by using a single-wafer cleaning device as shown in FIG. 4, for example. In this cleaning apparatus, a wafer cassette 12 is set in a housing 11, and the wafer cassette 12 houses a plurality of semiconductor substrates 1 on which the polycrystalline silicon film 7 is deposited. The semiconductor substrate 1 is taken out of the wafer cassette 12 by an indexer 13 that can move up and down and move in parallel in the horizontal direction. Indexer 13
The semiconductor substrate 1 taken out by is transferred to the transfer mechanism 14 and transferred to the cup 15 by the transfer mechanism 14.

FIGS. 5 (a) and 5 (b) are a plan view and a side view, respectively, showing the mechanism inside the cup 15 in an enlarged manner. A plurality of resin chuck pins 17 for holding the semiconductor substrate 1 on the spin base 16 are attached to the metal spin base 16.
The chuck pin 17 has a protrusion 18 on the top of a circular plane.
The semiconductor substrate 1 can be held on the spin base 16 by supporting the semiconductor substrate 1 by the protrusions 18 included in the plurality of chuck pins 17. The motor 1 is located below the spin base 16.
9, the power of the motor 19 is transmitted to the spin base 16 by the shaft 20 during the spin drying process. Further, the spin base 16 and the shaft 20 are fixed by a screw 21.

FIG. 6 (a) is an enlarged plan view showing the upper surface of the chuck pin 17, and FIG. 6 (b) and FIG.
(C) is a side view showing a different side surface of each chuck pin 17 in an enlarged manner.

As shown in FIG. 6, on the upper surface of the chuck pin 17 excluding the protruding portion 18, an inclined surface 22 that rises along the direction from the center of the supported semiconductor substrate 1 toward the outer periphery.
Are formed. Therefore, it is possible to reduce the area of the contact portion between the back surface of the semiconductor substrate 1 and the chuck pin 17. Further, since the curved surface is in contact with the curved surface of the contact portion between the semiconductor substrate 1 and the protruding portion 18, the shape of the contact portion is a line or a dot. That is, the semiconductor substrate 1 and the chuck pins 17 (projections 18)
Since it is possible to reduce the area of the contact portion with the foreign matter, it is possible to prevent foreign matter particles from adhering to the semiconductor substrate 1 due to the contact with the chuck pin 17. Furthermore, since the area of the contact portion between the semiconductor substrate 1 and the chuck pins 17 (protrusions 18) can be reduced, it is possible to prevent water from staying in the contact portion during the spin drying process of the semiconductor substrate 1. . According to an experiment conducted by the present inventors, the rotation speed of the spin base 16 during the spin drying process was 10 / min.
It has been found that when the rotation is about 00 to 3000 rotations, water can be effectively removed from the contact portion by setting the angle θ between the horizontal line and the inclined surface 22 to about 5 to 20 °. It was also found that the angle θ can be decreased as the rotation speed of the spin base 16 is increased.

A groove (first groove) 23 is formed around the protrusion 18 so as to surround the protrusion 18, and a part of the groove 23 reaches the side surface of the chuck pin 17. Therefore, during the spin drying process, even if water is present in the contact portion between the semiconductor substrate 1 and the chuck pin 17, the water can be discharged from the groove 23. In addition, on the upper surface of the protruding portion 18, a planar rectangular groove portion (the third
A groove portion 24 is formed, and the long side of the groove portion 24 extends toward the center of the semiconductor substrate 1. In the first embodiment, the bottom surface of the groove portion 24 is formed with an inclination that rises along the direction from the center of the semiconductor substrate 1 toward the outer periphery, but the groove portion 24 penetrates the protrusion 18 without providing the inclination. It may have a structure. In the plane, one short side of the groove 24 overlaps the contact portion between the semiconductor substrate 1 and the protrusion 18 (see FIG. 6A). Therefore, during the spin drying process, the upper surface of the semiconductor substrate 1 is not covered. The existing water can be discharged through the groove 24. That is, it is possible to easily remove the water present on the upper surface of the semiconductor substrate 1.

Furthermore, the inclined surface 22 also extends from the vicinity of the plane center of the chuck pin 17 (outer periphery of the plane of the protrusion 18) toward the center of the semiconductor substrate 1 and is continuous with the groove 23. A groove portion) 25 is formed. Therefore, the groove 25 has a shape that is continuous with the groove 24 in a plane. Therefore, in the spin drying process, the water present on the back surface of the semiconductor substrate 1 is discharged to the groove 23 through the groove 25, and the chuck pin 1 is discharged from the groove 23.
7 can be discharged to the outside. That is, it is possible to easily remove the water present on the back surface of the semiconductor substrate 1.

Further, the bottom surface of the groove portion 24 is formed at a position higher than the upper surface of the semiconductor substrate 1. As a result, it is possible to prevent the protrusions 18 from being scraped due to the contact between the groove 24 and the semiconductor substrate 1 and the force when the spin base 16 rotates acts on the contact portion. That is, since the protrusions 18 can be prevented from being scraped, it is possible to prevent the chuck pin 17 from lowering the holding force of the semiconductor substrate 1. Further, since the protrusion 18 can be prevented from being scraped, the life of the chuck pin 17 can be extended.

Here, after the cleaning step, the present inventors found that the diameter remaining in the region 1A (see FIG. 7A) on the back surface of the semiconductor substrate 1 where the chuck pins 17 contact is about 0.24 μm or more. The number of foreign matters (watermarks) was examined by an experiment. As a result, the above-mentioned groove portions 23, 24, 2
When a chuck pin in which No. 5 is not formed is used,
The number of foreign matters was 30, and when the chuck pin 17 in which the groove portions 23, 24, 25 were formed was used, the number of foreign matters was 2. That is, by forming the grooves 23, 24, and 25 in the chuck pin 17 of the first embodiment, it is possible to reduce the number of foreign matters remaining in the region 1A on the back surface of the semiconductor substrate 1 where the chuck pin 17 contacts. It can be confirmed from the experiment. By reducing such foreign matter, it is possible to prevent the foreign matter from short-circuiting the wiring or deteriorating the oxide film after the drying process.

The inclined surface 22 and the groove portion 2 as described above
The 3, 24, 25 may be additionally formed over conventional chuck pins where they are not formed. Thereby,
The manufacturing cost of the chuck pin 18 having the inclined surface 22 and the groove portions 23, 24, 25 can be reduced as compared with the case where the chuck pin 18 is newly manufactured.

Next, as shown in FIG. 8, a WSi _x (tungsten silicide) film is deposited on the polycrystalline silicon film 7. Then, the semiconductor substrate 1 is cleaned by the same brush cleaning as the brush cleaning after the deposition of the polycrystalline silicon film 7. At this time, the single-wafer cleaning apparatus according to the first embodiment described with reference to FIGS. 4 to 6 can be used.

Subsequently, the above WS is formed by, for example, the CVD method.
A silicon oxide film is deposited on the i _x film. Next, after performing a visual inspection of the semiconductor substrate 1 on which the silicon oxide film is deposited, the semiconductor substrate 1 is cleaned by the same brush cleaning as the brush cleaning after the deposition of the polycrystalline silicon film 7. At this time, the single-wafer cleaning apparatus according to the first embodiment described with reference to FIGS. 4 to 6 can be used. Then, the silicon oxide film, the WSi _x film, the polycrystalline silicon film 7 and the gate oxide film 6 are patterned by dry etching using a photoresist film (not shown) patterned by the photolithography technique as a mask. _The gate electrode 31 composed of the _x film and the polycrystalline silicon film 7 can be formed.

Next, P or As (arsenic) is ion-implanted into the p-type well 4 to form an n-type semiconductor region (source, drain) 32, and B is ion-implanted into the n-type well 5 to form p. A type semiconductor region (source, drain) 33 is formed. Through the steps so far, the n-channel type MISFET Qn is formed in the p-type well 4,
A p-channel type MISFET Qp can be formed in the n-type well 5.

Next, as shown in FIG. 9, an n-channel type M
An n-type semiconductor region (source, drain) 3 is formed by forming an interlayer insulating film 34 on the ISFET Qn and the p-channel type MISFET Qp, and then dry etching the interlayer insulating film 34 using a photoresist film as a mask.
A contact hole 35 is formed in the upper part of the 2 and p-type semiconductor regions (source, drain) 33. Then, for example, a titanium nitride film is deposited on the semiconductor substrate 1 including the inside of the contact hole 35 by a sputtering method. Subsequently, the semiconductor substrate 1 is heat-treated, and then the semiconductor substrate 1 is cleaned by the same brush cleaning as the brush cleaning after the deposition of the polycrystalline silicon film 7. At this time, FIGS.
The single-wafer cleaning apparatus according to the first embodiment described with reference to can be used. Then, a W (tungsten) film is deposited on the semiconductor substrate 1 by the CVD method, and the contact hole 35 is filled with the W film. After that, the titanium nitride film and the W film on the insulating film 9 other than the contact hole 35 are removed by, for example, the CMP method to form the plug 36.

Next, a Ti (titanium) film, an Al alloy film and a titanium nitride film are sequentially deposited on the interlayer insulating film 34. Subsequently, after performing a visual inspection of the semiconductor substrate 1 on which the Ti film, the Al alloy film and the titanium nitride film are deposited, the semiconductor substrate 1 is subjected to the same brush cleaning as the brush cleaning after the deposition of the polycrystalline silicon film 7. To wash. At this time,
The single-wafer cleaning apparatus according to the first embodiment described with reference to FIG. 6 can be used. Then, the Ti film, the Al alloy film, and the titanium nitride film are patterned by dry etching using a photoresist film (not shown) patterned by the photolithography technique as a mask. The wiring 37 made of a laminated film of films can be formed.

Next, as shown in FIG. 10, for example, CV
After depositing the silicon oxide film 38 on the semiconductor substrate 1 by the D method, the surface of the silicon oxide film 38 is subjected to CMP (Ch
It is flattened by polishing with the emical Mechanical Polishing method. Then, the semiconductor substrate 1 is cleaned by the same brush cleaning as the brush cleaning after the deposition of the polycrystalline silicon film 7. At this time, the single-wafer cleaning apparatus according to the first embodiment described with reference to FIGS. 4 to 6 can be used.

Next, the silicon oxide film 38 is dry-etched using the photoresist film as a mask,
A contact hole 39 is formed on the wiring 37. Then, the semiconductor substrate 1 is cleaned by the same brush cleaning as the brush cleaning after the deposition of the polycrystalline silicon film 7. At this time, the single-wafer cleaning apparatus according to the first embodiment described with reference to FIGS. 4 to 6 can be used. Then, a Ti (titanium) film, an Al alloy film, and a titanium nitride film are sequentially deposited on the silicon oxide film 38 including the inside of the contact hole 39. Subsequently, after performing a visual inspection of the semiconductor substrate 1 on which the Ti film, the Al alloy film and the titanium nitride film are deposited, the semiconductor substrate 1 is subjected to the same brush cleaning as the brush cleaning after the deposition of the polycrystalline silicon film 7. To wash. At this time, the single-wafer cleaning apparatus according to the first embodiment described with reference to FIGS. 4 to 6 can be used. Then, the Ti film, the Al alloy film, and the titanium nitride film are patterned by dry etching using a photoresist film (not shown) patterned by the photolithography technique as a mask. The wiring 40 made of a laminated film of films is formed, and the CMOS logic LSI of the first embodiment is manufactured. In addition,
By repeating the process shown in FIG. 10, wiring may be formed in multiple layers.

(Second Embodiment) A method for manufacturing a semiconductor integrated circuit device according to the second embodiment is the same as the CMO of the first embodiment.
The method is almost the same as the method for manufacturing the S logic LSI, but the chuck pin 17 (see FIG. 6) is replaced with another chuck pin.

FIG. 11 shows a chuck pin 17A included in the single-wafer cleaning apparatus used in the cleaning step of the semiconductor substrate (see FIG. 1) 1 in the second embodiment. FIG. 18A is a plan view showing the upper surface of the chuck pin 17A.
8B and FIG. 18C are side views showing different side surfaces of the chuck pin.

As shown in FIG. 11, the chuck pin 17A according to the second embodiment is connected to an interlocking jig (first jig) 17C with a fixing jig 17B sandwiched therebetween, such as a screw. By fixing the fixing jig 17B to the spin base 16 by using, the attachment to the spin base 16 is possible. The interlocking jig 17C contains a magnet inside thereof, and is capable of rotating motion interlocking with the operation of a magnet arranged outside. Also, chuck pin 1
7A and the interlocking jig 17C are connected by using, for example, a bearing and a screw, and it is possible to transmit the rotational movement of the interlocking jig 17C to the chuck pin 17A. In the second embodiment, the chuck pin 17A
And the rotation angle θ2 of the rotary motion of the interlocking jig 17C is 60
It can be exemplified that the angle is set to about ° (see FIG. 11A).
By enabling such rotational movement, the holding of the semiconductor substrate 1 by the chuck pins 17A can be made more reliable than in the case of the first embodiment.

The chuck pin 17A is provided with grooves 23, 24, 25 and an inclined surface 22 similarly to the chuck pin 17 (see FIG. 6) shown in the first embodiment. In the second embodiment, when the chuck pin 17A holds the semiconductor substrate 1 by the above rotational movement,
The long sides of the grooves 24 and 25 are made to extend toward the center of the semiconductor substrate 1. Thereby, when the semiconductor substrate 1 is spin-dried, it is possible to easily discharge the water present on the surface of the semiconductor substrate 1 through the grooves 24 and 25 by the centrifugal force. That is, it is possible to easily remove the water present on the surface of the semiconductor substrate 1.

According to the second embodiment as described above, it is possible to obtain the same effect as that of the first embodiment.

The invention made by the present inventor has been specifically described above based on the embodiments of the present invention, but the present invention is not limited to the above-mentioned embodiments, and various modifications can be made without departing from the scope of the invention. It goes without saying that it can be changed.

For example, in the above-mentioned embodiment, the case where the present invention is applied to the semiconductor substrate (semiconductor wafer) having a diameter of about 6 inches has been described, but it is also applied to the semiconductor substrates of other sizes. It is possible.

[0039]

The effects obtained by the typical ones of the inventions disclosed by the present application will be briefly described as follows. (1) In the single-wafer cleaning apparatus, by forming an inclined surface on the upper surface of the chuck pin that supports the semiconductor substrate, the area of the contact portion between the back surface of the semiconductor substrate and the chuck pin can be reduced. It is possible to prevent water from staying. (2) In the single-wafer cleaning apparatus, a groove (first groove) is formed so as to surround the protrusion formed on the upper surface of the chuck pin supporting the semiconductor substrate, and a part of the groove is a side surface of the chuck pin. Therefore, in the spin drying process of the semiconductor substrate, even if water is present at the contact portion between the semiconductor substrate and the chuck pin, the water can be discharged from the groove. (3) In the single-wafer cleaning apparatus, a flat rectangular groove (third groove) is formed on the upper surface of the protrusion formed on the upper surface of the chuck pin that supports the semiconductor substrate, and the long side of the groove is supported. Since it extends toward the center of the semiconductor substrate, the water present on the upper surface of the semiconductor substrate can be drained from the groove portion during the spin drying process of the semiconductor substrate.

[Brief description of drawings]

FIG. 1 is a main-portion cross-sectional view showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 2 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG.

FIG. 3 is an explanatory diagram showing a semiconductor wafer cleaning process during a manufacturing process of the semiconductor integrated circuit device according to the embodiment of the present invention.

FIG. 4 is a perspective view of a cleaning device used in a cleaning process of a semiconductor wafer during a manufacturing process of a semiconductor integrated circuit device according to an embodiment of the present invention.

5A and 5B are a plan view and a side view, respectively, showing a mechanism inside a cup included in the cleaning device shown in FIG.

6 (a) is a plan view showing the upper surface of the chuck pin shown in FIG. 5, and FIGS. 6 (b) and 6 (c) are respectively FIG.
It is a side view which shows the different side surface of the chuck pin shown inside.

FIG. 7A is a plan view illustrating a region on the back surface of the semiconductor substrate where the chuck pins contact, and FIG. 7B is a diagram illustrating the number of foreign matters remaining in the region on the back surface of the semiconductor substrate where the chuck pins contact. It is a figure.

FIG. 8 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG. 2;

9 is a main-portion cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 8;

FIG. 10 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG. 9;

FIG. 11A is a plan view showing an upper surface of a chuck pin included in a cleaning device used in a cleaning process of a semiconductor wafer in a manufacturing process of a semiconductor integrated circuit device according to another embodiment of the present invention; (B) And (c) is a side view which shows a different side of the chuck pin, respectively.

[Explanation of symbols]

1 Semiconductor substrate (semiconductor wafer) 1A area 2 element isolation groove 3 Silicon oxide film 4 p-type well 5 n-type well 6 Gate oxide film 7 Polycrystalline silicon film 11 housing 12 wafer cassette 13 Indexer 14 Transport mechanism 15 cups 16 spin base 17 Chuck pin 17A chuck pin 17B Fixing jig 17C interlocking jig (first jig) 18 Projection 19 motor 20 shaft 21 screw 22 Inclined surface 23 Groove (first groove) 24 Groove (third groove) 25 Groove (second groove) 31 Gate electrode 32 n-type semiconductor region (source, drain) 33 p-type semiconductor region (source, drain) 34 Interlayer insulation film 35 contact holes 36 plugs 37 wiring 38 Silicon oxide film 39 contact holes 40 wiring

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Shuichi Kami             Hitachi, 145 Nakajima, Nanae-cho, Kameda-gun, Hokkaido             Inside North Sea Semiconductor Co., Ltd. F-term (reference) 5F043 AA02 BB27 DD30 EE35 GG10

Claims (5)

[Claims] 1. A method of cleaning a semiconductor substrate using a single-wafer cleaning apparatus, wherein the cleaning apparatus has a plurality of chuck pins for supporting the semiconductor substrate, and the chuck pins have an upper surface (a). A protrusion, a first groove surrounding the protrusion and a second groove extending from the first groove, and (b) an inclined surface on the upper surface excluding the protrusion, the first groove and the second groove. (C) a third groove is formed on the upper surface of the protrusion, a part of the first groove reaches the side surface of the chuck pin, and the second groove and the third groove are the protrusions. A method for manufacturing a semiconductor integrated circuit device, wherein the method extends from the center of the plane toward the center of the semiconductor substrate. 2. A step of cleaning a semiconductor substrate using a single-wafer cleaning apparatus, the cleaning apparatus having a plurality of chuck pins for supporting the semiconductor substrate, wherein the chuck pins are (a) an upper surface. A protrusion, a first groove surrounding the protrusion and a second groove extending from the first groove, and (b) an inclined surface on the upper surface excluding the protrusion, the first groove and the second groove. (C) a third groove is formed on the upper surface of the protrusion, a part of the first groove reaches the side surface of the chuck pin, and the second groove and the third groove are the protrusions. A semiconductor integrated circuit device, wherein the third groove portion is formed at a position which does not contact the semiconductor substrate when the semiconductor substrate is supported. Manufacturing method. 3. A step of cleaning a semiconductor substrate using a single-wafer cleaning apparatus, wherein the cleaning apparatus has a plurality of chuck pins for supporting the semiconductor substrate, and the chuck pins have an upper surface (a). A protrusion, a first groove surrounding the protrusion and a second groove extending from the first groove, and (b) an inclined surface on the upper surface excluding the protrusion, the first groove and the second groove. (C) a third groove is formed on the upper surface of the protrusion, a part of the first groove reaches the side surface of the chuck pin, and the second groove and the third groove are the protrusions. Extending from the center of the plane toward the center of the semiconductor substrate, the third groove portion is formed at a position not contacting the semiconductor substrate when the semiconductor substrate is supported, and the inclination of the inclined surface is about 5 ° to Characterized in that it is 20 ° Method for producing a conductive integrated circuit device. 4. A step of cleaning a semiconductor substrate using a single-wafer cleaning apparatus, the cleaning apparatus having a plurality of chuck pins for supporting the semiconductor substrate, wherein the chuck pins are (a) an upper surface. A protrusion, a first groove surrounding the protrusion and a second groove extending from the first groove, and (b) an inclined surface on the upper surface excluding the protrusion, the first groove and the second groove. And (c) a third groove is formed on the upper surface of the protrusion, and a first jig that is coupled to the chuck pin and that rotates together with the chuck pin is disposed below the chuck pin. A part of the first groove portion reaches a side surface of the chuck pin, and the second groove portion and the third groove portion extend in a direction from a plane center of the protrusion to a center of the semiconductor substrate when the semiconductor substrate is supported. Present A method of manufacturing a semiconductor integrated circuit device, comprising: 5. A step of cleaning a semiconductor substrate using a single-wafer cleaning apparatus, the cleaning apparatus having a plurality of chuck pins for supporting the semiconductor substrate, wherein the chuck pins are (a) an upper surface. A protrusion, a first groove surrounding the protrusion and a second groove extending from the first groove, and (b) an inclined surface on the upper surface excluding the protrusion, the first groove and the second groove. And (c) a third groove is formed on the upper surface of the protrusion, and a first jig that is coupled to the chuck pin and that rotates together with the chuck pin is disposed below the chuck pin. A part of the first groove portion reaches a side surface of the chuck pin, and the second groove portion and the third groove portion extend in a direction from a plane center of the protrusion to a center of the semiconductor substrate when the semiconductor substrate is supported. Exists, The method for manufacturing a semiconductor integrated circuit device, wherein the third groove portion is formed at a position which does not contact the semiconductor substrate when the semiconductor substrate is supported.