JP2003196252A - Multi-processor system and its method of configuration - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a new multi-processor system capable of realizing a much larger data transfer capacity for an interconnection network and its method of configuration. <P>SOLUTION: An interconnection network is configured of a logic circuit based on a pulse logic whose operating time is hardly affected by wiring length. Especially, the interconnection network is configured of a plurality of routers and a line connecting those routers, and the time-division multiple transmission of packets is executed by a rate converting circuit, and an ultra-high speed logic circuit constituted of single magnetic flux quantum (magnetic flux quantized in an ultra-conductive loop including Josephson junction) is adopted in the rate converting circuit so that the interconnection network having a large transfer capacity can be realized. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system suitable for a high-performance computer, a server, etc., and a method of configuring the same.

[0002]

2. Description of the Related Art Research and development of multiprocessor technology for constructing a high-performance computer have been actively carried out. The multiprocessor is a method in which a plurality of processors are arranged in parallel and a program is distributed to each processor or data is divided to perform multiple processing to increase the speed of the entire system.

A typical multiprocessor system configuration in the prior art is shown in FIGS. 5 (a), 5 (b) and 5 (c). In the figure, 1 is an independent processor unit PU, 2
Is an independent memory M, 3 is a local memory L for each PU
M and 4 are mutual coupling networks that couple the processor units PU, or between the processor units PU and the memory M, and switch control the transfer of data and control information.

In FIG. 5A, a plurality of memories M are arranged independently, each processor shares the address space of each memory M, and the processor units PU are connected via the memories M by an interconnection network. It is a method to do. Since the mutual connection network switches the address space of the memory M by a switch, the access time from each processor to the arbitrary memory M is constant regardless of the address. In FIG. 5B, each processor unit PU has a local memory LM.
Is a system in which the local memory LM is connected to the local memory LM attached to another processor unit PU through an interconnection network. FIG. 5C shows
Each processor unit PU has its own memory M, and the processor unit PU is directly connected to another microprocessor via an interconnection network.
In this case, there is no shared memory. The interconnection network may be a router or the like that automatically selects a connection destination according to control information from a connection request source and routes a signal path.

In the case of implementing such a multiprocessor system, conventionally, a plurality of microprocessors and memories are all mounted on one printed board, and an integrated circuit I dedicated to a switch is also mounted on the same printed board.
It has been common to mutually couple the respective microprocessors or between the microprocessor and the memory via C or a router IC so as to exchange data. Further, when the number of installed microprocessors is large, the board is divided into a plurality of pieces and the microprocessors are distributed and mounted.

[0006]

In the prior art, the data transfer capacity of one wiring on the printed circuit board is limited to several hundred Mbps due to the characteristics of the printed circuit board. on the other hand,
The standard microprocessor operating frequency is already 1
The frequency exceeds GHz to reach 2-3 GHz, and the difference between the signal processing capacity of the microprocessor and the data transfer capacity of the board is large. In particular, in a multiprocessor system in which a plurality of microprocessors are connected to operate in parallel, the mutual connection network between the microprocessors is constantly crowded, causing a delay in data transfer, which is a major factor limiting the improvement in system processing performance. Has become. As described above, the lack of data transfer capacity of the interconnection network in the multiprocessor system is expected to become a serious problem in the future.

Further, in the printed circuit board, the charging / discharging time of the wiring on the circuit board becomes an important factor that limits the data transfer capability. It is conceivable that the characteristics of the printed circuit board will be improved and the data transfer capability will be improved in the future, but even in that case, it is essentially difficult to expect a significant improvement. That is,
The interfaces of the conventional microprocessor, memory, and switch of the interconnection network follow the level logic for detecting 1,0 change of the signal with the threshold value set to the intermediate level. For example, as shown in FIG. 6, when data is transferred from a microprocessor, the output of the microprocessor and the input of the switch or memory of the interconnection network connected to the microprocessor must have the same potential in order for the data transfer to be performed normally. There is. However, in order for the potential on the output side and the potential on the input side to become the same potential by this level logic,
The wiring in the meantime needs to be charged / discharged, and the charging / discharging time is proportional to the length of the wiring. Therefore, for example, 1GH
There is a problem that the distance for transmitting the z signal is limited to about several cm.

In view of the above circumstances, the present invention is intended to solve the problems of the prior art, and provides a new multiprocessor system capable of realizing a larger data transfer capacity for an interconnection network and a method of configuring the same. To do.

[0009]

In order to solve the above problems, the present invention employs a logic circuit according to pulse logic in an interconnection network of a multiprocessor system. As shown in FIG. 1A, the pulse logic responds to the presence or absence of an input pulse, and the influence of the charge / discharge time of the wiring can be made significantly smaller than that of the level logic. The present invention is particularly characterized in that an ultra-high speed single magnetic flux quantum logic circuit (SFQ circuit) is used as the pulse logic circuit. Specifically, by forming an interconnected network composed of a single magnetic flux quantum logic circuit on a substrate on which multiple microprocessors or memories of a multiprocessor system are mounted, an interconnected network with a large transfer capacity is provided. A multiprocessor configuration method is provided.

Single flux quantum logic circuits are described in the reference [Yoshida
Jiro: Logic circuit technology using single-flux quantum devices, applications
Science Vol. 67, No. 4, 1998 pp.410-416]
Has been. FIG. 1B shows an example of a single magnetic flux quantum logic circuit and
Then, the RS flip-flop circuit is shown. Circuit shown
Is the two Josephson junction J₁, J₂With superconductivity
Group. First the circulating current in the closed loop of the circuit
In the reset state where no
Go J₁When an input pulse is applied to the S terminal on the₁Flow through
When the current exceeds the critical current value, J₁Is superconducting
Switch, J ₁Voltage is generated and the closed loop is rotated clockwise
Current flows. Input pulse of S terminal disappeared, J
₁If the current flowing through₁Returns to the superconducting state
The current flowing through the closed loop becomes a permanent current and
Small unit Φ₀The quantized magnetic flux is stored in. This state
Becomes the set state of the flip-flop. Where Jo
Sefson junction J₂When a pulse is input to the R terminal on the
₂Switches from the superconducting state, J₂To the voltage generated in
The current flows more counterclockwise and the previous clockwise current
Cancel and return to reset state. And J at this time₂
The voltage change is output from the Out terminal.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Preferred embodiments of the present invention will be described below.

FIG. 2 shows a mounting configuration example of the multiprocessor system according to the present invention. In the figure, 10 is a substrate,
Reference numeral 11 denotes a total of eight processor modules arranged on the substrate 10, each of which is a processor unit PU.
And memory M. Reference numeral 12 is a router of an interconnection network composed of a single magnetic flux quantum logic circuit, 13 is a Josephson transmission line connecting the routers, and 14 is a Josephson transmission line connecting the processor module and the router.
The router 12 is a data transfer means that distributes data to destinations specified by a packet format between networks. In the illustrated example, one router is provided for each of two processor modules, and a total of four routers are provided. They are connected in a ring shape to form an interconnection network. However, many variations are possible in the configuration of such an interconnection network.

In FIG. 2, a processor unit P of a plurality of processor modules 11 arranged on a substrate 10
The U and the memory M exchange data with the processor unit PU and the memory M of an arbitrary processor module via one or two routers 12 of the mutual connection network, and have a function as one high-performance computer as a whole. Demonstrate. In addition,
The form of the multiprocessor system shown is merely exemplary, and may take any other form as shown in FIGS. 5 (a), (b), (c), and may be a processor module. The number of may be arbitrary.

A single-flux-quantum logic circuit which constitutes a router performs an operation by correlating the presence or absence of l quantized magnetic fluxes (called flux quanta) in a superconducting loop including Josephson junctions with binary signals. To do. Since a single magnetic flux quantum logic circuit uses a kind of electromagnetic wave called magnetic flux as a signal, the Josephson transmission line used as a wiring has a bandwidth of 100 Gbps per line and a logic gate of 100.
It can operate above GHz. According to the present invention, the single-flux-quantum logic circuit having such characteristics is manufactured on the substrate as an interconnection network in the various multiprocessor configurations described above, and enables data transmission at an extremely high speed.

A major problem of the interconnection network in the multiprocessor is packet transparency. Eg 2
If two processors try to access one memory address at the same time, a collision (memory conflict) occurs and one packet is usually dropped, thus reducing the transparency. This is a major factor that hinders the performance improvement of the entire multiprocessor. In the conventional interconnection network, the transmittance reaches a peak at around 65%. In the interface with the outside in the future microprocessor, the bandwidth in one signal path may be expanded to about 3 GHz, but this bandwidth is much larger than that of the single flux quantum logic circuit. It is very low. Therefore, a signal input or output at about 3 GHz is packetized, and parallel input packets of a plurality of channels are
By using a rate conversion circuit composed of a single magnetic flux quantum logic circuit, by gradually shifting the packets of each channel by the method of time division data communication and time division multiplexing (multiplexing) into one time series signal, high speed is achieved. It is possible to simultaneously perform a plurality of data exchanges with different destinations. A packet signal transmitted by time division multiplexing is distributed (demultiplexing) at the transmission destination by a rate conversion circuit that operates in reverse of time division multiplexing, and packets of multiple channels are spatially separated and delivered to the destination. To do. By using such a rate conversion circuit and connecting the routers by the Josephson line 12, the signal transmission time between the plurality of processor modules can be significantly shortened.

FIG. 3 is an explanatory diagram of the rate conversion circuit.
The frequency of the signal output from the processor unit PU remains at around several GHz, but the single-flux quantum logic circuit has a bandwidth of several tens GHz. Therefore, as shown in the figure, the inputs of the packets A, B, C, and D that come in parallel at a low speed are rearranged into a high-speed time series while shifting the time by the time division rate conversion circuit 15 by the single magnetic flux quantum logic circuit. Even if it does, it can be sufficiently processed due to the high speed of the single flux quantum logic circuit. By increasing the packet rate, the packet discard rate can be reduced, and as a result, the packet transparency rate can be significantly improved.

FIG. 4 shows an example of where the rate conversion circuit is provided. The figure (a) is an example in which the rate conversion circuit is provided on the processor unit PU or the memory M side and the single flux quantum logic circuit is not used. The figure (b) shows the rate conversion circuit by the single flux quantum logic circuit. This is an example of having the mutual connection network side.

In the example of FIG. 4A, reference numeral 20 is a processor module as a unit constituting a multiprocessor. Reference numeral 21 denotes a processor unit PU or memory M in the module, which is an access source or an access destination of data in the system. Reference numeral 22 is a rate conversion circuit incorporated in the module, which operates based on the same level logic as that of the processor unit PU or the memory M, and performs speed conversion of data. 23 is a single magnetic flux quantum logic circuit S
It is an SFQ transfer circuit on the side of the mutual coupling network composed of FQ,
Performs router operation between the network and the module. Reference numeral 24 is an SFQ network similarly composed of a single magnetic flux quantum logic circuit SFQ, and is composed of an SFQ line connecting modules. In the case of this example, the bandwidth of the output of the processor unit PU or the memory M is 3 GHz.
Since the rate conversion circuit 22 operates based on the level logic, it is not possible to increase the degree of time division multiplexing as in the case of using the single flux quantum logic circuit SFQ.
For this reason, if the amount of information per unit time is increased by a method such as multileveling a binary input signal, the communication capacity that can be output should be increased to the communication capacity of a single magnetic flux quantum logic circuit. Is possible. However, since it is extremely difficult to process a multilevel signal with a switch or a router, the multilevel signal output from the rate conversion circuit 22 is converted into a binary signal again on the SFQ transfer circuit 23 side,
It is necessary to process as time-series data of the form shown in FIG. This method can also be an effective means of relaxing the limit (pin neck) due to the number of pins of the interface, which is one of the major problems of microprocessors.

On the other hand, FIG. 4B shows that the function of the rate conversion circuit is placed in the router of the interconnection network, and the SFQ rate conversion / transfer circuit is combined with the function of the SFQ transfer circuit 23 of FIG. 4A. It is configured as 25. In the case of this example, although the problem of the pin neck cannot be solved, there is an advantage that it is not necessary to make a large change to the interface unit of the microprocessor. However, the signal is a router that uses a single-flux-quantum logic circuit on the side of the mutual coupling network, and requires rate conversion to be multiplexed with time-series data.

Furthermore, another advantage of performing signal transmission using a single-flux-quantum logic circuit is that it has a self-healing action of the propagation waveform, that is, the waveform does not collapse during the propagation of the signal. This means that even if the substrate is a curved substrate or a flexible substrate where accurate information transmission cannot be performed due to dissipation of energy such as radiation, a single flux quantum logic circuit can send a signal without distortion. Therefore, by using a single magnetic flux quantum logic circuit as an interconnection network on such a substrate, it becomes possible to mount the microprocessor in higher density or more flexibly. This leads to improved performance of multiprocessor systems.

[0021]

As described above, according to the present invention,
It is possible to significantly improve the transfer capacity of the interconnection network in the multiprocessor. As a result, the multiprocessor can obtain faster signal processing or higher computing capacity, and can further improve the performance of the computer.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a schematic diagram showing an example of a mounting configuration of a multiprocessor system according to the present invention.

FIG. 3 is an explanatory diagram of a rate conversion circuit.

FIG. 4 is an explanatory diagram showing an example of inserting a rate conversion circuit.

FIG. 5 is a schematic diagram showing an example of a typical multiprocessor system configuration in a conventional technique.

FIG. 6 is an explanatory diagram of level logic of a conventional logic circuit.

[Explanation of symbols]

1: Processor unit PU 2: Memory M 3: Local memory LM 4: Mutual coupling network 10: Substrate 11: Processor module 12: Router of mutual coupling network composed of single flux quantum logic circuit 13: Joseph coupling between routers Son transmission line 14: Josephson transmission line 15 for coupling between the processor module and the router: Rate conversion circuit

Claims (12)

[Claims] 1. A multiprocessor system comprising a plurality of modules equipped with a microprocessor and a memory, wherein the modules are interconnected by an interconnected network, wherein the interconnected network is constructed using pulse logic. Characteristic multiprocessor system. 2. The multiprocessor system according to claim 1, wherein the mutual coupling network is configured by using a single magnetic flux quantum logic circuit. 3. The interconnection network comprises a router provided for each module, a line connecting between the router and the microprocessor and memory in the module, and a line connecting the routers. The multiprocessor system according to claim 1 or 2. 4. The multiprocessor system according to claim 2, wherein the interconnection network includes a rate conversion circuit. 5. The multiprocessor system according to claim 4, wherein the rate conversion circuit has a function of time-division multiplexing packets input in parallel and converting the packets into a high-speed time series signal. 6. The interconnection network comprises a line connecting between a microprocessor and a memory in a module and a router,
The multiprocessor system according to claim 3, wherein the line connecting the routers is a Josephson line. 7. A multiprocessor system comprising a plurality of modules equipped with a microprocessor and a memory, wherein the modules are interconnected using a logic circuit according to pulse logic. 8. The logic circuit according to the pulse logic is constituted by a single flux quantum logic circuit.
The multiprocessor configuration method described in. 9. The modules are interconnected by a router provided for each module, a line connecting between the router and the microprocessor and memory in the module, and a line connecting the routers. The multiprocessor configuration method according to claim 7 or 8. 10. The multiprocessor configuration method according to claim 7, wherein rate conversion is performed when mutual coupling is performed. 11. The multiprocessor configuration method according to claim 10, wherein the rate conversion is performed by time-division multiplexing packets input in parallel and converting the packets into a high-speed time series signal. 12. The method for constructing a multiprocessor according to claim 9, wherein a line connecting between the router and the microprocessor and memory in the module and a line connecting between the routers are composed of Josephson lines. .