JP2003178919A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which the inductance of an inductor element can be made changeable and which can obtain desired characteristics, and to provide a method of manufacturing the device. <P>SOLUTION: This semiconductor device is constituted by connecting first wiring 12 to one end of the wiring 20 of the inductor element 30 formed on a substrate through a dielectric film, and second wiring 12a to a midpoint of the wiring 20 through another dielectric film. At the time of manufacturing this semiconductor device having the inductor element 30 formed on the substrate, a first conductive film, a dielectric film, and a second conductive film are formed on an insulating film and lower-layer wiring 10, 12 and 12a is formed by patterning the first conductive film. Then upper-layer wiring 20 and 23 is formed by patterning a third conductive film so that the wiring 20 and 23 may be connected to the lower-layer wiring 10, 12 and 12a directly or through the second conductive film and dielectric film and connected to the lower-layer wiring 10, 12 and 12a through the second conductive film and dielectric film. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having an inductor element formed on a substrate and a method of manufacturing the same.

[0002]

2. Description of the Related Art When an inductor is provided in a semiconductor device,
Usually, the inductor is externally connected to the integrated circuit, and then the inductor is connected by wire bonding or the like.

However, as semiconductor devices have been driven at high frequencies, the inductance of wires has become non-negligible.

Therefore, in recent years, a method of forming an inductor, which is a passive element, on the same silicon substrate as the integrated circuit has been performed for the purpose of improving the performance of the integrated circuit and supporting high frequencies.

When an inductor is formed on a silicon substrate, it generally has the structure shown in FIG. FIG. 8A shows a plan view and FIG. 8B shows a sectional view. The inductor element 50 is configured by the spiral wiring 51 made of a low resistance material such as Al. The inner end of the spiral wiring 51 is connected to the lead wiring 52 in the lower layer via the contact portion 53. The other end of the lead wire 52 extends to the outside of the spiral wire 51 and is connected to another wire (not shown) or the like via a contact portion 54. The spiral wiring 51 is formed on an insulating layer 56 such as a field oxide film or an interlayer insulating film formed on the silicon substrate 55 in order to reduce the parasitic capacitance with the silicon substrate 55.

[0006]

By the way, the value of the inductance of the inductor element is generally determined by the size of the inductor element (that is, the diameter of the spiral) and the number of turns. However, considering the entire circuit, the wiring connected to the inductor element also has an inductance,
The actual inductance is the sum of the inductance of these inductor elements and the inductance of the wiring.

Therefore, in order to obtain a desired inductance in an actual circuit, some circuits in which the wiring connected to the inductor element and the peripheral wiring are changed are actually manufactured,
It becomes necessary to find a combination that has the desired characteristics. Of course, it is possible to estimate to some extent a combination that can obtain a desired characteristic by a prior circuit simulation including wiring, but as the number of elements of the integrated circuit increases, the calculation time becomes enormous.

Further, for example, when manufacturing an LC resonator, resonance is made at a target frequency by a combination of values of inductance and capacitance. However,
In the actual semiconductor manufacturing process, the resonance frequency may deviate from the target value due to variations in characteristics of the element due to variations in manufacturing. In order to avoid this, a pn junction is usually used as a capacitor, and a variable capacitor whose capacitance can be changed by a reverse bias applied is used.

On the other hand, it is difficult for the inductor to variably change like a capacitor. Therefore, in order to design a circuit in consideration of variations in element characteristics in the semiconductor manufacturing process, it is necessary to use a capacitor having a wide variable range so as to be able to correct variations in the circuit itself and variations in the inductance.

Then, in order to form a capacitor having a wide variable range with a pn junction, the concentration difference between p and n is increased. However, in this case, the parasitic resistance on the low concentration side increases, so that the characteristics of the variable capacitor deteriorate in terms of frequency characteristics and the like.

As described above, since it is difficult to form a variable inductor, it is necessary to empirically form a circuit by producing some combinations in which wirings in a circuit pattern are changed. Therefore, there is a great disadvantage in efficiently developing an integrated circuit in a short period of time. In addition, since variations in characteristics must be covered by other elements, the original ability of those elements will be reduced, and there will be many disadvantages in making high-performance integrated circuits. It was

In order to solve the above-mentioned problems, the present invention provides a semiconductor device which can change the inductance of an inductor element, obtains desired characteristics and has high performance, and a manufacturing method thereof. It is a thing.

[0013]

The semiconductor device of the present invention comprises:
At least an inductor element is formed on a substrate, the first wiring is connected to one end of the wiring of the inductor element through a dielectric film, and the intermediate portion of the wiring of the inductor element is connected via a dielectric film. The second wiring is connected.

The method of manufacturing a semiconductor device according to the present invention comprises the steps of forming a first conductive film on an insulating film when manufacturing a semiconductor device in which an inductor element is formed on the insulating film on a substrate, and A step of forming a dielectric film on the first conductive film, a step of forming a second conductive film on the dielectric film, a step of patterning the second conductive film and the dielectric film thereunder, respectively. A step of patterning the conductive film to form a lower wiring, and forming an upper wiring so as to be directly connected to the lower wiring by the third conductive film or via the second conductive film and the dielectric film thereunder. A step of forming an inductor element wiring by wiring of either one of the upper layer wiring and the lower layer wiring, and connecting the inductor element wiring to one end of the inductor element wiring by the other layer wiring. In the middle of the wiring of 1 and the wiring of the inductor element Forming a second wiring connected,
The first wiring and the second wiring are connected to the wiring of the inductor element through the second conductive film and the dielectric film thereunder.

According to the above-described structure of the semiconductor device of the present invention, the first wiring is formed on one end of the inductor element via the dielectric film.
Of the first wiring or the second wiring and the wiring of the inductor element by connecting the second wiring through the dielectric film to a portion in the middle of the wiring of the inductor element. Thus, the dielectric film can be destroyed to selectively obtain inductor elements having different numbers of turns. This makes it possible to form an inductor element having variable inductance.

According to the above-described method of manufacturing a semiconductor device of the present invention, the wiring of the inductor element is formed by the wiring of one of the upper layer wiring and the lower layer wiring, and the inductor of the other layer wiring is formed. A first wire connected to one end of the wire of the element and a second wire connected in the middle of the wire of the inductor element are formed, and the first wire and the second wire and the wire of the inductor element are connected to each other. By connecting via the second conductive film and the dielectric film thereunder, the dielectric film between the first wiring or the second wiring and the wiring of the inductor element is destroyed, and an inductor having a different number of turns selectively. It is possible to manufacture a structure from which an element can be obtained. This allows
It is possible to form an inductor element having variable inductance.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention is a semiconductor device in which an inductor element is formed on at least a substrate, and the first wiring is connected to one end of the wiring of the inductor element via a dielectric film. The second wiring is connected to a part in the middle of the wiring through a dielectric film.

According to the present invention, in the above semiconductor device,
As the second wiring, a plurality of wirings connected to different portions in the wiring of the inductor element are provided.

According to the present invention, in the above semiconductor device,
The wiring of the inductor element is composed of a wiring layer higher than a wiring layer forming the first wiring and the second wiring, and is opposite to the ends of the first wiring and the second wiring connected to the wiring of the inductor element. A third wiring is connected to the end via a dielectric film.

According to the present invention, in the above semiconductor device,
The wiring of the inductor element and the third wiring are connected to the first wiring and the second wiring through the dielectric film and the conductive film thereabove.

Further, the present invention provides the above semiconductor device,
The wiring of the inductor element has a spiral shape.

According to the present invention, in the above semiconductor device,
A capacitive element is formed on a substrate, and the dielectric film of the capacitive element is formed of the same film as the above dielectric film.

The present invention also provides the above semiconductor device,
Either the first wiring or the second wiring is electrically connected to the wiring of the inductor element by breaking the dielectric film.

The present invention is a method for manufacturing a semiconductor device in which an inductor element is formed on an insulating film on a substrate,
A step of forming a first conductive film on the insulating film, a step of forming a dielectric film on the first conductive film, a step of forming a second conductive film on the dielectric film, and a second conductive film And a step of patterning the underlying dielectric film, a step of patterning the first conductive film to form a lower layer wiring, and a third conductive film directly on the lower layer wiring or the second conductive film and the same. A step of forming an upper layer wiring so as to be connected via a lower dielectric film, wherein the wiring of one of the upper layer wiring and the lower layer wiring forms the wiring of the inductor element, and the other The first wiring connected to one end of the wiring of the inductor element and the second wiring connected in the middle of the wiring of the inductor element by the wiring of the layer The wiring of the device, the second conductive film and the dielectric film thereunder It is a manufacturing method of a semiconductor device to be connected through.

Further, according to the present invention, in the method for manufacturing a semiconductor device described above, a plurality of wirings connected to different portions in the middle of the wiring of the inductor element are formed as the second wirings.

Further, according to the present invention, in the method of manufacturing a semiconductor device, the wiring of the inductor element is formed by the wiring of the upper layer, the first wiring and the second wiring are formed by the wiring of the lower layer, and the first wiring and A third wiring is formed by the upper wiring so as to be connected to the end of the second wiring opposite to the end connected to the inductor element via the dielectric film and the second conductive film.

Further, according to the present invention, in the method of manufacturing a semiconductor device described above, the wiring of the inductor element has a spiral shape.

According to the present invention, in the method of manufacturing a semiconductor device described above, a capacitive element is formed on a substrate, and a dielectric film of the capacitive element is formed simultaneously with the dielectric film.

According to the present invention, in the method of manufacturing a semiconductor device described above, the dielectric film is destroyed with respect to either the first wiring or the second wiring after the step of forming the upper wiring. A step of electrically connecting to the wiring of the inductor element is performed.

FIG. 1 shows a schematic configuration diagram (plan view) of an inductor element as an embodiment of the present invention. 2A shows a sectional view taken along line XX of FIG. 1, FIG. 2B shows a sectional view taken along line YY, and FIG. 2C shows a sectional view taken along line ZZ. The inductor element 30 is composed of the spiral wiring 20 made of a wiring material having a low resistance such as Al. This spiral wiring 20 is shown in FIG. 2A.
~ As shown in FIG. 2C, the insulating layer 2 on the silicon substrate 1
It is formed on 3,13.

Then, in the present embodiment, FIGS.
Also, as shown in FIG. 2B, the outer end of the spiral wiring 20 is connected to the first wiring 12 via the first capacitance (capacitor) C1 formed by the electrode 8 and the thin dielectric film 5. . In addition, as shown in FIGS. 1 and 2C,
As it branches in the middle of the spiral wiring 20,
It is also connected to the second wiring 12a via the third capacitor C3 formed via the thin dielectric film 5. Further, as shown in FIGS. 1, 2B, and 2C, the other ends of the first and second wirings 12 and 12a have second capacitors C2 and C2 formed by the electrodes 9 and 9a and the thin dielectric film 5, respectively. Each is connected to the third wiring 23 via the fourth capacitor C4.

On the other hand, the inner end of the spiral wiring 20 is connected to one end of the lead wiring 10 via the contact portion 14. The other end of the lead wiring 10 extends to the outside of the spiral wiring 20 and is connected to another wiring (not shown) or the like via the contact portion 15.

The first wiring 12, the second wiring 12a, and the lead wiring 10 are formed on the insulating layer 2 on the silicon substrate 1.
3 is formed on the first wiring layer. In addition, the spiral wiring 20 and the third wiring 23
Is composed of a second wiring layer formed on the interlayer insulating film 13 covering the first wiring layer. By thus forming the spiral wiring 20 of the inductor element by the second wiring layer, the distance between the substrate 1 and the spiral wiring 20 can be increased to reduce the parasitic capacitance.

The electrodes 8 and 9 are provided in order to stably form the thin dielectric film 5 forming the capacitors C1 and C2 with a predetermined film thickness. The dielectric film 5 is formed by using the electrodes 8 and 9 as stoppers when forming a contact hole in the interlayer insulating film 13 for connecting to the upper wirings 20 and 23.
Can be prevented from being scraped.

In the state shown in FIGS. 1 and 2, the spiral wiring 20 is grounded and the first wiring 12 is biased, so that the gap between the electrode 8 and the first wiring 12 is passed through the dielectric film 5. At that moment, a large current may flow, and Al or the like forming the wiring may be melted at a high temperature, causing dielectric breakdown of the first capacitor C1. This makes it possible to form a state in which the spiral wiring 20 and the first wiring 12 are locally connected.

In addition, by the same method, the second capacitance C
Dielectric breakdown of 2 can also form a state in which the third wiring 23 and the first wiring 12 are locally connected. As a result, an inductor element 30A (see FIG. 3A) including the third wiring 23, the electrode 9, the first wiring 12, the electrode 8, the spiral wiring 20, the contact portion 14, and the lead wiring 10 is formed. .

On the other hand, similarly to this, if the third capacitance C3 and the fourth capacitance C4 are dielectrically broken down, the third wiring 23-the electrode 9a-the second wiring 12a-the electrode 8a-the spiral wiring 20. Part-contact portion 14-lead wiring 10
Inductor element 30B configured by (see FIG. 3B)
Is formed. In this case, since the wiring length of the spiral wiring 20 is shorter than that of the inductor 30A, the inductance can be reduced.

In an actual integrated circuit, as shown in FIG.
Wirings 25 and 26 for bias application are connected to the first wiring 12 and the second wiring 12a. Further, the other ends of the wirings 25 and 26 for applying bias are connected to a bias applying circuit.

When applying the bias, the spiral wire 20 side of the inductor element 30 is grounded,
The bias applying circuit sets which of the bias applying wirings 25 or 26 the bias is applied to, and the connected wiring, that is, the first wiring 12 or the second wiring is connected through the bias applying wiring 25 or 26. A bias is applied to 12a. As a result, the dielectric film 5 at one end of the biased wiring 12 or 12a on the side of the spiral wiring 20 is destroyed, and the spiral wiring 20 and the first wiring 12 or the second wiring 12 of the inductor element is destroyed.
a is electrically connected. Similarly, the third wiring 23 side is grounded, and the bias is applied again to the same wiring 12 or 12a to which the bias has been applied. As a result, the dielectric film 5 at the other end of the wiring 12 or 12a to which the bias is applied on the side of the spiral wiring 20 is destroyed, and the first wiring 1
2 or the second wiring 12a and the third wiring 23 are electrically connected.

Here, the structure of the bias applying circuit for switching the wiring 12 or 12a for applying the bias can be easily formed by using a normal logic circuit.
It does not require a special circuit.

When considered at a high frequency, the capacitance also becomes one of the resistances. Therefore, for example, in the structure in which the first wiring 12 side in FIG. 3A is connected, the spiral wiring 20-dielectric film 5-second wiring 12a. It also becomes necessary to consider the current that flows in the branched portion. However, if the capacitance formed in this portion is set to about several hundred fF to several fF, a resistance of several hundred to several tens kΩ even at 10 GHz, so a value that can be ignored compared to the wiring resistance (usually several Ω or less) Therefore, it is not necessary to consider the branch of the current due to this.

From the above, depending on where the second wiring 12a is arranged in the spiral wiring 20 of the inductor element 30, an arbitrary inductance can be produced for the inductor element 30 having the same size.

Further, a plurality of wirings branched from the middle of the inductor element 30 may be provided not only in the second wiring 12a but also from different portions of the inductor element 30. By thus providing a plurality of wirings in the middle of the spiral wiring 20 of the inductor element 30, it becomes possible to discretely change the inductance of the inductor element 30.

According to the present embodiment described above, the first wiring 12 has the capacitor element 30 via the dielectric film 5 and the electrode 8.
Is connected to one end of the spiral wiring 20, and the second wiring 12a is connected to an intermediate portion of the spiral wiring 20 of the capacitor element 30 via the dielectric film 5 and the electrode 8a. Wiring 12 or second wiring 12a
It becomes possible to locally connect the first wiring 12 or the second wiring 12a to the spiral wiring 20 by destroying the dielectric film 5 between either one of them and the spiral wiring 20. .

As a result, it is possible to form the inductor element 30A with a large number of turns or the inductor element 30B with a small number of turns, and it is possible to selectively obtain inductor elements with different numbers of turns, so that the inductance can be varied. Can be configured. Therefore, for example, when manufacturing an LC resonator,
It is possible to realize a desired resonance frequency without degrading the characteristics of the variable capacitor.

Further, by providing a plurality of second wirings 12a branched from the middle of the inductor element 30 respectively from different portions of the inductor element 30, the inductance of the inductor element 30 is discretely changed. Will be possible. Therefore, even if there are variations in the characteristics in the semiconductor forming process, the inductance can be trimmed after the semiconductor manufacturing process is completed. As a result, since the variation is covered by another element, the characteristics of the other element do not deteriorate, and a high-performance integrated circuit can be manufactured.

Further, since the inductance can be easily changed by the inductor element 30 having a variable inductance, it is not necessary to actually produce a combination of a large number of circuits to search for a combination having a desired characteristic. This makes it possible to efficiently develop and design an integrated circuit in a short period of time.

The spiral wiring 20 and the electrodes 8-
Dielectric film 5-MIM (metal-insulator-) of the first wiring 12 and the like
When the metal) structure is also used as a normal capacitor (capacitance element) to form a capacitance element of MIM structure, a high-performance MIM capacitance element with low parasitic resistance / parasitic capacitance is used as the capacitor element 30 of the present embodiment. It is also possible to mix-mount them on the same silicon substrate 1. In this case, the dielectric film of the MIM capacitance element is provided with the spiral wiring 20 and the first and second wirings 1.
It is composed of the same dielectric film as the dielectric film 5 between 2 and 12a. By constructing the capacitive element having the MIM structure as described above, a high-performance integrated circuit can be manufactured, and the effect is particularly great in a circuit for high frequency use.

Subsequently, as one embodiment of the method for manufacturing a semiconductor device of the present invention, an inductor element having the same structure as shown in FIGS. 1 and 2 and a capacitive element having an MIM structure are mixedly mounted on the same silicon substrate. The manufacturing process of the semiconductor device having the above structure will be described below.

First, as shown in FIG. 4A, the inductor element forming region 31 and the MIM structure capacitor forming region 3 are formed.
Separate from 2. As a semiconductor substrate, for example, a concentration of 1 × 1
A field oxide film 2 having a thickness of about 200 to 1500 nm is formed on the p-type silicon substrate 1 having a thickness of about 0 ¹⁵ cm ^-3 by the LOCOS oxidation method which is usually performed. After that, the interlayer insulating film 3 is formed in a manner similar to the existing semiconductor process.

Next, a conductive film 4 made of a low resistance material such as Al is formed on the entire surface to a film thickness of about 1 μm. Then T
10 to 10 by plasma CVD method using EOS
A thin dielectric film 5 of about 0 nm, for example, a silicon oxide film is formed on the entire surface. This dielectric film 5 will also become a dielectric film of a capacitive element having an MIM structure later.

As the dielectric film 5, a silicon nitride film may be formed instead of the silicon oxide film. The film thickness of the dielectric film 5 is preferably in the range of 5 to 100 nm.

Then, a conductive film 6 of TiN or the like is formed on the entire surface by 20.
The film is formed with a film thickness of about 0 nm (see FIG. 4B above).

Next, the conductive film 6 is patterned by the RIE (reactive ion etching) method or the like using a patterning process with a photoresist. This makes MI
The upper electrode 7 of the capacitance element is formed in the formation region 32 of the capacitance element having the M structure, and the electrodes 8 and 9 for the inductor element are formed in the formation region 31 of the inductor element. The etching at this time is performed under the condition that the dielectric film 5 serves as a stopper. Then, the dielectric film 5 is etched under the condition that the conductive film 4 is used as a stopper to pattern the dielectric film 5 under the upper electrode 7 and the electrodes 8 and 9 into the same pattern as the electrodes 7, 8 and 9. To do. The electrode 8 is formed immediately below the outer end of the spiral wire 20 of the inductor element (see FIG. 4C above).

Next, the conductive film 4 is patterned by the RIE (reactive ion etching) method or the like using a patterning process with a photoresist. As a result, in the inductor element formation region 31, the lead-out wiring 10 and the first wiring 12 for taking out from the inside of the inductor element are formed, and in the capacitive element formation region 32 of the MIM structure, The lower electrode 11 is formed. Note that one end of the first wiring 12 is formed directly below the electrode 8 via the dielectric film 5, and the other end is formed directly below the electrode 9 via the dielectric film 5 (see FIG. 5D above).

FIG. 6 shows a plan view from above in this state. Electrodes 8a formed in the same manner as the electrodes 8 and 9,
9a, and there is a second wiring 12a formed in the same manner as the first wiring 12. The electrode 8 is arranged on one end side of the first wiring 12 and the electrode 9 is arranged on the other end side thereof. Similarly, the electrode 8a is arranged on one end side of the second wiring 12a, and the electrode 9a is arranged on the other end side thereof.

Next, the interlayer insulating film 13 is formed on the entire surface by the plasma CVD method using TEOS or the like. continue,
After performing the patterning process using the photoresist,
By processing the interlayer insulating film 13 by the RIE method or the like, the contact holes 14 and 15 are formed on the lead wiring 10 of the capacitor element, and the contact hole 16 is formed on the upper electrode 7 of the capacitor element having the MIM structure. A contact hole 17 is formed on the lower electrode 11 of the capacitive element having the structure.
Is formed, a contact hole 18 is formed on the electrode 8 on the right end side of the first wiring 12, and a contact hole 19 is formed on the electrode 9 on the left end side of the first wiring 12 (see FIG. 5E.
reference).

Then, a conductive film such as Al is formed on the entire surface,
RI using patterning process using photoresist
This conductive film is patterned by the E method or the like. As a result, the spiral wiring 20 of the inductor element and M
An upper electrode lead-out electrode 21 and a lower electrode lead-out electrode 22 of the IM structure capacitor and a third wire 23 for taking out the first wire 12 are formed.

Here, the electrode 8 on the right end side of the first wiring 12
Is the spiral wiring 2 formed by the contact hole 18.
It is connected to the outer edge of 0. The electrode 9 on the left end side of the first wiring 12 is connected to the third wiring 23 through the contact hole 19. The left end of the lead wire 10 of the inductor element is connected to the inner end of the spiral wire 20. The right end of the lead wire 10 of the inductor element is connected to the wire 24 that is connected to other elements and the like. In the capacitive element having the MIM structure, the upper electrode lead electrode 21 is connected to the upper electrode 7, and the lower electrode lead electrode 22 is connected to the lower electrode 11 (see FIG. 5F.
reference).

In FIG. 5F, in order to simplify the illustration,
The number of turns of the spiral wiring 20 is smaller than that in FIG.

FIG. 7 shows a plan view from above in this state. In FIG. 7, the number of turns of the spiral wiring 20 is the same as that in FIG. As shown in FIG. 7, contact holes 18a and 19a formed in the same manner as the contact holes 18 and 19 are on the second wiring 12a.
As a result, the spiral wiring 20 of the inductor element is formed.
The middle part of the electrode is the electrode 8a and the dielectric film 5 (see FIG. 5F).
Is connected to one end of the second wiring 12a via.
Further, the third wiring 23 is a lead-out wiring at the outer end of the spiral wiring 20 of the inductor element.

As described above, a semiconductor device in which the inductor element 30 shown in FIGS. 1 and 2 and the capacitive element having the MIM structure are mixedly mounted can be manufactured.

In an actual integrated circuit, as shown in FIG. 1, wirings 25 and 26 for bias application are connected to the first wiring 12 and the second wiring 12a in advance. Then, after forming the inductor element 30, a step of applying a bias through the wiring 25 or 26 for bias application is performed. As a result, the inductor element 30A or the third wiring 23-the electrode 9a formed by the third wiring 23-the electrode 9-the first wiring 12-the electrode 8-the spiral wiring 20-the contact portion 14-the lead wiring 10 is formed. -Second wiring 12a-Electrode 8a-Part of spiral wiring 20-
An inductor element 30B including the contact portion 14 and the lead wiring 10 is formed.

In the above-mentioned embodiment, the capacitance element M
IM structure and spiral wiring 20 of inductor element
And MI connected to the third wiring 23 for taking out the electrode
Although the M structure is formed at the same time by using the forming process, the MIM structure on the inductor element side and the capacitive element may be formed in independent processes.

If the formation steps are performed at the same time as in the above-described embodiment, the number of steps can be reduced, the manufacturing cost can be reduced, and the capacitive element can have the MIM structure. A capacitive element which is advantageous in terms of parasitic resistance and parasitic capacitance can be formed.

According to the manufacturing process of this embodiment described above,
With the same inductor element, it is possible to manufacture a structure in which the inductance can be changed according to the application. That is, by manufacturing the inductor element 30 in the state shown in FIG. 1 and performing the step of causing the dielectric breakdown of the dielectric film 5 by changing the wirings 25 and 26 for applying a bias according to the application, an inductor having a desired inductance is obtained. The device 30A or 30B can be manufactured.

Further, according to the above-described manufacturing process of the present embodiment, it is possible to form a capacitive element (capacitor) having a high performance in terms of parasitic resistance and parasitic capacitance at the same time as the inductor element. , It is advantageous in terms of high performance of the integrated circuit.

In each of the above-described embodiments, the wiring 20 of the inductor element 30 has a spiral shape, but the wiring of the inductor element may have another shape (for example, an S shape or a shape in which a plurality of spirals are connected).

In each of the above-mentioned embodiments, the dielectric film 5 is formed on both ends of the first wiring 12 and the second wiring 12a.
It is connected to the wirings 20 and 23 via. In the present invention,
Regarding the first wiring 12 and the second wiring 12a connected to the wiring of the inductor element via the dielectric film 5, the wiring on the side opposite to the wiring 20 of the inductor element (third wiring 23)
The connection with may be made directly without using the dielectric film 5. In addition, the side opposite to the wiring 20 of the inductor element of the first wiring 12 and the second wiring 12a is further extended,
It is also possible to directly or indirectly connect to another circuit element formed on the same substrate 1.

Further, in each of the above-described embodiments, the first wiring 12 and the second wiring 12a are formed by the wiring of the first layer, and the spiral wiring 20 and the third wiring 23 of the inductor element are formed into the third wiring. Although the wiring is formed of two layers, in the present invention, the wiring of the inductor element and the wiring connected to the end or the middle of the inductor element are used as another wiring layer (for example, the first wiring and the second wiring). It is also possible to adopt a configuration in which the vertical relationship of the wiring layers is modified, such as the configuration in which the wiring is formed by the wiring of the third layer.

In the above embodiment, the spiral wiring 20 of the inductor element is grounded and a bias is applied to the first wiring or the second wiring to destroy the dielectric film. However, the method is not limited to this method, and a voltage (potential difference) may be applied between the wiring of the inductor element and the first wiring or the second wiring when the dielectric film is destroyed.

The present invention is not limited to the above-mentioned embodiments, and various other configurations can be adopted without departing from the gist of the present invention.

[0073]

According to the present invention described above, it is possible to selectively obtain inductor elements having different numbers of turns by breaking the dielectric film connected to the first wiring or the second wiring. Therefore, the inductance of the inductor element can be made variable. This makes it possible to form an inductor element having a desired inductance. Therefore, it is possible to realize a desired high-performance integrated circuit without degrading the characteristics of other elements.

Further, according to the present invention, since the connecting portion between the inductor element and the wiring has the MIM structure, the capacitor element having the high performance MIM structure in terms of parasitic resistance and parasitic capacitance should be formed simultaneously with the inductor element. Is possible, which is advantageous in improving the performance of the integrated circuit.

Further, when a plurality of wirings connected in the middle of the wiring of the inductor element are provided so as to be connected to different portions of the wiring of the inductor element, the inductance can be discretely changed from the same inductor element. It will be possible. As a result, it becomes possible to arbitrarily change the inductance of the same circuit depending on the application. Therefore,
Even if there are variations in characteristics in the semiconductor forming process, the inductance can be trimmed after the semiconductor manufacturing process is completed, and a high-performance integrated circuit can be manufactured.

Further, according to the present invention, it is possible to efficiently develop and design a high performance integrated circuit in a short period of time.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram (plan view) of a capacitor element according to an embodiment of the present invention.

2 is a sectional view taken along line XX in FIG. B
It is sectional drawing in YY of FIG. C ZZ of FIG.
FIG.

3A and 3B are plan views of a capacitor obtained by dielectric breakdown of the capacitance of the capacitor element of FIG.

4A to 4C are process diagrams showing a manufacturing process of a semiconductor device in which the capacitor element and the capacitor element of FIG. 1 are formed on the same semiconductor substrate.

5A to 5F are process diagrams showing manufacturing steps of a semiconductor device in which the capacitor element and the capacitor element of FIG. 1 are formed on the same semiconductor substrate.

FIG. 6 is a plan view in the state of FIG. 5D.

FIG. 7 is a plan view in the state of FIG. 5F.

8A and 8B are schematic configuration diagrams of a conventional spiral capacitor element.

[Explanation of symbols]

1 silicon substrate, 2 element isolation film, 3 interlayer insulating film,
5 dielectric film, 10 lead wiring, 12 first wiring,
12a second wiring, 20 (spiral-shaped) wiring,
23 Third wiring, 30, 30A, 30B Inductor element, C1, C2, C3, C4 Capacitance (capacitor)

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[Procedure amendment]

[Submission date] December 27, 2001 (2001.12.
27)

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0041

[Correction method] Change

[Correction content]

When considered at a high frequency, the capacitance also becomes one of the resistances. Therefore, for example, in the structure in which the first wiring 12 side in FIG. 3A is connected, the spiral wiring 20-dielectric film 5-second wiring 12a. It also becomes necessary to consider the current that flows in the branched portion. However, if the capacitance formed in this portion is set to about several tens of fF to several fF, it becomes a resistance of several hundreds to several tens of kΩ even at 10 GHz. Therefore, it is not necessary to consider the branch of the current due to this.

Claims (13)

[Claims] 1. A semiconductor device in which an inductor element is formed on at least a substrate, wherein a first wiring is connected to one end of the wiring of the inductor element via a dielectric film. A semiconductor device, characterized in that a second wiring is connected to an intermediate portion via a dielectric film. 2. The semiconductor device according to claim 1, wherein a plurality of wirings are provided as the second wirings, and the wirings are connected to different portions in the middle of the wiring of the inductor element. 3. The wiring of the inductor element is the first
Of the first wiring and the second wiring, and a dielectric layer is formed at an end opposite to the end of the first wiring and the second wiring connected to the wiring of the inductor element. The semiconductor device according to claim 1, wherein the third wiring is connected via a film. 4. The wiring of the inductor element and the third wiring
4. The semiconductor device according to claim 3, wherein said wiring is connected to said first wiring and said second wiring via said dielectric film and a conductive film thereon. 5. The semiconductor device according to claim 1, wherein the wiring of the inductor element has a spiral shape. 6. The semiconductor device according to claim 1, wherein a capacitive element is formed on the substrate, and the dielectric film of the capacitive element is formed of the same film as the dielectric film. 7. The semiconductor device according to claim 1, wherein any one of the first wiring and the second wiring has a wiring of the inductor element by breaking the dielectric film. A semiconductor device, which is electrically connected to. 8. A method of manufacturing a semiconductor device in which an inductor element is formed on an insulating film on a substrate, comprising the steps of forming a first conductive film on the insulating film, and the first conductive film. Forming a dielectric film on the dielectric film; forming a second conductive film on the dielectric film; patterning the second conductive film and the dielectric film below the conductive film; A step of patterning the conductive film to form a lower wiring, and a third conductive film so as to connect to the lower wiring directly or through the second conductive film and the dielectric film thereunder. Forming a wiring of the inductor element by wiring of one of the upper wiring and the lower wiring, and forming the wiring of the other layer by the wiring of the other layer. Connected to one end of the element wiring A first wiring and a second wiring connected in the middle of the wiring of the inductor element are formed, and the first wiring and the second wiring and the wiring of the inductor element are connected to the second conductive layer. A method of manufacturing a semiconductor device, comprising connecting through a film and the dielectric film below the film. 9. The method of manufacturing a semiconductor device according to claim 8, wherein a plurality of wirings connected to different locations in the middle of the wiring of the inductor element are formed as the second wirings. 10. The wiring of the inductor element is formed by the wiring of the upper layer, the first wiring and the second wiring are formed of the wiring of the lower layer, and the first wiring and the second wiring are formed. A third wiring is formed by the upper wiring so as to be connected to the end opposite to the end connected to the inductor element via the dielectric film and the second conductive film. Item 9. A method of manufacturing a semiconductor device according to item 8. 11. The method of manufacturing a semiconductor device according to claim 8, wherein the wiring of the inductor element is formed in a spiral shape. 12. The method of manufacturing a semiconductor device according to claim 8, wherein a capacitive element is formed on the substrate, and a dielectric film of the capacitive element is formed simultaneously with the dielectric film. 13. After the step of forming the upper wiring, the dielectric film is destroyed to electrically connect the wiring of the inductor element to the wiring of either the first wiring or the second wiring. 9. The method of manufacturing a semiconductor device according to claim 8, wherein the step of electrically connecting is performed.