JP2003143476A - Image signal processor, image signal processing method and television receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To restrain increase of power consumption for processing even high- definition input image signals (high clock frequency and increase of the memory capacity for reducing or enlarging them. SOLUTION: Before a size changing process for reducing or enlarging an image displayed on a digital base on a display device, a process is executed for lessening the effective pixel number (in other words, image signal speed) in one horizontal period of an input image signal. More concretely, a digital/ analog input processor circuit 113 for changing the pixel number processes for equalizing the effective pixel number of the information image signal with the dot number per horizontal line of the display device, if the former number is greater than the latter, in the front stage of circuits for the size change (scale down processor circuit 114, frame memory 115 and scale up processor circuit 116).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing device, such as a television receiver, provided with a scaling processing circuit for digitally scaling up / down a video displayed on a display device. In particular, the present invention relates to a video signal processing apparatus suitable for reducing power consumption and / or memory capacity in the scaling processing circuit.

[0002]

2. Description of the Related Art In recent years, in computers, particularly personal computers (hereinafter referred to as personal computers), the number of dots has been dramatically improved in order to improve performance and display with high definition. Furthermore, BS digital broadcasting has begun in the field of television, and the broadcasting system is changing from analog to digital. Also, the display device is not limited to the conventional CRT direct-view TV or projection TV,
Fixed pixel display devices, such as a liquid crystal display monitor (hereinafter, referred to as LCD) and a plasma display panel (hereinafter, referred to as PDP), which perform digital signal processing and display, are being commercialized one after another.

Under such circumstances, by directly inputting a digital signal to the display device, high image quality can be achieved without going through the A / D and D / A, and a low price can be achieved. It is considered to interface with a display device. The interface is DVI (Digital V
It is standardized as isual Interface) or DFP (Digital Flat Panel) and is being applied to consumer equipment such as digital broadcasting compatible set top boxes and personal computers.

There are various types of formats of a video signal output from a personal computer and a digital video signal that can be received by a set top box compatible with digital broadcasting (in other words, sent from the broadcasting station side). An example thereof is shown in FIG. For example, in the case of television signals, there are the NTSC system which is the current analog broadcast and the HDTV broadcast standard of 1080i and 720p. VGA for personal computer signals
To UXGA, and more recently, signals with the number of pixels larger than UXGA have been proposed, and devices capable of outputting high-definition signals have begun to appear on the market.

[0005]

By the way, in the above-mentioned display device, it is necessary to display an image corresponding to signals having various signal specifications as shown in FIG.
A fixed pixel display device has a fixed number of pixels, a refresh rate, and a dot clock that are determined for each device.
It is necessary to convert and display the image by reduction or enlargement processing. Therefore, a device having a display device or a device transmitting a video signal to the display device requires a digital video signal processing circuit having a large circuit scale.

Further, if the dot clock frequency of the input digital video signal is reduced or enlarged with respect to various signal specifications as shown in FIG. 6, the following problems occur. For example, when the input video signal is UXGA, about 2
It is necessary to perform digital image processing with a high-speed clock signal as high as 30 MHz, and when the digital video signal processing circuit is operated at high speed, power consumption increases. In addition, the memory capacity for performing the reduction and enlargement processing also becomes large, resulting in an expensive system.

The present invention has been made in view of the above problems. The purpose is that the input video signal is high definition
Even if the clock frequency is high, increase in power consumption due to signal processing of the video signal is suppressed, and /
Alternatively, it is possible to suppress an increase in the memory capacity for performing the reduction or enlargement processing.

[0008]

In order to achieve the above object, according to the present invention, before the size conversion processing for digitally enlarging / reducing the image displayed on the display device, the input image signal of the input image signal is converted. The processing for reducing the number of effective pixels (in other words, the speed of the video signal) in one horizontal period is performed.

More specifically, when the number of effective pixels per horizontal period of the input video signal is larger than the number of dots per horizontal line of the display device at the stage before the size conversion processing, the effective pixel is effective. Processing for making the number of pixels equal to the number of dots is performed. For example, when the number of effective pixels per horizontal cycle of the input video signal is 800 and the number of dots per horizontal line of the display device is 640, the effective pixel number is reduced to 640 in advance.

With this configuration, the input video signal of the high-speed dot clock frequency can be converted into the video signal of the low-speed clock frequency before digitally performing the enlargement / reduction processing of the image. , Later (digital)
The clock frequency of the scaling processing circuit can be reduced. Therefore, optimal pixel conversion for the display device is possible, and power consumption can be significantly reduced. Further, the memory capacity for performing the reduction or enlargement processing may be the optimum capacity for the display capability of the display device. Therefore, an inexpensive memory which has a low speed and a small capacity can be used, and an inexpensive system can be constructed.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described with reference to the drawings. In addition, the same reference numerals are given to portions common to each drawing. FIG. 1 is a block diagram showing a first embodiment of a video signal processing device according to the present invention. In the embodiments described below, a tuner (not shown) for synchronizing the present invention with a display device such as a liquid crystal panel and a PDP and a desired channel of television broadcasting.
An example applied to a television receiver having and is shown.

A digital video signal such as a personal computer or a set top box compatible with digital broadcasting is input to the digital video signal input terminal 101. The digital video signal input to the digital video signal input terminal 101 is a process for reducing the number of effective pixels per horizontal cycle with respect to the input digital video signal (hereinafter, also referred to as speed conversion process). Is supplied to the digital / analog signal input processing unit 103 which is a pixel number conversion unit for performing the above. In the digital / analog signal input processing unit 103, first, an LPF (LPF: L
The input digital video signal is band-limited by the ow pass filter) 106 and output to the speed conversion memory 107. At this time, the sync signal transmitted to the sync signal input terminal 103 together with the digital video signal is
Enable control circuit 108 and first switch circuit 109
Is input to one of the input terminals. Further, the clock signal input to the clock input terminal 102 and transmitted together with the digital video signal is input to the speed conversion memory 107. The enable control circuit 108 generates an enable control signal corresponding to the speed to be converted from the input synchronization signal and inputs the enable control signal to the speed conversion memory 107.

The digital video signal from the LPF 106 is
It is written in the speed conversion memory 107 using a clock and an enable control signal synchronized with the digital video signal.
PLL (PLL: Phase Locked Loop)
Reference numeral 111 inputs the sync signal selected by the first switch circuit 110 (in this case, the sync signal input together with the digital video signal), generates a read clock based on the sync signal, and performs speed conversion. It is supplied to the memory 107. This read clock has a frequency lower than the frequency of the input clock signal, as will be described later. The digital video signal written in the speed conversion memory 107 is
It is read according to the read clock. Therefore,
The speed of the digital video signal is converted according to the ratio of the write clock frequency and the read clock frequency. The speed-converted digital video signal is input to one input terminal of the second switch circuit 112.

On the other hand, the analog video signal input terminal 104 receives an analog video signal from a conventional recording medium device such as a personal computer or a VTR. The analog video signal input to the analog video signal input terminal 104 is A /
It is input to the D converter 109. Sync signal input terminal 105
The sync signal input from the first switch circuit 1 is the sync signal transmitted together with the analog video signal.
10 to the other input terminal. When the digital video signal is used as a display signal, the first switch circuit 110 selects the input of the sync signal input terminal 103,
When using an analog video signal as a display signal,
It operates so as to select the input of the synchronization signal input terminal 105. The synchronization signal selected by the first switch circuit 110 is input to the PLL circuit 111. PLL circuit 11
In 1, the clock synchronized with the sync signal input is generated,
It is input as a clock of the speed conversion memory 107, the A / D conversion circuit 109, and the reduction processing circuit 114 that constitutes a part of the size conversion circuit. The A / D conversion circuit 109 converts an analog video signal into a digital signal and inputs it to the other input terminal of the second switch circuit 112.

Similar to the first switch circuit 110, the second switch circuit 112 selects the output of the speed conversion memory 107 and displays the analog video signal when the digital video signal is used as a display signal. When it is used as a signal for, the output of the A / D conversion circuit 109 is operated to be selected. Then, the digital video signal selected by the second switch circuit 112 is input to the reduction processing circuit 114 which is a part of the size number conversion circuit. Here, in the present embodiment, the size conversion circuit is the reduction processing circuit 11
4, the frame memory 115, and the enlargement processing circuit 116.

The reduction processing circuit 114 reduces the size in the vertical and horizontal directions and writes the data in the frame memory 115. The video signal read from the frame memory 115 is input to the enlargement processing circuit 116, and enlargement processing is performed in the vertical direction and the horizontal direction. Here, the reduction processing circuit 114, the frame memory 115, and the enlargement processing circuit 116 are used to display the LCD.
The image is reduced or enlarged so that the number of vertical and horizontal pixels required for the fixed pixel panel 117 such as a PDP or PDP, the refresh rate, and the dot clock are obtained, and this signal is output to the output terminal 1
Output from 16. Further, the synchronization generation circuit 118 generates a synchronization signal to be given to the fixed pixel panel 122 (a fixed pixel panel such as a liquid crystal panel or a PDP is used as a display device in the present embodiment) which is a display device, and the synchronization signal is generated. While outputting from the output terminal 120,
A clock signal is output from the clock output terminal 121. A video signal output from the output terminal 119, a sync signal output from the sync output terminal 120, and a clock output from the clock output terminal 121 are given to a fixed pixel panel 117 to display a video.

Normally, the digital image processing unit in the subsequent stage of the digital / analog signal input processing unit 113 is not limited to the circuit shown in FIG. 1, but is also a progressive circuit for converting an interlaced signal into a progressive signal, an image quality correction circuit,
Although a large-scale circuit such as a gamma correction circuit and a frame memory control circuit is required, these circuits are not shown in FIG. 1 because they do not substantially relate to the essence of the present invention.

Here, of the signals shown in FIG. 6, a UXGA signal is input as an input signal, and the fixed pixel panel has an XG signal.
A case of a display device having dots corresponding to A will be described as an example. First, UX from the digital video signal input terminal 101
When a GA signal is input, the band is limited by the LPF 106 and input to the speed conversion memory 107. The enable control circuit 108 generates an enable control signal for horizontal reduction so that the number of effective pixels per horizontal cycle of the input digital video signal becomes equal to the number of effective pixels in one horizontal line of the fixed pixel panel. Then, the video data is written in the speed conversion memory 107 using this enable control signal. Here, in the first switch circuit 110, the synchronization signal input together with the digital video signal is input to the PLL 111.
The PLL 111 supplies a clock signal having a frequency such that the number of effective pixels in one horizontal cycle of the input digital video signal becomes equal to the number of effective pixels in one horizontal line of the fixed pixel panel. It is generated and input as a read clock of the speed conversion memory 107.

That is, in the speed conversion memory 107, speed conversion is performed so that the number of horizontal pixels of the UXGA signal input is 1,600 pixels and the number of horizontal pixels corresponding to XGA is 1024 pixels. At this time, the frequency of the read clock of the speed conversion memory is 1024/1600 times the frequency of the clock signal input from the clock input terminal 102. That is, it is equal to the ratio of the number of effective pixels of one horizontal cycle of the input digital video signal to the number of effective pixels of one horizontal line of the fixed pixel panel 122.

The video signal read from the speed conversion memory 107 passes through the second switch circuit 112 and is input to the size conversion circuit. First, the signal selected by the second switch circuit is input to the reduction processing circuit 114, subjected to reduction processing, and input to the frame memory 115. The reduction processing circuit 114 reduces the image in the vertical direction so as to correspond to the number of display pixels of the fixed pixel panel 122, from 1200 pixels which is the vertical pixel number of the UXGA signal input to XGA.
The corresponding number of pixels in the vertical direction is converted into 768 pixels and written in the frame memory 115. The video signal read from the frame memory 115 is input to the enlargement processing circuit 116.
Since this signal is converted into the number of pixels corresponding to XGA, when it is displayed as it is on the fixed pixel panel 122,
The enlargement process is not performed and the image is displayed with the same number of pixels. However, various forms of display on the fixed pixel panel 122 are conceivable. For example, when enlarging and displaying a part of the screen, in the enlarging processing circuit 116, the enlarging ratio according to the display form is used in the vertical and horizontal directions. It can be realized by expanding to.

On the other hand, from the analog video input terminal 104 to U
When the XGA signal is input, the video signal is guided to the A / D conversion circuit 109. Here, the first switch circuit 11
0 switches so that the analog input sync signal is input to the PLL 111, and the PLL 111 causes the A / D conversion circuit 10 to operate.
Generate a clock for 9. At this time, the PLL 111
A clock signal having a frequency such that the number of effective pixels of one horizontal cycle of the input digital video signal becomes equal to the number of effective pixels of one horizontal line of the fixed pixel panel is generated.
The D conversion circuit 109 converts the digital video signal. This digital video signal passes through the second switch circuit 112,
It is input to the reduction processing circuit 114. The processing after the reduction processing circuit 114 performs the same operation as in the case of the digital input described above, and converts the image into the number of vertical and horizontal pixels, the refresh rate, and the dot clock according to the display form of the fixed pixel panel 122, and then the fixed pixel panel. To display.

As described above, since the digital video signal input at the high-speed dot clock frequency can be converted into the digital video signal of the low-speed clock frequency in the speed conversion memory 107 immediately after input, the latter stage The clock frequency of the digital image processing unit having a large circuit scale can be slowed down, optimal pixel conversion can be performed for a fixed pixel panel, and power consumption can be significantly reduced. Further, even in the case of an analog video signal input at a high-speed dot clock frequency, the A / D conversion circuit 109 can convert it into a digital video signal of a low-speed clock frequency, and thus the power consumption can be greatly reduced. Can be done.
In addition, the frame memory 115 for performing reduction and enlargement processing
Also, the memory capacity can be processed with the optimum capacity for the display capacity of the fixed pixel panel, a low speed and low capacity inexpensive memory can be used, and an inexpensive system can be constructed. In particular,
The video signal processing device having a digital input according to this embodiment is generally formed into an LSI, and low power consumption and reduction in memory capacity are particularly effective. Further, in the case of analog input, a PLL is indispensable for clock generation, and also in the case of digital input, sharing the same PLL makes it possible to simplify the system and reduce costs.

The case where a high-definition video signal having a high-speed dot clock frequency is input and converted into a digital video signal having a low-speed frequency and displayed on a fixed pixel panel has been described above. Is not limited to, input a video signal with a slow dot clock frequency,
It is also possible to display a high-speed digital video signal on a fixed pixel panel, and an optimum clock frequency can be set according to the digital image processing unit in the subsequent stage.

An example of the detailed operation of the speed conversion memory 107 will be described with reference to FIG. FIG. 2A is a diagram showing an input clock of a digital video signal from the clock input terminal 102 and also showing a write input clock of the speed conversion memory 107. FIG. 2B shows the speed conversion memory 1
07 shows an enable control signal, and FIG. 2C shows a digital video signal input to the speed conversion memory 107.
FIG. 2D is a diagram showing a PLL 111 output and a read clock of the speed conversion memory 107, and FIG. 2E is a diagram showing an output of a digital video signal whose clock frequency is speed converted by the speed conversion memory 107. is there.

For ease of explanation, FIG. 2 shows a case where the output frequency of the digital video signal of the speed conversion memory 107 is set to 2/3 times the input frequency.

The input digital video signal is synchronized with the input clock, as shown in FIG.
3, A4. ... is entered. At this time, in the speed conversion memory 107, the input is ⅔ times as large as the input, so that the enable control circuit 108 outputs an enable control signal for stopping writing to the speed conversion memory every three pixels as shown in FIG. 2B. Generate and control the writing of digital video data to the speed conversion memory. In the PLL111, as shown in FIG.
As shown in (d), a clock whose generated clock frequency is ⅔ of the input clock frequency is generated. The digital video signal read from the speed conversion memory 107 is A1, A2, as shown in FIG.
A4, A5. Is output at a speed 2/3 times as fast as the input digital video signal.

By performing such an operation, the digital video signal input at the high speed dot clock frequency can be converted into the digital video signal of the low speed clock frequency in the speed conversion memory 107 immediately after the input. The clock frequency of the digital image processing unit having a large circuit scale in the subsequent stage can be slowed down, optimal pixel conversion can be performed for a fixed pixel panel, and power consumption can be significantly reduced. Further, even in the case of an analog video signal input at a high-speed dot clock frequency, the A / D conversion circuit 109 can convert it into a digital video signal of a low-speed clock frequency, and thus the power consumption can be greatly reduced. Can be done. Further, the memory capacity of the frame memory 115 for performing the reduction and enlargement processing can be processed with the optimum capacity for the display capacity of the fixed pixel panel, and a low-speed and low-capacity inexpensive memory can be used to construct an inexpensive system. be able to. In the present embodiment, the case where the speed is converted to 2/3 speed has been described, but the speed conversion of an arbitrary magnification can be performed by arbitrarily controlling the frequency division ratio of the PLL 111.

FIG. 3 is a configuration block diagram showing an example of the second embodiment according to the present invention. The embodiment of FIG. 3 implements a digital / analog signal input processing unit in order to realize a function of displaying two systems of video inputs such as left and right dual screen display and picture-in-picture on a single screen on a television or monitor.
This system is intended to be multi-functional and is different from the embodiment shown in FIG. 1 in this respect.

In the present embodiment, the first digital / analog signal input processing unit 113, as described in the first embodiment, sets the clock frequency of the digital video signal by the speed conversion memory 107 when the digital video signal is input. The speed conversion is performed, and at the time of analog input, it is converted into a digital signal in the A / D conversion circuit 109, and the image reduction / multiplexing circuit 307.
Output to. The second digital / analog signal input processing unit 306 also performs the same operation as the first digital / analog signal input processing unit 113, and the video reduction / multiplexing circuit 3
It outputs to the other input of 07. Video reduction multiplex circuit 3
In the case of realizing, for example, two screens 07, the input from the first digital / analog input processing unit 113 is horizontally reduced so that the input becomes half of the screen in the horizontal direction, and the second digital / analog input The processing unit 306 is also horizontally displayed on the screen 1
Horizontal reduction is done to become / 2. Further, since both inputs have different synchronization timings, they are written to and read from the frame memory 115 to guide the left and right two screens to the enlargement processing circuit 116 in synchronization with each other. Video reduction multiplexing circuit 307,
In the frame memory 115 and the enlargement processing circuit 116, the first
Similar to the above embodiment, the image is converted into the number of vertical and horizontal pixels, the refresh rate, and the dot clock according to the display form of the fixed pixel panel and displayed on the fixed pixel panel.

As described above, in the digital video signal input or the analog video signal input, it is possible to realize various screen displays such as two screens and multi screens when two different video signals are input. A digital video signal input at a high-speed dot clock frequency can be converted into a digital video signal having a low-speed clock frequency in the speed conversion memory 107 immediately after input, so that the digital image processing unit of the latter stage having a large circuit scale can The clock frequency can be slowed down, optimal pixel conversion can be performed for a fixed pixel panel, and power consumption can be significantly reduced. In the case of an analog video signal input at a high dot clock frequency, the A / D conversion circuit 10
Since the digital video signal having the low clock frequency can be obtained in No. 9, similarly, the power consumption can be greatly reduced. Further, the memory capacity of the frame memory 115 for performing the reduction and enlargement processing can be processed with the optimum capacity for the display capacity of the fixed pixel panel, and a low-speed and low-capacity inexpensive memory can be used to construct an inexpensive system. be able to.

FIG. 4 is a configuration block diagram showing an example of the third embodiment according to the present invention. In the embodiment of FIG. 4, 401 is a D / A conversion circuit for converting a digital video signal into an analog video signal, 402 is an output terminal of the analog video signal, and 403 is a cathode ray tube type CRT monitor.

In the first embodiment shown in FIG. 1, a signal input by a digital video signal input or an analog video signal input is converted according to a fixed pixel panel for displaying and a video signal is digitally output. However, in the present embodiment, the same effect can be obtained even with a CRT monitor having a coarse definition in consideration of television display by having a configuration in which the video signal is output in analog.

In this embodiment, as described in the first embodiment, the analog / digital input processing unit 113 performs speed conversion of the clock frequency of the digital video signal by the speed conversion memory 107 when the digital video signal is input. At the time of analog input, the A / D conversion circuit 109 converts the signal into a digital signal, the second switch circuit 112 selects a video signal, and outputs the video signal to the reduction processing circuit 114. The reduction processing circuit 114, the frame memory 115, and the enlargement processing circuit 116 perform pixel conversion such as reduction and enlargement of the image so that the number of vertical and horizontal pixels required for the CRT monitor 403, the refresh rate, and the dot clock are obtained, and D / The signal is guided to the A conversion circuit 401. The signal converted into the analog video signal by the D / A conversion circuit 401 is output from the output terminal 402 and displayed on the CRT monitor 403.

As described above, in a CRT monitor with a high definition in consideration of television display, a digital video signal input at a high dot clock frequency is input to the speed conversion memory 107 at a low speed clock immediately after input. Since the digital video signal having the frequency can be used, the clock frequency of the digital image processing unit having a large circuit scale in the subsequent stage can be reduced, the pixel conversion suitable for the CRT monitor can be performed, and the power consumption can be significantly reduced. it can. Further, even in the case of an analog video signal input at a high-speed dot clock frequency, the A / D conversion circuit 109 can convert it into a digital video signal of a low-speed clock frequency, and thus the power consumption can be greatly reduced. Can be done.
In addition, the frame memory 115 for performing reduction and enlargement processing
Also, the memory capacity can be processed with the optimum capacity for the display capacity of the fixed pixel panel, a low speed and low capacity inexpensive memory can be used, and an inexpensive system can be constructed.

FIG. 5 is a configuration block diagram showing an example of the fourth embodiment according to the present invention. In the embodiment of FIG. 5, 501 is a clock input terminal 10 for inputting a digital signal.
A second PLL circuit that generates a clock obtained by dividing the clock from 2 and a reference numeral 502 is a third switch circuit that switches the clock.

In the first embodiment shown in FIG. 1, the PLL 111 in which the synchronizing signals of digital and analog inputs are shared is constructed, but in the present embodiment, for example, an analog signal input section and a digital signal input section are provided. When each is configured by a separate LSI, an optimal system configuration can be obtained by using different PLLs.

In this embodiment, as in the first embodiment shown in FIG. 1, the digital video signal is taken into the speed conversion memory 107 by the output video signal of the LPF 106 and the synchronized clock and enable control signal. The read clock of the speed conversion memory 107 divides and oscillates a low-speed clock corresponding to the fixed pixel panel 122 in the second PLL 501. Speed conversion memory 1 with this clock
The digital video signal is read from 07 and input to the second switch circuit 112. In addition, the second PLL circuit 501
Is input to the third switch circuit 502.

On the other hand, an analog video signal from a conventional personal computer, a recording media device such as a VTR, etc., inputted from the analog video signal input terminal 104, is inputted to the A / D converter 109. Analog video signal sync signal input terminal 10
The synchronization signal input from 5 is directly input to the PLL circuit 111. The PLL circuit 111 generates a clock synchronized with the input of the synchronizing signal, converts the analog video signal into a digital signal in the A / D conversion circuit 109, and inputs it to the other input of the second switch circuit 112. To do. The clock of the PLL circuit 111 is input to the other input of the third switch circuit 502. This second
The switch circuit 112 and the third switch circuit 502 of
When selecting digital video signals, speed conversion memory 1
When selecting the output of 07 and the clock of the second PLL circuit 501 and selecting the analog video signal, the operation of selecting the output of the A / D conversion circuit 109 and the clock of the PLL circuit 111 is performed. The digital video signal selected by the second switch circuit 112 is input to the reduction processing circuit 114. The processing after the reduction processing circuit 114 performs the same operation as that of the first embodiment to convert the image into the number of vertical and horizontal pixels, the refresh rate, and the dot clock according to the display form of the fixed pixel panel, and LCD, PDP, etc. The fixed pixel panel 122 is displayed.

As described above, even when the analog signal input section and the digital signal input section are configured by different LSIs, the first embodiment has a configuration in which different clock oscillations are performed for the digital input signal and the analog input signal. The same effect as can be obtained. That is, since a digital video signal having a low clock frequency can be converted into the speed conversion memory 107 immediately after input, the clock frequency of the digital image processing unit having a large circuit scale in the subsequent stage can be made low, which is suitable for a fixed pixel panel. It is possible to perform various pixel conversions and significantly reduce power consumption. Further, even in the case of an analog video signal input at a high-speed dot clock frequency, the A / D conversion circuit 109 can convert it into a digital video signal of a low-speed clock frequency, and thus the power consumption can be greatly reduced. Can be done. Further, the memory capacity of the frame memory 115 for performing the reduction and enlargement processing can be processed with the optimum capacity for the display capacity of the fixed pixel panel, and a low-speed and low-capacity inexpensive memory can be used to construct an inexpensive system. be able to. In particular, the video signal processing device having a digital input described in this embodiment is generally formed into an LSI, and low power consumption and reduction in memory capacity are particularly effective.

[0040]

As described above, according to the configuration of the present invention, the digital video signal input at the high speed dot clock frequency is converted into the digital video signal of the low speed clock frequency before the size conversion processing. Therefore, power consumption can be reduced. In addition, a low-speed, low-capacity, inexpensive memory can be used, and an inexpensive system can be constructed.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of a first embodiment of the present invention.

FIG. 2 is a block diagram showing an example of detailed operation of a speed conversion memory according to the present invention.

FIG. 3 is a block diagram showing an example of a second exemplary embodiment of the present invention.

FIG. 4 is a block diagram showing an example of a third exemplary embodiment of the present invention.

FIG. 5 is a block diagram showing an example of a fourth exemplary embodiment of the present invention.

FIG. 6 is a diagram showing an example of signal specifications of a television signal and a personal computer signal.

[Explanation of symbols]

101 ... Digital video signal input terminal, 102 ... Clock input terminal, 103 ... Digital synchronization signal input terminal, 104
... analog video signal input terminal, 105 ... analog synchronization signal input terminal, 106 ... digital LPF, 107 ... speed conversion memory, 108 ... enable control circuit, 109 ... A /
D conversion circuit, 110 ... First switch circuit, 111 ... P
LL circuit, 112 ... Second switch circuit, 113 ... Digital / analog signal input processing unit, 114 ... Reduction processing circuit, 115 ... Frame memory, 116 ... Enlargement processing circuit,
117 ... Output processing clock input terminal, 118 ... Synchronous generation circuit, 119 ... Digital video signal output terminal, 120 ...
Synchronous output, 121 ... Clock output terminal, 122 ... Fixed pixel panel, 301 ... Second digital video signal input terminal,
302 ... Second clock input terminal, 303 ... Second digital synchronization signal input terminal, 304 ... Second analog video signal input terminal, 305 ... Second analog synchronization signal input terminal, 306 ... Second digital / analog Signal input processing unit, 307 ... Video reduction / multiplexing circuit, 401 ... D / A conversion circuit, 402 ... Analog video signal output terminal, 403 ... CR
T monitor, 501 ... Second PLL circuit, 502 ... Third switch circuit.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H04N 5/45 H04N 5/45 5C080 5/66 5/66 D (72) Inventor Katsunobu Kimura Yokohama City, Kanagawa Prefecture 292, Yoshida-cho, Totsuka-ku, Hitachi Co., Ltd. (72) Inventor Takeshi Sakai, 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa (72) In-house Hitachi, Ltd. Tech, Kazuo Ishikura Ome, Tokyo F-Term in Device Development Center, Hitachi, Ltd. 3-16-16 Shinmachi (reference) 5C006 AA01 AB01 AF01 AF71 AF81 BC11 BC16 BF23 FA05 FA07 FA08 5C020 AA01 AA09 AA35 CA15 5C023 AA02 AA38 CA03 DA04 5C025 BA27 BA28 CA06 5A058 A06 A11 BA35 BB11 5C080 AA10 BB05 DD21 EE21 JJ02 JJ04 KK02 KK43

Claims (21)

[Claims] 1. A video signal processing apparatus comprising a size conversion circuit for inputting a video signal, converting the size of the input video signal in the vertical and / or horizontal direction, and supplying the size to a display device. A video signal processing device comprising a pixel number conversion means for reducing the number of effective pixels per horizontal cycle of the input video signal before being supplied. 2. The pixel number conversion means reduces the number of effective pixels per horizontal cycle of the input video signal when the number of effective pixels per horizontal cycle of the input video signal is larger than a predetermined value. The video signal processing apparatus according to claim 1, further comprising: 3. The video signal processing apparatus according to claim 2, wherein the predetermined value is equal to the number of dots per horizontal line of the display device. 4. At least a plurality of types of video signals having different numbers of pixels per horizontal cycle can be input, and the vertical and / or horizontal sizes of the input video signals are converted and supplied to a display device. In a video signal processing device having a size conversion circuit, when the number of effective pixels per horizontal cycle of the input video signal is larger than the number of dots per horizontal line of the display device, the size conversion circuit is supplied to the size conversion circuit. A video signal processing device comprising a pixel number conversion means for reducing the number of effective pixels per horizontal cycle of the input video signal before the input. 5. The pixel number conversion means performs processing for making the number of effective pixels per horizontal cycle of the input video signal equal to the number of dots per horizontal line of the display device. Item 4. The video signal processing device according to item 4. 6. The video signal processing according to claim 1, wherein the input video signal is a digital video signal, and a clock signal and a synchronization signal are input together with the digital video signal. apparatus. 7. The pixel number conversion means controls an LPF that band-limits the input video signal, a memory in which a video signal band-limited by the LPF is written by the input clock signal, and a write timing of the memory. And an enable control circuit for generating an enable control signal for outputting to the memory based on the input synchronization signal, and generating a read clock signal having a frequency lower than the frequency of the input clock signal from the synchronization signal. The video signal processing device according to claim 6, further comprising a PLL circuit that outputs the video signal to the memory, and the video signal read from the memory according to the read clock is supplied to the size conversion circuit. . 8. A digital video signal and an analog video signal can both be input as the video signal, and a first clock signal and a first synchronization signal are input together with the digital video signal, and the analog video signal 6. A second synchronization signal is also input together with the second synchronization signal.
The video signal processing device according to any one of 1. 9. The pixel number conversion means includes an LPF for band-limiting the input video signal, a memory into which the video signal band-limited by the LPF is written by the first clock signal, and a write timing of the memory. And an enable control circuit for generating an enable control signal for controlling the output of the enable control signal based on the first synchronization signal and outputting the enable control signal to the memory, and selecting either the first synchronization signal or the second synchronization signal. A first switch circuit for outputting the analog video signal and an A / D converter for converting the analog video signal into a digital signal,
A second clock signal having a frequency lower than that of the first clock signal is generated from the synchronization signal output from the first switch circuit to generate the memory and the A / D.
The PLL circuit for outputting to the converter, the video signal read from the memory by the second clock, and the video signal converted into a digital signal by the A / D converter are selected, and The video signal processing device according to claim 8, further comprising a second switch circuit that supplies the size conversion circuit. 10. The frequency of the read clock output from the PLL circuit is equal to the ratio of the number of effective pixels per horizontal cycle of the input video signal to the number of dots per horizontal line of the display device. The video signal processing device according to claim 7, wherein the video signal processing device comprises: 11. The video signal processing apparatus according to claim 7, wherein the read clock output from the PLL circuit is used as a clock for size conversion processing in the size conversion circuit. 12. The size conversion circuit includes at least a circuit for converting the number of lines of a video signal output from the pixel number conversion circuit, according to any one of claims 1 to 11. Video signal processing device. 13. A video signal processing apparatus comprising a size conversion circuit for inputting a video signal, converting the size of the input video signal in the vertical and / or horizontal direction, and supplying the converted video signal to a display device. A video signal processing device comprising a speed conversion circuit for controlling a clock frequency of the input video signal with respect to the input video signal before being supplied to convert the speed of the input video signal. 14. The speed conversion circuit includes a digital signal input terminal to which a digital video signal, a first synchronizing signal and a clock signal are input, and an analog signal input terminal to which an analog video signal and a second synchronizing signal are input. A digital LPF for band limiting the digital video signal from the digital signal input terminal, a speed conversion memory in which the video signal of the digital LPF is written by the input clock signal, and the speed from the first synchronization signal. An enable control circuit for generating an enable control signal for a conversion memory, an A / D conversion circuit for converting an analog video signal from the analog signal input terminal into a digital video signal, the first synchronizing signal and the second A first switch circuit that selects and outputs one of the synchronization signals and a synchronization signal from the first switch circuit is input The PLL circuit for generating the read clock of the speed conversion memory and the clock of the A / D conversion circuit, the video signal from the speed conversion memory and the video signal from the A / D conversion circuit are selected to select the size. The video signal processing device according to claim 13, further comprising a second switch circuit for outputting to the conversion circuit. 15. The size conversion circuit includes a reduction processing circuit for reducing the number of pixels and / or the number of lines of the signal output from the second switch circuit according to a display format and a display device specification. A frame memory that stores the output signal from the reduction processing circuit, and an enlargement processing circuit that enlarges the number of pixels and / or lines of the signal read from the frame memory according to the display format and the specifications of the display device. A video signal processing device comprising: 16. The video signal processing apparatus according to claim 15, further comprising a D / A conversion circuit which converts a signal from the enlargement processing circuit into an analog signal and supplies the analog signal to the display device. . 17. The number of effective pixels in one horizontal period of the input video signal is converted at a stage before converting the number of lines of the input video signal to enlarge / reduce the image displayed on the display device. A video signal processing method characterized by executing a pixel number conversion process for reducing. 18. The pixel number conversion process, wherein when the number of effective pixels per horizontal cycle of the input video signal is larger than the number of dots per horizontal line of the display device,
18. The video signal processing method according to claim 17, further comprising processing for making the number of effective pixels equal to the number of dots. 19. A television receiver comprising a display device for displaying a video and a size conversion circuit for converting a vertical and / or horizontal size of an input video signal and supplying the size to the display device. A television receiver comprising a pixel number conversion unit for reducing the number of effective pixels per horizontal cycle of the input video signal before being supplied to the conversion circuit. 20. The number-of-pixels conversion means sets 1 of the input video signal when the number of effective pixels of the input video signal per horizontal cycle is larger than the number of dots per horizontal line of the display device. 20. The television receiver according to claim 19, wherein processing is performed to reduce the number of effective pixels per horizontal cycle to be equal to the number of dots. 21. A television receiver comprising a display device for displaying a video and a size conversion circuit for converting a vertical and / or horizontal size of an input video signal and supplying the size to the display device. A television receiver including a speed conversion circuit for controlling a clock frequency of the input video signal with respect to the input video signal before being supplied to the circuit to convert the speed of the input video signal. .