JP2003141887A - Nonvolatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory in which high speed operation and reduction of chip area can be achieved simultaneously. SOLUTION: This device is constituted of a block decoder/auxiliary gate decoder, a sub-decoder, a gate decoder, a selection MOS transistor, a sense amplifier, a memory cell sub-array, or the like. Memory cells C000-C030 has structure of an associative ground type sharing mutually a local drain line and a local source line being adjacent on the same word line, as they have an auxiliary gate in addition to a control gate and a floating date, an operation current is suppressed though operation is write operation by injection of hot electrons, parallel operation being equal to write operation by FN tunnel can be realized, further, as a sub-decoder 20 driving word lines comprises two NMOS for one word line, layout of a sub-decoder can be adapted to making microfabrication.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device such as a flash memory, and more particularly to reducing the layout area of a decoder element which constitutes a decoder circuit,
The present invention relates to a technique effectively applied to a non-volatile semiconductor memory device that enables high integration.

[0002]

According to a study made by the present inventor, the following techniques can be considered for a flash memory as an example of a nonvolatile semiconductor memory device.

Since flash memories are excellent in portability and shock resistance and can be electrically erased collectively, in recent years, there has been a rapid demand for them as files for small portable information devices such as portable personal computers and digital still cameras. It is expanding. In order to expand the market, it is essential to reduce the bit cost by reducing the memory cell area, and various memory cell systems that realize this have been proposed. For example, 19
94 Symposium on VLSI Circ
uits, Digest of Technical
Papers, pp. 61-62, etc. are mentioned.

The following is a technology which has not been publicly known but has been examined by the present inventor as a premise of the present invention, and the outline thereof is as follows.

FIG. 12 shows an example of an array configuration in a flash memory. In the figure, C000 to C00
m and C100 to C10m are memory cells, and one data line (D0 or D1) is provided in the sub array in one block.
There are m memory cells above. W00-W1m
Is a word line. The sources (S0 or S1) and drains (D0 or D1) of the memory cells in one block are commonly connected using a diffusion layer. This source is a block selection MOS transistor (ST0S or ST1) controlled by S0S or S1S.
It is connected to the common source line (SL0) via S). The drain is connected to the global data line (DL0) via the block selection MOS transistor (ST0D or ST1D) controlled by S0D or S1D. By using the diffusion layer wiring in this way, one contact hole to the metal wiring can be shared by m memory cells, and the memory cell area can be miniaturized.

Further, the word decoder circuit is hierarchized into a block decoder for selecting a block and a gate decoder and a sub-decoder for selecting a specific word line in the selected block in order to increase the speed. .
FIG. 13 shows a configuration example of the sub-decoder element. The sub-decoder element forming the sub-decoder is a complementary MOS (CMO
S) inverter, each output of which is connected to a word line.

In FIG. 12, G00 to G0m are word line selection gate signals input to each sub-decoder, and B
0P and B1P are source signals of a P-channel type MOS transistor (hereinafter referred to as PMOS) which is each sub-decoder element, and B0N and B1N are N-channel type MOS transistors (hereinafter referred to as NMOS) which are each sub-decoder element.
Is the source signal of. The gate signal of the sub-decoder element and the source signal of the PMOS and the source signal of the NMOS can be independently controlled by the hierarchical gate decoder and the block decoder, and the sub-decoder having the inverter configuration is provided for each word line. One is provided. The memory cell is a so-called AND type flash memory including a floating gate for storing electrons and a control gate connected to a word line. Each operation of writing, erasing and reading will be briefly described. Table 5 shows each operating voltage when the selected memory cell is assumed to be C000.

[0008]

[Table 5]

In the write operation, for example, B0P = 17V,
By setting B0N = 4.5V and G00 = 0V, W0
0 = 17V. At this time, for example, DL0 = 0V, S0
Set D0 = 0V with D = 3V, SL0 = 0V, S0S
By setting S0 = floating with = 0 V, electrons are injected into the floating gate by the Fowler-Nordheim tunnel phenomenon (hereinafter referred to as FN tunnel phenomenon). In the erase operation, for example, B0P = 0V, B0
By setting N = -16V and G00 = 2V, W00 =
-16V. At this time, for example, SL0 = DL0 = 2
By setting V0, S0D = S0S = 7V, and setting D0 = S0 = 2V and the substrate voltage of the memory cell = 2V, electrons are emitted from the floating gate to the substrate by the FN tunnel phenomenon. In the read operation, for example, B0P = 3V, B0
By setting N = 0V and G00 = -1V, W00 = 3
V. At this time, for example, DL0 = 1V, S0D = 5V
Is set to D0 = 1V, SL0 = 0V, S0S = 3V, and S0 = 0V. At this time, if the memory cell is in the written state, the threshold value is high and D0 = 1V is held, and if the memory cell is in the erased state, the threshold value is low and a current flows and D0 = 0V. Reading is performed by verifying this with a sense amplifier.

FIG. 14 is a schematic layout diagram of a sub-decoder element of the precondition technique of the present invention, which controls the word lines as described above. The PMOS and NMOS of the inverter forming each sub-decoder are laid out so as to be divided into a region for laying out the PMOS by separating the well and a region for laying out the NMOS and connected in series in the word line direction.

[0011]

However, the above sub-decoder having the inverter structure causes a problem with the miniaturization of the memory cell. As the memory cells become finer, the block length shown in FIG. 14 tends to become smaller and smaller. On the other hand, the sub-decoder with the inverter configuration is
Due to the circuit configuration, it is necessary to divide the diffusion layer into two MOS units as shown in FIG. Also, PMOS and NMO
A well isolation region for dividing S is required. Therefore, there is a problem that the layout of the sub-decoder cannot keep up with the miniaturization of memory cells.

As a means for solving this problem, a method of forming all the decoder elements by NMOS can be considered. If all the decoder elements are composed of NMOS, it is not necessary to divide the diffusion layer in two MOS units, and the well isolation region is also unnecessary. However, when writing data to the memory cell, in order to apply a high voltage of, for example, 17V to the word line via the NMOS, a higher voltage, for example, a voltage of about 20V is required at the gate of the NMOS, There is a problem that the MOS has no withstand voltage. Moreover, the area of the internal power supply circuit for generating a high voltage of 20 V increases.

As a method of reducing the write voltage, there is a method using hot electron injection. However, writing by hot electron injection requires a large amount of current, which limits parallel operation. As a result, the writing time increases.

In view of the above, the present invention solves the above-mentioned problems and enables parallel operation so that the write operation speed is fast and the layout of the decoder circuit is adapted to the miniaturization of memory cells. Is intended to provide. That is, an object of the present invention is to provide a non-volatile semiconductor memory device that can simultaneously achieve high-speed operation and reduction in chip area.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0016]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

In order to achieve the above object, the present invention uses hot electron injection, which is disclosed in Japanese Patent Laid-Open No. 2001-28428, which can reduce the operating voltage at the time of writing, and the amount of current at the time of writing. Reducible memory cell (first conductivity type well formed on the main surface of the semiconductor substrate and second well formed in the well extending in the first direction)
A conductive type semiconductor region, a first gate formed on the semiconductor substrate via a first insulating film, a second gate formed on the first gate via a second insulating film, 1
A third gate formed through a third insulating film, the third gate is formed to extend in the first direction, and is embedded in a gap between the first gates. A non-volatile semiconductor memory device having a plurality of memory cells, a word line connected to the memory cells, and a sub-decoder circuit for driving the word lines. All the sub-decoder elements forming the decoder circuit are NMOS or PMOS
It is characterized by being composed of.

That is, the nonvolatile semiconductor memory device of the present invention selectively drives a sub-decoder circuit including a plurality of sub-decoder elements having a function of selectively driving a word line and a source signal of the sub-decoder element. In a configuration having a block decoder circuit having a function to perform and a gate decoder circuit having a function to selectively drive the gate signal of the sub-decoder element, the following features are provided.

(1) Each of the plurality of sub-decoder elements includes a first N-channel MOS transistor and a second N-channel MOS transistor.
Two N-channel type M of channel type MOS transistors
Drains of the first N-channel MOS transistor and the second N-channel MOS transistor are connected to the same word line, and a gate signal and a source signal of the first N-channel MOS transistor are formed. The gate signal and the source signal of the second N-channel type MOS transistor are independently controlled.

(2) In (1) above, all the well substrates of the sub-decoder elements are source signals of the first N-channel type MOS transistor and the second N-channel type MOS transistor which are the sub-decoder elements. Of these, it is connected to the source signal on the low voltage side.

(3) In (1), the source signals of the sub-decoder elements driving the word lines share the diffusion layer with the same source signals of the adjacent sub-decoder elements.

(4) In (1), the gate of the sub-decoder element is arranged in the same direction as the word line. Alternatively, it is arranged in a direction perpendicular to the word line.

(5) Each of the plurality of sub-decoder elements includes a first P-channel MOS transistor and a second P-channel MOS transistor.
Two P-channel type M of channel type MOS transistors
Drains of the first P-channel MOS transistor and the second P-channel MOS transistor are connected to the same word line, and a gate signal and a source signal of the first P-channel MOS transistor are formed. The gate signal and the source signal of the second P-channel MOS transistor are independently controlled.

(6) In (5), all the well substrates of the sub-decoder elements are source signals of the first P-channel type MOS transistor and the second P-channel type MOS transistor which are the sub-decoder elements. Of these, it is connected to the source signal on the high voltage side.

(7) In (5), the source signals of the sub-decoder elements that drive the word lines share the diffusion layer between the same source signals of the adjacent sub-decoder elements.

(8) In (5), the gate of the sub-decoder element is arranged in the same direction as the word line. Alternatively, it is arranged in a direction perpendicular to the word line.

(9) In the above (1) to (8), further, a well of the first conductivity type formed in the semiconductor substrate,
A second conductivity type semiconductor region formed in the well,
A local source line / local bit line formed by connecting the semiconductor regions, a selection MOS transistor for selecting the local source line / local bit line, and a first insulating film formed on the semiconductor substrate via a first insulating film. A first gate, a second gate formed via the first gate and a second insulating film, a word line formed by connecting the second gate, a first gate and a third insulating film. And a third gate having a function different from that of the first gate and the second gate, which is formed through the memory cell block on the local source line and the local bit line separated by the selection MOS transistor. The memory cell blocks are arranged in the word line direction to form a memory cell array, and the binding portion of the third gate is connected to the memory cell block. A word line existing at the nearest position to said select MOS transistor in the click, the selection MOS
The present invention is applied to a non-volatile semiconductor memory device existing between the gate of a transistor.

(10) In the above (1) to (8), a well of the first conductivity type formed in a semiconductor substrate, a semiconductor region of the second conductivity type formed in the well, and A local source line and a local bit line formed by connecting semiconductor regions, a selection MOS transistor for selecting the local source line and the local bit line, and a first insulating film formed on the semiconductor substrate via a first insulating film. A local gate having one gate, a second gate formed through the first gate and a second insulating film, and a word line formed by connecting the second gate, and separated by the selection MOS transistor. A memory cell block is composed of the memory cells on the source line and the local bit line,
The present invention is applied to a nonvolatile semiconductor memory device in which the memory cell blocks are arranged in the word line direction to form a memory cell array.

[0029]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. In all the drawings for explaining the embodiments, members having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

(Embodiment 1) FIG. 1 is a schematic diagram of a configuration around a memory array showing an example of a nonvolatile semiconductor memory device according to Embodiment 1 of the present invention. Here, the numbers of word lines, global bit lines, and blocks are omitted for simplification of description. In the figure, the points different from the base technology of the present invention are the first embodiment of the present invention.
Since the memory cell having the auxiliary gate disclosed in Japanese Patent Laid-Open No. 2001-28428 is used, the block decoder section is provided with the auxiliary gate decoder. In the figure, the periphery of the memory array is composed of a block decoder / auxiliary gate decoder 10, a sub decoder 20, a gate decoder 30, a selection MOS transistor 40, a sense amplifier 50, a memory cell sub array 60, and the like. In addition, ST0ES, ST0OS, ST0ED, ST
0OD, ST1ES, ST1OS, ST1ED, ST1
OD is the gate signal of the selection MOS transistor, AG0
E, AG0O, AG1E and AG1O are auxiliary gate signals,
B0H, B0L, B1H and B1L are source signals of sub-decoder elements, W00 to W0m and W10 to W1m are word lines, DL0 to DL2 are global bit lines, and SL0 is a global source line. As shown in the figure, the word decoder circuit has a block decoder for selecting a block and a gate decoder and a gate decoder for selecting a specific word line in the selected block in the same manner as the precondition technique of the present invention in order to increase the speed. It is hierarchically divided into sub-decoders.

FIG. 2 is a configuration diagram of the periphery of the memory array showing an example of the nonvolatile semiconductor memory device according to the first embodiment of the present invention, and FIGS. 3 and 4 are circuit diagrams of memory cells. FIG. 5 is a schematic layout diagram of the sub-decoder section. In FIG. 2, the number of memory cells is partially omitted for simplicity of explanation. In FIG. 2, C000 to C030 in the sub-array are memory cells, W
00 to W0m and W10 to W1m are word lines, D00
And D01, S00 to S02, D10 and D11, S10
S12 is a local bit line or a local source line, each of which is wired by a diffusion layer. Also, DL0-D
L2 is a global bit line and SL0 is a global source line, both of which are metal wirings. The local bit line or local source line is connected to the global bit line and the global source line via a block selection MOS transistor (hereinafter referred to as a selection transistor). There is one global bit line for every two local bit lines. As a result, the wiring pitch of the global bit lines can be doubled, and it becomes possible to cope with the miniaturization of memory cells. ST0ES, ST0
OS, ST0ED, ST0OD, ST1ES, ST1O
S, ST1ED and ST1OD are gate signals of the selection transistor. The sub-decoder that drives the word line is 1
It is composed of two NMOS sub-decoder elements for one word line. B0H and B1H are source signals for applying a high potential to the word line. Also, B0
L and B1L are source signals for giving a low potential to the word line. G0H to GmH, G0L to GmL, G1H
.About.GmH and G1L to GmL are gate signals of the sub-decoder, which are signals generated from the address buffer to selectively apply a voltage to the word line. AG0E, AG0
O, AG1E, AG1O are signals applied to the auxiliary gates of the memory cells. The memory cell has a so-called virtual ground type structure in which the local drain line and the local source line of the memory cells adjacent to each other on the same word line are shared with each other, and as shown in FIGS. It has an auxiliary gate in addition to a control gate and a floating gate.

Table 1 shows an example of the operating voltage, and each operation will be described.

[0033]

[Table 1]

First, the write operation will be described. The write operation is performed by injecting hot electrons into the floating gate. In FIG. 2, it is assumed that the memory cells C000 and C020 are selected memory cells. For example, B0H = 12V, B0L = 0V, B1H = 0V,
B1L = 0V. At this time, G0H = 17V, G0L
= 0V, G1H to GmH = 0V, G1L to GmL = 17
By setting V, the selected word line W00 = 12V and the unselected word lines W01 to W of the selected block (block 0)
0m = 0V, and the word lines W11 to W1m of the non-selected block (block 1) become 0V. Also, AG0E = 2V,
By setting AG0O = AG1E = AG1O = 0V, the voltage of 2V is applied only to the auxiliary gates of the selected memory cells C000 and C020. Also, DL0 to DL2 =
5V, SL0 = 0V, ST0ES = ST0ED = 1
By setting 0V, ST0OS = ST0OD = 0V, D00 = D01 = 5V, S00 = S01 = S02 =
It becomes 0V. Also, ST1ES = ST1ED = ST1O
By setting S = ST1OD = 0V, D10 = D1
1 = S10 = S11 = S12 = floating. By the above operation, the memory cells C000 and C020
Only those are selected, and programming by hot electron injection is performed. At this time, the memory cells C010 and C030 are also applied with the write selection voltage for the word and the source.
Writing is not performed because the voltage of the auxiliary gate is 0V. Thus, in this embodiment, writing is performed by applying a positive high voltage to the control gate and drain of the memory cell and injecting hot electrons into the floating gate. At this time, by setting the voltage of the auxiliary gate to an appropriate voltage, the amount of current flowing at the time of writing is suppressed, and parallel operation equivalent to the writing operation by the FN tunnel phenomenon is enabled. As described above, the auxiliary gate in the write operation has a role of electrically disconnecting adjacent memory cells on the same word line and a role of suppressing the amount of current flowing at the time of writing.

Next, the erase operation will be described. The erasing operation is performed by emitting electrons from the floating gate to the substrate by utilizing the FN tunnel phenomenon as in the precondition technique of the present invention. In FIG. 2, it is assumed that the memory cells C000 to C030 existing on the word line W00 are selected memory cells. For example, B0H = 0V, B0L = -16V,
It is assumed that B1H = 0V and B1L = 0V. At this time, G0H =
-16V, G0L = 0V, G1H to GmH = 0V, G1
By setting L to GmL = -16V, the selected word line W00 = -16V, the non-selected word lines W01 to W0m = floating of the selected block (block 0), and the word lines W11 to W1m of the non-selected block (block 1) = f
It becomes loading. Also, AG0E = AG0O = A
G1E = AG1O = 0V. Also, DL0 to DL2
= 2V, SL0 = 2V, ST0ES = ST0ED =
By setting ST0OS = ST0OD = 10V, D
00 = D01 = S00 = S01 = S02 = 2V.
Also, ST1ES = ST1ED = ST1OS = ST1O
By setting D = 0V, D10 = D11 = S10 =
S11 = S12 = floating. By the above operation, the memory cell C00 existing on the word line W00
0 to C030 is selected, and erasing is performed by the FN tunnel phenomenon. In the above operation, G0L = 3V,
By setting G1H to GmH = 3V, it is possible to set all the voltages of the non-selected word lines to 0V.

Next, the read operation will be described. The read operation is performed by verifying the state of the drain voltage as in the precondition technique of the present invention. In FIG. 2, it is assumed that the memory cell of C000 is the selected memory cell. For example, B0H
= 3V, B0L = 0V, B1H = 0V, B1L = 0V. At this time, G0H = 7V, G0L = 0V, G1H
By setting GmH = 0V and G1L to GmL = 7V, the selected word line W00 = 3V, the unselected word lines W01 to W0m = 0V of the selected block (block 0), and the word lines W11 to W11 of the unselected block (block 1). W1m = 0
It becomes V. Also, AG0E = 3V, AG0O = AG1E
= AG1O = 0V, the selected memory cell C
The voltage of 3V is applied only to the auxiliary gates of 000 and C020. Also, DL0 = 1V, DL1 = DL2 = 0V,
SL0 = 0V, ST0ES = ST0ED = 10V,
By setting ST0OS = ST0OD = 0V, D0
0 = 1V, D01 = 0V, S00 = S01 = S02 = 0
It becomes V. Also, ST1ES = ST1ED = ST1OS
= ST1OD = 0V, D10 = D11
= S10 = S11 = S12 = floating.
By the above operation, only the memory cell C000 is selected and the reading is performed. At this time, the read selection voltage is applied to the word and source in the memory cell C010 as well.
Reading is not performed because the voltage of the auxiliary gate is 0V. In this way, the auxiliary gate in the read operation plays a role of electrically disconnecting adjacent memory cells on the same word line.

FIG. 5 shows the outline of the layout of the sub-decoder for realizing the above operation.
In the present embodiment, since the sub-decoder element is composed of only NMOS, the well isolation region for separating PMOS and NMOS, which is required when the inverter of the preparatory technique of the present invention is configured, is unnecessary. In addition, in the inverter configuration of the base technology of the present invention, two Ms are provided on the circuit configuration as shown in FIG.
Although it was necessary to divide the diffusion layer in each OS, it is not necessary to divide the diffusion layer in two MOS units in this embodiment. Furthermore, considering drive capability, NM is better than PMOS.
Since the OS can make the constant smaller, the present embodiment is also effective in this respect.

In summary, the following effects can be obtained in this embodiment. The write operation voltage is reduced by using the N-channel type memory cell having a virtual ground type structure and an auxiliary gate in addition to the control gate and the floating gate of the premise technique of the present invention to perform writing by hot electron injection. Further, it is possible to realize a parallel operation similar to the write operation by the FN tunnel phenomenon. In this way, the write operation voltage, which becomes a positive high voltage, can be reduced, so that the element of the sub-decoder that drives the word line is NM.
It is possible to configure with only the OS, and the layout area can be reduced. That is, it is possible to realize a nonvolatile semiconductor memory device that operates at high speed and has a small chip area.

(Embodiment 2) FIG. 1 is a schematic configuration diagram of the periphery of a memory array showing an example of a nonvolatile semiconductor memory device according to Embodiment 2 of the present invention, which is the same as that of Embodiment 1. Therefore, the description is omitted. The present embodiment is an embodiment in which the N-channel MOS memory cell described in the first embodiment is replaced with a P-channel MOS memory cell. The effect on the layout area is similar to that of the first embodiment, and only the operating voltage is different. Therefore, the description of the layout area is omitted here, and only the operating voltage is described.

FIG. 6 is a configuration diagram of the periphery of the memory array showing an example of the nonvolatile semiconductor memory device according to the second embodiment of the present invention, and FIGS. 7 and 8 are circuit diagrams of the memory cells. Table 2 is a table showing examples of operating voltages. As described above, the point different from the first embodiment is that the memory cell is a P-channel type MOS. Along with this, the select transistors arranged in the same region as the memory cell array are also PMOS. Since the signal names of the respective parts are the same as those in the first embodiment, the description thereof will be omitted.

[0041]

[Table 2]

First, the write operation will be described. The write operation is performed by injecting hot holes into the floating gate. In FIG. 6, C000 and C02
Assume that the memory cell of 0 is the selected memory cell. For example,
B0H = 0V, B0L = -12V, B1H = 0V, B1
Let L = 0V. At this time, G0H = -12V, G0L =
3V, G1H to GmH = 3V, G1L to GmL = -12
By setting V, the selected word line W00 = −12V,
Non-selected word line W01 of selected block (block 0)
W0m = 0V and the word lines W11 to W1m = 0V of the non-selected block (block 1). Also, AG0E = -2
By setting V and AG0O = AG1E = AG1O = 0V, the voltage of −2V is applied only to the auxiliary gates of the selected memory cells C000 and C020. Also, DL0-DL
2 = -5V, SL0 = 0V, ST0ES = ST0E
By setting D = -10V and ST0OS = ST0OD = 0V, D00 = D01 = -5V, S00 = S01 =
S02 = 0V. Also, ST1ES = ST1ED =
By setting ST1OS = ST1OD = 0V, D1
0 = D11 = S10 = S11 = S12 = floatin
It becomes g. By the above operation, the memory cells C000 and C
Only 020 is selected and writing is performed by hot hole injection. At this time, the memory cells C010 and C030 are also applied with the write selection voltage for the word and the source.
Writing is not performed because the voltage of the auxiliary gate is 0V. As described above, in this embodiment, writing is performed by applying a negative high voltage to the control gate and drain of the memory cell and injecting hot holes into the floating gate. At this time, by setting the voltage of the auxiliary gate to an appropriate voltage, the amount of current flowing at the time of writing is suppressed, and parallel operation equivalent to the writing operation by the FN tunnel phenomenon is enabled. As described above, the auxiliary gate in the write operation has a role of electrically disconnecting adjacent memory cells on the same word line,
It plays the role of suppressing the amount of current flowing during writing. As shown in Table 2, in this embodiment, the withstand voltage of the MOS transistor required for the sub-decoder element at the time of writing can be further lowered as compared with the first embodiment.

Next, the erase operation will be described. The erasing operation is performed by using the FN tunnel phenomenon as in the base technology of the present invention. However, since the memory cell is a P-channel type MOS, the polarities of the voltages are reversed. Therefore, the FN tunnel phenomenon is used to discharge holes from the floating gate to the substrate. In FIG. 6, it is assumed that the memory cells C000 to C030 existing on the word line W00 are selected memory cells. For example, B0H = 16V, B0L = 0
It is assumed that V, B1H = 0V, and B1L = 0V. At this time, G0
H = 19V, G0L = 0V, G1H to GmH = 0V, G
By setting 1L to GmL = 19V, the selected word line W00 = 16V, the unselected word lines W01 to W0m = 0V of the selected block (block 0), and the word lines W11 to W1m = 0V of the unselected block (block 1). Become. Further, it is assumed that AG0E = AG0O = AG1E = AG1O = 0V. Also, DL0 to DL2 = -2V, SL0 = -2V
And ST0ES = ST0ED = ST0OS = ST0O
By setting D = -10V, D00 = D01 = S0
0 = S01 = S02 = −2V. Also, ST1ES
= ST1ED = ST1OS = ST1OD = 0V, so that D10 = D11 = S10 = S11 = S12 =
It will be floating. By the above operation, the memory cells C000 to C030 existing on the word line W00 are selected and erased by the FN tunnel phenomenon. As shown in Table 2, in the present embodiment, all the voltages of the non-selected word lines at the time of erasing can be set to 0V.

Next, the read operation will be described. The read operation is performed by verifying the state of the drain voltage as in the precondition technique of the present invention. In FIG. 6, it is assumed that the memory cell of C000 is the selected memory cell. For example, B0H
= 0V, B0L = -3V, B1H = 0V, B1L = 0V
And At this time, G0H = −3V, G0L = 3V, G1
By setting H to GmH = 3V and G1L to GmL = -3V, the selected word line W00 = -3V and the unselected word lines W01 to W0m = 0 of the selected block (block 0).
V, word lines W11 to W11 of the non-selected block (block 1)
W1m = 0V. Also, AG0E = −3V, AG0
By setting O = AG1E = AG1O = 0V, only the auxiliary gates of the selected memory cells C000 and C020 are -3.
A voltage of V is applied. Also, DL0 = -1V, DL1
= DL2 = 0V, SL0 = 0V, ST0ES = ST
By setting 0ED = -10V and ST0OS = ST0OD = 0V, D00 = -1V, D01 = 0V, S00
= S01 = S02 = 0V. Also, ST1ES = S
By setting T1ED = ST1OS = ST1OD = 0V, D10 = D11 = S10 = S11 = S12 = fl
It becomes oating. By the above operation, the memory cell C
Only 000 are selected and read. At this time, the read selection voltage is applied to the word and the source also in the memory cell C010, but the reading is not performed because the voltage of the auxiliary gate is 0V. In this way, the auxiliary gate in the read operation plays a role of electrically disconnecting adjacent memory cells on the same word line.

As described above, the effect on the layout area in this embodiment is the same as that in the first embodiment.

In summary, the following effects can be obtained in this embodiment. A virtual ground type structure is used, and a P-channel type memory cell having an auxiliary gate in addition to a control gate and a floating gate according to the premise technique of the present invention is used to perform writing by hot hole injection, so that the write operation voltage is negative. It is possible to set the voltage, and it is possible to realize a parallel operation similar to the write operation by the FN tunnel phenomenon. As described above, since the write operation voltage can be set to a negative voltage, the element of the sub-decoder that drives the word line is NMOS.
The layout area can be reduced because it can be configured with only. That is, it is possible to realize a nonvolatile semiconductor memory device that operates at high speed and has a small chip area. Also,
As described above, in this embodiment, the withstand voltage of the MOS transistor required for the sub-decoder element at the time of writing can be further lowered as compared with the first embodiment. Further, all the voltages of the non-selected word lines at the time of erasing can be set to 0V.

(Embodiment 3) FIG. 1 is a schematic diagram of the configuration around a memory array showing an example of a nonvolatile semiconductor memory device according to Embodiment 3 of the present invention, which is the same as that of Embodiment 1 above. Therefore, the description is omitted. This embodiment is an embodiment in which the sub-decoder element described in the first embodiment is configured by a PMOS. PM sub-decoder element
Since it is composed of the OS, it is necessary to design the MOS constant to be slightly larger, but the effect on the layout area is almost the same as that of the first embodiment, and only the operating voltage is different. Therefore,
Here, description of the layout area is omitted, and only the operating voltage will be described.

FIG. 9 is a configuration diagram of the periphery of the memory array showing an example of the nonvolatile semiconductor memory device according to the third embodiment of the present invention, and the circuit diagram of the memory cell is the same as that of the first embodiment, as shown in FIG. And the memory cell of FIG. Table 3 is a table showing examples of operating voltages. As described above, the point different from the first embodiment is that the sub-decoder element is composed of PMOS. Since the signal names of the respective parts are the same as those in the first embodiment, the description thereof will be omitted.

[0049]

[Table 3]

First, the write operation will be described. The write operation is performed by injecting hot electrons into the floating gate. In FIG. 9, it is assumed that the memory cells C000 and C020 are selected memory cells. For example, B0H = 12V, B0L = 0V, B1H = 0V,
B1L = 0V. At this time, G0H = -3V, G0L
= 12V, G1H to GmH = 12V, G1L to GmL =
By setting -3V, the selected word line W00 = 12
V, unselected word line W0 of selected block (block 0)
1 to W0m = 0V, and the word lines W11 to W1m of the non-selected block (block 1) become 0V. Also, AG0E =
By setting 2V and AG0O = AG1E = AG1O = 0V, the voltage of 2V is applied only to the auxiliary gates of the selected memory cells C000 and C020. Also, DL0-DL
2 = 5V, SL0 = 0V, ST0ES = ST0ED
= 10V, ST0OS = ST0OD = 0V, D00 = D01 = 5V, S00 = S01 = S02
= 0V. Also, ST1ES = ST1ED = ST1
By setting OS = ST1OD = 0V, D10 = D
11 = S10 = S11 = S12 = floating. By the above operation, the memory cells C000 and C020
Only those are selected, and programming by hot electron injection is performed. At this time, the memory cells C010 and C030 are also applied with the write selection voltage for the word and the source.
Writing is not performed because the voltage of the auxiliary gate is 0V. Thus, in this embodiment, writing is performed by applying a positive high voltage to the control gate and drain of the memory cell and injecting hot electrons into the floating gate. At this time, by setting the voltage of the auxiliary gate to an appropriate voltage, the amount of current flowing at the time of writing is suppressed, and parallel operation equivalent to the writing operation by the FN tunnel phenomenon is enabled. As described above, the auxiliary gate in the write operation has a role of electrically disconnecting adjacent memory cells on the same word line and a role of suppressing the amount of current flowing at the time of writing. As shown in Table 3, in this embodiment, the breakdown voltage of the MOS transistor required for the sub-decoder element at the time of writing can be further lowered as compared with the first embodiment.

Next, the erase operation will be described. The erasing operation is performed by emitting electrons from the floating gate to the substrate by utilizing the FN tunnel phenomenon as in the precondition technique of the present invention. In FIG. 9, it is assumed that the memory cells C000 to C030 existing on the word line W00 are selected memory cells. For example, B0H = 0V, B0L = -16V,
It is assumed that B1H = 0V and B1L = 0V. At this time, G0H =
0V, G0L = -19V, G1H to GmH = -19V,
By setting G1L to GmL = 0V, the selected word line W00 = −16V, the unselected word lines W01 to W0m = 0V of the selected block (block 0), and the word lines W11 to W1m = 0V of the unselected block (block 1). Becomes Further, it is assumed that AG0E = AG0O = AG1E = AG1O = 0V. Also, DL0 to DL2 = 2V and SL0 = 2V, and ST0ES = ST0ED = ST0OS = ST0OD.
= 10V, D00 = D01 = S00 =
S01 = S02 = 2V. Also, ST1ES = ST
By setting 1ED = ST1OS = ST1OD = 0V, D10 = D11 = S10 = S11 = S12 = flo
becoming. By the above operation, the word line W00
The memory cells C000 to C030 existing above are selected and erased by the FN tunnel phenomenon. As shown in Table 3, in the present embodiment, all the voltages of the non-selected word lines at the time of erasing can be set to 0V.

Next, the read operation will be described. The read operation is performed by verifying the state of the drain voltage as in the precondition technique of the present invention. In FIG. 9, it is assumed that the memory cell of C000 is the selected memory cell. For example, B0H
= 3V, B0L = 0V, B1H = 0V, B1L = 0V. At this time, G0H = −3V, G0L = 3V, G1H
-GmH = 3V, G1L-GmL = -3V, the selected word line W00 = 3V, the unselected word lines W01 to W0m = 0V of the selected block (block 0), and the word line of the unselected block (block 1) W11-W1m =
It becomes 0V. Also, AG0E = 3V, AG0O = AG1
By setting E = AG1O = 0V, the voltage of 3V is applied only to the auxiliary gates of the selected memory cells C000 and C020. Also, DL0 = 1V, DL1 = DL2 = 0
V, SL0 = 0V, ST0ES = ST0ED = 10
By setting V, ST0OS = ST0OD = 0V,
D00 = 1V, D01 = 0V, S00 = S01 = S02
= 0V. Also, ST1ES = ST1ED = ST1
By setting OS = ST1OD = 0V, D10 = D
11 = S10 = S11 = S12 = floating. By the above operation, only the memory cell C000 is selected and the reading is performed. At this time, the memory cell C010
Also, the read selection voltage is applied to the word and the source, but the read is not performed because the auxiliary gate voltage is 0V. In this way, the auxiliary gate in the read operation plays a role of electrically disconnecting adjacent memory cells on the same word line.

As described above, since the sub-decoder element is composed of the PMOS in this embodiment, it is necessary to design the MOS constant a little larger, but the effect on the layout area is almost the same as that of the first embodiment. Is.

In summary, the following effects can be obtained in this embodiment. The write operation voltage is reduced by using the N-channel type memory cell having a virtual ground type structure and an auxiliary gate in addition to the control gate and the floating gate of the premise technique of the present invention to perform writing by hot electron injection. Further, it is possible to realize a parallel operation similar to the write operation by the FN tunnel phenomenon. In this way, the write operation voltage, which is a positive high voltage, can be reduced, so that the element of the sub-decoder that drives the word line is PM
It is possible to configure with only the OS, and the layout area can be reduced. That is, it is possible to realize a nonvolatile semiconductor memory device that operates at high speed and has a small chip area. Further, as described above, in this embodiment, the breakdown voltage of the MOS transistor required for the sub-decoder element at the time of writing can be further lowered as compared with the first embodiment. Further, all the voltages of the non-selected word lines at the time of erasing can be set to 0V.

(Embodiment 4) FIG. 1 is a schematic configuration diagram of the periphery of a memory array showing an example of a nonvolatile semiconductor memory device according to Embodiment 4 of the present invention, which is the same as that of Embodiment 1. Therefore, the description is omitted. In this embodiment, the N-channel MOS memory cell described in the first embodiment is changed to a P-channel MOS memory cell, and the sub-decoder element described in the first embodiment is formed by a PMOS. It is an embodiment. Sub decoder element is PMO
Since it is composed of S, it is necessary to design the MOS constant to be slightly larger, but the effect on the layout area is the same as that of the first embodiment.
Is almost the same as the above, and only the operating voltage is different. Therefore, the description of the layout area is omitted here, and only the operating voltage is described.

FIG. 10 is a configuration diagram of the periphery of the memory array showing an example of the non-volatile semiconductor memory device according to the fourth embodiment of the present invention, and the circuit diagram of the memory cell is similar to that of the second embodiment. And the memory cell shown in FIG. Also, Table 4
Is a table showing examples of operating voltages. As described above, the difference from the first embodiment is that the memory cell is a P channel type MO
It is S and that the sub-decoder element is composed of PMOS. Since the memory cell is the P-channel type MOS, the select transistor arranged in the same region as the memory cell array is also the PMOS. Since the signal names of the respective parts are the same as those in the first embodiment, the description thereof will be omitted.

[0057]

[Table 4]

First, the write operation will be described. The write operation is performed by injecting hot holes into the floating gate. In FIG. 10, C000 and C0
Assume that 20 memory cells are selected memory cells. For example, B0H = 0V, B0L = -12V, B1H = 0V,
B1L = 0V. At this time, G0H = -15V, G0
L = 0V, G1H to GmH = 0V, G1L to GmL =-
By setting the voltage to 15 V, the selected word line W00 = −12
V, unselected word line W0 of selected block (block 0)
1 to W0m = 0V, and the word lines W11 to W1m of the non-selected block (block 1) become 0V. Also, AG0E =
By setting -2V and AG0O = AG1E = AG1O = 0V, the voltage of -2V is applied only to the auxiliary gates of the selected memory cells C000 and C020. Also, DL0
DL2 = -5V, SL0 = 0V, ST0ES = ST
By setting 0ED = -10V and ST0OS = ST0OD = 0V, D00 = D01 = -5V, S00 = S0
1 = S02 = 0V. Also, ST1ES = ST1E
By setting D = ST1OS = ST1OD = 0V,
D10 = D11 = S10 = S11 = S12 = float
It will be ing. By the above operation, the memory cell C000
And C020 are selected, and writing is performed by hot hole injection. At this time, memory cells C010 and C03
A write selection voltage is applied to the word and the source at 0, but writing is not performed because the voltage of the auxiliary gate is 0V. As described above, in this embodiment, writing is performed by applying a negative high voltage to the control gate and drain of the memory cell and injecting hot holes into the floating gate. At this time, by setting the voltage of the auxiliary gate to an appropriate voltage, the amount of current flowing at the time of writing is suppressed, and parallel operation equivalent to the writing operation by the FN tunnel phenomenon is enabled. As described above, the auxiliary gate in the write operation has a role of electrically disconnecting adjacent memory cells on the same word line and a role of suppressing the amount of current flowing at the time of writing.
As shown in Table 4, in this embodiment, the withstand voltage of the MOS transistor required for the sub-decoder element at the time of writing can be further lowered as compared with the first embodiment.

Next, the erase operation will be described. The erasing operation is performed by using the FN tunnel phenomenon as in the base technology of the present invention. However, since the memory cell is a P-channel type MOS, the polarities of the voltages are reversed. Therefore, the FN tunnel phenomenon is used to discharge holes from the floating gate to the substrate. In FIG. 10, it is assumed that the memory cells C000 to C030 existing on the word line W00 are selected memory cells. For example, B0H = 16V, B0L =
It is assumed that 0V, B1H = 0V, and B1L = 0V. At this time, G
0H = 0V, G0L = 16V, G1H to GmH = 16
By setting V and G1L to GmL = 0V, the selected word line W00 = 16V, the unselected word lines W01 to W0m = floating of the selected block (block 0), and the word lines W11 to W1m of the unselected block (block 1) =
It will be floating. Also, AG0E = AG0O =
AG1E = AG1O = 0V. Also, DL0-DL
2 = -2V, SL0 = -2V, ST0ES = ST0
By setting ED = ST0OS = ST0OD = -10V, D00 = D01 = S00 = S01 = S02 = -2
It becomes V. Also, ST1ES = ST1ED = ST1OS
= ST1OD = 0V, D10 = D11
= S10 = S11 = S12 = floating.
By the above operation, the memory cells C000 to C030 existing on the word line W00 are selected and erased by the FN tunnel phenomenon. In the above operation, G0
By setting H = 3V and G1L to GmL = 3V, it is possible to set all the voltages of the non-selected word lines to 0V.

Next, the read operation will be described. The read operation is performed by verifying the state of the drain voltage as in the precondition technique of the present invention. In FIG. 10, it is assumed that the memory cell of C000 is the selected memory cell. For example, B0
H = 0V, B0L = -3V, B1H = 0V, B1L = 0
V. At this time, G0H = 0V, G0L = -6V, G
By setting 1H to GmH = −6V and G1L to GmL = 0V, the selected word line W00 = −3V and the unselected word lines W01 to W0m = 0 of the selected block (block 0).
V, word lines W11 to W11 of the non-selected block (block 1)
W1m = 0V. Also, AG0E = −3V, AG0
By setting O = AG1E = AG1O = 0V, only the auxiliary gates of the selected memory cells C000 and C020 are -3.
A voltage of V is applied. Also, DL0 = -1V, DL1
= DL2 = 0V, SL0 = 0V, ST0ES = ST
By setting 0ED = -10V and ST0OS = ST0OD = 0V, D00 = -1V, D01 = 0V, S00
= S01 = S02 = 0V. Also, ST1ES = S
By setting T1ED = ST1OS = ST1OD = 0V, D10 = D11 = S10 = S11 = S12 = fl
It becomes oating. By the above operation, the memory cell C
Only 000 are selected and read. At this time, the read selection voltage is applied to the word and the source also in the memory cell C010, but the reading is not performed because the voltage of the auxiliary gate is 0V. In this way, the auxiliary gate in the read operation plays a role of electrically disconnecting adjacent memory cells on the same word line.

As described above, since the sub-decoder element is composed of the PMOS in this embodiment, it is necessary to design the MOS constant a little larger, but the effect on the layout area is almost the same as that of the first embodiment. Is.

In summary, the following effects can be obtained in this embodiment. A virtual ground type structure is used, and a P-channel type memory cell having an auxiliary gate in addition to a control gate and a floating gate according to the premise technique of the present invention is used to perform writing by hot hole injection, so that the write operation voltage is negative. It is possible to set the voltage, and it is possible to realize a parallel operation similar to the write operation by the FN tunnel phenomenon. As described above, since the write operation voltage can be a negative voltage, the element of the sub-decoder that drives the word line is PMOS.
The layout area can be reduced because it can be configured with only. That is, it is possible to realize a nonvolatile semiconductor memory device that operates at high speed and has a small chip area. Also,
As described above, in this embodiment, the withstand voltage of the MOS transistor required for the sub-decoder element at the time of writing can be further lowered as compared with the first embodiment.

(Fifth Embodiment) FIG. 11 shows a computer system in which the nonvolatile semiconductor memory device according to the first to fourth embodiments is incorporated in the fifth embodiment of the present invention. This system has a system bus. It is composed of a host CPU, an input / output device, a RAM, and a memory card, which are connected to each other via a host CPU.

The memory card includes, for example, a flash EEPROM (flash memory) having a large capacity of several tens of gigabytes as a replacement of a hard disk storage device.
Since the flash memory according to the embodiment of the present invention enjoys the advantages of high-speed operation and small chip area, it has sufficient industrial advantages as a storage device as a final product.

The present invention is not limited to a memory card having a relatively small thickness, and even when the thickness is relatively large, the interface with the host bus system and the command of the host system are analyzed. It goes without saying that the present invention can be applied to any nonvolatile semiconductor memory device including an intelligent controller capable of controlling a flash memory.

Data stored for a long period of time is stored in this non-volatile storage device, while data that is processed by the host CPU and frequently changed is RA of the volatile memory.
Stored in M.

The memory card has a system bus interface connected to the system bus, and enables a standard bus interface such as the ATA system bus. The controller connected to the system bus interface receives commands and data from the host CPU or input / output device host system connected to the system bus.

If the command is a read command, the controller accesses the required one or more flash EEPROMs and transfers the read data to the host system.

If the command is a write command, the controller accesses the required one or more of the flash EEPROMs and stores the write data from the host system therein. This storing operation includes a program operation and a verify operation for a necessary block, sector or memory cell of the flash memory.

If the command is an erase command, the controller accesses the required one or more of the flash EEPROMs to erase the data stored therein. This erase operation includes an erase operation and a verify operation for a necessary block, sector, or memory cell of the flash memory.

As described above, the invention made by the present inventor is
Although the specific description has been given based on the above-described embodiments, the present invention is not limited to the above-described embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention.

For example, the present invention may be applied to a one-chip microcomputer (semiconductor device) having a memory cell array section having a non-volatile semiconductor memory element.

Further, in any of the embodiments, at least two states of electrons or holes accumulated in the floating gate at the time of writing are required, but four or more states are formed to form one memory. It may be applied to so-called multi-valued storage, in which data of 2 bits or more is stored in a cell.

Further, in the embodiment of the present invention, Japanese Patent Laid-Open No.
The case where the hot electron injection is used in the memory cell having the virtual ground structure and having the third gate, which is disclosed in JP-A-01-28428, has been described as an example.
Any memory cell that can reduce the operating voltage can be applied even when the FN tunnel phenomenon is used, and it is not particularly limited to the memory cell.

Even if the operating voltage is high, it is applicable if the sub-decoder is composed of MOS transistors having withstand voltage.

There is no particular limitation on the structure of the selection transistor or the peripheral circuit.

Further, although the substrate voltage of the memory cell array has been described as 0V in the embodiment of the present invention, the voltage may be applied to the substrate of the memory cell array as in the erase operation of the precondition technique example of the present invention. .

[0078]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
It is as follows.

(1) It is possible to reduce the chip area of the nonvolatile semiconductor memory device.

(2) It is possible to improve the operating speed of the nonvolatile semiconductor memory device.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing a configuration around a memory array of a nonvolatile semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram showing the periphery of a memory array of the nonvolatile semiconductor memory device according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram showing a memory cell in the nonvolatile semiconductor memory device according to the first embodiment of the present invention.

FIG. 4 is a circuit diagram showing a memory cell in the nonvolatile semiconductor memory device according to the first embodiment of the present invention.

FIG. 5 is a layout schematic diagram showing a sub-decoder element in the nonvolatile semiconductor memory device according to the first embodiment of the present invention.

FIG. 6 is a configuration diagram showing the periphery of a memory array of a nonvolatile semiconductor memory device which is Embodiment 2 of the present invention.

FIG. 7 is a circuit diagram showing a memory cell in a nonvolatile semiconductor memory device which is Embodiment 2 of the present invention.

FIG. 8 is a circuit diagram showing a memory cell in a nonvolatile semiconductor memory device which is Embodiment 2 of the present invention.

FIG. 9 is a configuration diagram showing the periphery of a memory array of a nonvolatile semiconductor memory device which is Embodiment 3 of the present invention.

FIG. 10 is a configuration diagram showing the periphery of a memory array of a nonvolatile semiconductor memory device which is Embodiment 4 of the present invention.

FIG. 11 is a configuration diagram showing a computer system in which a nonvolatile semiconductor memory device according to any one of the first to fourth embodiments is incorporated in the fifth embodiment of the present invention.

FIG. 12 is a configuration diagram showing the periphery of a memory array of a nonvolatile semiconductor memory device examined as a premise of the present invention.

FIG. 13 is a circuit diagram showing a sub-decoder element in a nonvolatile semiconductor memory device examined as a premise of the present invention.

FIG. 14 is a schematic layout diagram showing a sub-decoder element in a nonvolatile semiconductor memory device examined as a premise of the present invention.

[Explanation of symbols]

10 Block Decoder / Auxiliary Gate Decoder 20 Sub Decoder 30 Gate Decoder 40 Select MOS Transistor 50 Sense Amplifier 60 Memory Cell Sub Array C000, C010, C020, C030, C00m,
C100, C10m memory cells W00, W01, W02, W03, W0m-1, W0
m, W10, W11, W12, W13, W1m-1,
W1m word lines D00, D01, S00, S01, S02, D10, D
11, S10, S11, S12 Local source line / local bit line S0, S1 Local source line D0, D1 Local bit line SL0 Global source line DL0, DL1, DL2 Global bit line ST0ES, ST0OS, ST0ED, ST0OD, S
T1ES, ST1OS, ST1ED, ST1OD, S0
S, S0D, S1S, S1D Select transistor gate signals B0H, B0L, B1H, B1L, B0P, B0N, B
Source signals G0H, G0L, G1H, G1L, G2H, G2L, G of 1P, B1N, BiP, BiN sub-decoders
m-1H, Gm-1L, GmH, GmL, G00, G0
1, G02, G03, G0m, Gij Sub-decoder gate signals AG0E, AG0O, AG1E, AG1O Auxiliary gate signals

Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 29/788 29/792 (72) Inventor Hideaki Kurata 1-280 Higashi Koigakubo, Kokubunji, Tokyo Metropolitan Research Center, Hitachi Ltd. (72) Inventor Naoki Kobayashi 1-280, Higashi Koigakubo, Kokubunji, Tokyo, Central Research Laboratory, Hitachi, Ltd. (72) Takayuki Kawahara 1-280, Higashi Koigakubo, Kokubunji, Tokyo F-Term, Hitachi Central Research Laboratory (reference) ) 5B025 AA03 AB01 AC01 AD00 AD02 AE00 AE05 5F083 EP02 EP22 EP30 ER02 ER09 ER19 ER22 ER29 ER30 GA01 GA09 KA06 KA12 LA04 LA05 LA12 ZA13 ZA14 5F101 BA01 BB02 BB09 BC11 BD02 BD31 BE21 BE05 BE07 BE07 BE05 BE07

Claims (5)

[Claims] 1. A sub-decoder circuit comprising a plurality of sub-decoder elements having a function of selectively driving a word line,
A block decoder circuit having a function of selectively driving a source signal of the sub-decoder element, and a gate decoder circuit having a function of selectively driving a gate signal of the sub-decoder element, the plurality of sub-decoders Each of the elements is composed of two N channel type MOS transistors, a first N channel type MOS transistor and a second N channel type MOS transistor, and the first N channel type MOS transistor and the second N channel type. Type MOS transistors have their drains connected to the same word line, and the gate signal and source signal of the first N-channel type MOS transistor and the gate signal and source signal of the second N-channel type MOS transistor are independently controlled. , All the well substrates of the sub-decoder element are the sub-decoder element. The first N-channel MOS transistor and the second N-channel MOS transistor
A nonvolatile semiconductor memory device characterized in that it is connected to a source signal on a low voltage side among source signals of a channel type MOS transistor. 2. A sub-decoder circuit comprising a plurality of sub-decoder elements having a function of selectively driving a word line,
A block decoder circuit having a function of selectively driving a source signal of the sub-decoder element, and a gate decoder circuit having a function of selectively driving a gate signal of the sub-decoder element, the plurality of sub-decoders Each of the elements is composed of two P-channel type MOS transistors, a first P-channel type MOS transistor and a second P-channel type MOS transistor, and the first P-channel type MOS transistor and the second P-channel type MOS transistor. The drains of the MOS transistors are connected to the same word line, and the gate signal and source signal of the first P-channel MOS transistor and the gate signal and source signal of the second P-channel MOS transistor are independently controlled. , All the well substrates of the sub-decoder element are the sub-decoder element. The first P-channel MOS transistor and the second P-channel MOS transistor
A nonvolatile semiconductor memory device, characterized in that it is connected to a source signal on a high voltage side among source signals of a channel type MOS transistor. 3. The non-volatile semiconductor memory device according to claim 1, wherein the source signals of the sub-decoder elements that drive the word lines share a diffusion layer between the same source signals of adjacent sub-decoder elements. The gate of the sub-decoder element is arranged in the same direction as the word line or in the vertical direction. 4. The non-volatile semiconductor memory device according to claim 1, wherein the well of the first conductivity type is formed in the semiconductor substrate and the well of the second conductivity type is formed in the well. A semiconductor region, a local source line / local bit line formed by connecting the semiconductor region, a selection MOS transistor for selecting the local source line / local bit line, and a first insulating film on the semiconductor substrate. Formed by the first gate, the second gate formed by interposing the first gate and the second insulating film, the word line formed by connecting the second gate, the first gate and the first gate On a local source line and a local bit line separated by the selection MOS transistor, the first gate and the second gate having a third gate different in function from each other. A memory cell block is formed of memory cells, the memory cell blocks are arranged in the word line direction to form a memory cell array, and the binding portion of the third gate is located closest to the selection MOS transistor in the memory cell block. A non-volatile semiconductor memory device characterized by being present between a word line existing at a close position and a gate of the selection MOS transistor. 5. The nonvolatile semiconductor memory device according to claim 1, 2 or 3, wherein a first conductivity type well formed in a semiconductor substrate and a second conductivity type well formed in the well. A semiconductor region, a local source line and a local bit line formed by connecting the semiconductor region, and a selection MOS transistor for selecting the local source line and the local bit line,
A first insulating film formed on the semiconductor substrate via a first insulating film;
A local source having a gate, a second gate formed through the first gate and a second insulating film, and a word line formed by connecting the second gate, and separated by the selection MOS transistor A non-volatile semiconductor memory device characterized in that a memory cell block is constituted by memory cells on a line and a local bit line, and the memory cell block is arranged in the word line direction to constitute a memory cell array.