JP2003133961A - Dequantizing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an inverse quantization circuit adapted to MPEG-4 and the like, which can bring decrease in power consumption and size reduction of a chip mounted on the inverse quantization circuit, by decreasing the number of wiring. SOLUTION: At a double increment unit 5, processing is conducted to determine an OR processed value for a section of the bit 11 and the bit 10 of |QF[i] (AC/DC quantization coefficient)| as the value of the bit 11 of an output A[i], a section from the bit 9 to the bit 0 of |QF[i]| as a section from the bit 10 to the bit 1 of the output A[i], and the bit 0 of the output A[i] as '1'.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to MPEG (Moving
Picture Experts Group) -4, etc.

MPEG-4 is ISO-IEC / JTC1 / SC29 / W
It was discussed at G11 and adopted as a standard draft,
The main focus is on moving image transmission at low bit rates, and there are expectations for moving image distribution for mobile phones and mobile terminals. Power consumption is essential.

[0003]

2. Description of the Related Art FIG. 6 shows a previously proposed MPEG-4.
It is a circuit diagram which shows an example of the inverse quantization circuit for decoders.
In FIG. 6, QF [i] is an AC / DC quantized coefficient (64 one-dimensional array), and Y0 is 64 and Y1 is 64.
Individual,. ． ． , Cr are 64 in order.

1 is an AC / DC quantized coefficient (QF [i])
A shift unit that doubles the absolute value of (| QF [i] |)
2 is an increment unit that processes the output of the shift unit 1 (2 × | QF [i] |) by 1 and 3 is the output of the increment unit 2 (2 × | QF [i] | +1) and the quantization scale (quan
tiser_scale) is input to perform the second dequantization process shown in Formula 1, and the absolute value (| F ″) of the intermediate variable (F ″ [i]) is input.
[I] |) is a multiplication unit that outputs.

[0005]

[Equation 1]

Reference numeral 4 denotes the sign (sign (Q) of the output (| F ″ [i] |) of the multiplication unit 3 and the AC / DC quantization coefficient (QF [i]).
F [i])) and input the inverse quantization coefficient (F '[i])
If the output (| F ″ [i] |) of the multiplication unit 3 is not saturated as the absolute value of (| F ′ [i] |), the output of the multiplication unit 3 (| F ″ [i] | ) Is output, and when the output (| F ″ [i] |) of the multiplication unit 3 is saturated in the positive direction, 2047 is output and the output of the multiplication unit 3 is output. The saturation processing unit outputs 2048 when (| F ″ [i] |) is saturated in the negative direction.

FIG. 7 shows a shift unit 1 and an increment unit 2.
6 is a diagram for explaining the operation of FIG. | QF [i] |
According to the MPEG-4 standard, the maximum is 2048, so
| QF [i] |₁₁X_Ten... X₀]₂If you write
The shift part 1 is [X₁₁X_Ten... X ₀]₂Shift 1 bit to the left
Process it [X₁₁X_Ten... X₀0]₂2 x
| QF [i] | is calculated. Therefore, the shift unit 1
The output is 13 bits.

Further, the increment unit 2 is composed of the shift unit 1
By incrementing [X ₁₁ X ₁₀ ... X ₀ 0] ₂ output from [X ₁₁ X ₁₀ ... X ₀ 1] to obtain (2
× | QF [i] | +1) is calculated. Therefore, the output of the increment unit 2 is also 13 bits.

The multiplication unit 3 multiplies the output (13 bits) of the increment unit 2 by the quantization scale. Since the quantization scale is an integer value in the range of 1 to 31, 6 bits are required. Becomes Therefore, 19 bits are required as the output of the multiplication unit 3.

[0010]

According to the MPEG-4 standard,
The inverse quantization coefficient (F ′ [i]) is −2048 to 2047.
Although the maximum number is 12 bits in the 2's complement format, the inverse quantization circuit shown in FIG. , The output of the shift unit 1 is 13 bits, the output of the increment unit 2 is 13 bits, and the output of the multiplication unit 3 is 19 bits.
This is a bit, and this causes an increase in wiring, resulting in an increase in power consumption and an increase in the size of the chip with the inverse quantization circuit.

In view of the above point, the present invention makes it possible to reduce wiring, reduce power consumption, and reduce the size of a chip equipped with an inverse quantization circuit.
It is an object of the present invention to provide an inverse quantization circuit corresponding to the above.

[0012]

In the inverse quantization circuit of the present invention, the OR (logical sum) processed value of the bit 11 and bit 10 portions of | QF [i] | is set as a new bit 11 value, and |
The bit 9 to bit 0 portion of QF [i] | is set as a new bit 10 to bit 1, and the new bit 0 is set to "1".

According to the present invention, the operation (2 × | QF [i] | +1) necessary for the second dequantization processing can be performed in the first processing unit in a form in which the saturation processing is taken in advance. The output can be 12 bits.

[0014]

1 is a circuit diagram showing a main part of one embodiment of the present invention. One embodiment of the present invention is MPEG-
It is an example of an inverse quantization circuit corresponding to 4. In FIG. 1, reference numeral 5 is a double / increment unit that constitutes the first processing unit, and reference numeral 6 is the output of the double / increment unit 5 or | QF controlled by a control signal.
[I] | Selector, 7 is a multiplication unit that forms a second processing unit, 8 is a scale table unit that draws dc_scaler (DC scaler) from the table, and 9 is a quantization scale or scale table unit controlled by a control signal. Output from 8
A selector 10 that selects dc_scaler is a saturation processing unit that forms a third processing unit.

FIG. 2 is a diagram for explaining the operation of the double / increment unit 5. In FIG. 2, A [i] is the output of the double / increment unit 5, and 11 is an OR circuit. The double / increment unit 5 changes | QF [i] | to [X ₁₁ X ₁₀
.. X ₀ ] ₂ , the OR processing value (X ₁₁ + X ₁₀ ) of the value [X ₁₁ ] of bit ₁₁ and the value [X ₁₀ ] of bit 10 of | QF [i] | Set the value of bit 11 to | Q
Value of bit 9 to bit 0 of F [i] | [X ₉ X ₈ ... X ₀ ] ₂
Is shifted to the left by 1 bit and bits 10 to 10 of A [i]
A process of setting the value of bit 1 to the value of bit 0 of A [i] to [1] is performed, and setting the value of A [i] to [(X ₁₁ + X ₁₀ ) X ₉
X ₈ ... X ₀ 1] ₂ is output.

That is, the double / increment unit 5 is
| QF [i] | is the maximum value [2048] ₁₀ = [10
0000000000] ₂ and then [204
9] ₁₀ = [100000000001] ₂ is output, and |
QF [i] | is [2047] ₁₀ = [011111111
111] ₂ or less, then | QF [i] |
Double processing and further +1 processing (2 × | QF [i] | +
1) is output, so to speak, the operation of (2 × | QF [i] | +1) is performed in a form in which saturation processing is taken in advance.

FIG. 3 is a circuit diagram showing a main part of the multiplication unit 7. In FIG. 3, 12 is the output A of the double / increment unit 5.
It is a multiplier that multiplies [i] and the quantization scale so as to match the second inverse quantization process. Here, since the output A [i] of the double / increment unit 5 is 12 bits,
If the quantization scale is 6 bits, the output of the multiplier 12 will be 18 bits.

Further, 13 is bit 1 of the output of the multiplier 12.
An OR circuit for ORing the portion of 7 to 12 bits, and 14 ORs the portion of bits 11 to 0 of the output of the multiplier 12
It is a high-order 1-bit expansion circuit that outputs the result of adding the output of the circuit 13 as the value of bit 12.

That is, the output of the multiplier 12 is [Y ₁₇ Y ₁₆
.., Y ₀ ] ₂ , the OR circuit 13 has Y ₁₇ , Y ₁₆ ,
, Y ₁₂ is OR-processed and (Y ₁₇ + Y ₁₆ + ... + Y ₁₂ ) is output, and the upper 1-bit expansion circuit 14 outputs [(Y ₁₇ + Y ₁₆ +
_{... + Y 12) Y 11 Y} 10 ... Y 0] will output a _2.

As a result, the high-order 1-bit expansion circuit 14
When (Y ₁₇ + Y ₁₆ + ... + Y ₁₂ ) = 1, [1Y ₁₁ Y
₁₀ ... Y ₀ ] ₂ will be output, but [1000000
Since 000000] ₂ is [4096] ₁₀ , the bit 12 of the output B [i] of the multiplication unit 7 serves as a flag bit indicating whether or not the multiplication is saturated.

In the multiplier 12, the macro block being processed is an intra macro block, and the DC component (AC / DC quantization coefficient QF [i] 0th (i =
0) coefficient), | QF [i] | × dc_scaler
It is controlled so as to perform an operation of (DC scaler).

The value of dc_scaler can be derived from Table 1, but if necessary, according to Table 1, "2 × quantiser_"
Instead of performing calculations such as "scale",
The calculations specified in Table 1 are performed, the results are stored in a table, and the scale table unit 7 is used when necessary.
I will take it out through. In this way, the amount of calculation can be reduced.

[0023]

[Table 1]

FIG. 4 is a circuit diagram showing a main part of the saturation processing section 10. In FIG. 4, 15 is [100000000000000]
2048 output circuit that outputs ₂ (= [2048] ₁₀ ),
16 is [010000000000000] (= [2047]
₂₀ ) output circuit for outputting ₁₀ ), 17 is a part of bits 11 to 0 of the output (B [i]) of the multiplication unit 7, or
It is a selector that selects and outputs the output of the 2048 output circuit 15 or the output of the 2047 output circuit 16. Here, the parameter bits_per_pixel has a fixed value of 8.

Reference numeral 18 is an OR circuit for ORing the bit 12 and bit 11 portions of the output (B [i]) of the multiplication unit 7, 1
Reference numeral 9 is a selector control circuit for controlling the select operation of the selector 17 by inputting the output of the OR circuit 18 and the sign of QF [i]. When the code of QF [i] is "0",
It shows that QF [i] is a positive value, and when it is "1", it shows that QF [i] is a negative value.

In the selector control circuit 19, 20 is O.
An AND circuit for ANDing the output of the R circuit 18 and the sign of QF [i], and 21 for inverting the sign of QF [i]
A T circuit, 22 is an AND circuit for ANDing the output of the OR circuit 18 and the output of the NOT circuit 21.

SEL1 and SEL0 are selector control signals, and SEL1 is the output of the AND circuit 20 and SEL.
0 is the output of the AND circuit 22. Table 2 is a truth table of the selector control circuit 19, and Table 3 is a truth table of the selector 17.

[0028]

[Table 2]

[0029]

[Table 3]

That is, the saturation processing section 10 selects SEL1 =
When “0” and SEL0 = “0”, the output B [i] of the multiplication unit 7 is not saturated, so the output B of the multiplication unit 7 is B.
The bits 11 to 0 of [i] are output and SEL
When 1 = “0” and SEL0 = “1”, the output B [i] of the multiplication unit 7 is saturated in the positive direction.
111111111] ₂ (= [2047] ₁₀ ) is output, and when SEL1 = "1" and SEL0 = "0",
Since the output B [i] of the multiplication unit 7 is saturated in the negative direction, [100000000000000] ₂ (= [2048]
₁₀ ) is output.

After the saturation process, a process of adding a sign is performed if necessary. For example, when the sign of QF [i] is “0” (QF [i] is a positive value), the result of saturation processing is used as it is, and “0” is assigned to the most significant bit (bit 11). Every other time, the code of QF [i] is “1” (Q
When F [i] is a negative value, all the bits of the saturation processing result are inverted and "1" is added, and the most significant bit (bit 1) is added.
Substitute “1” for 1). Instead of this, it is also possible to use two systems of signals, the result of saturation processing (absolute value) and the code to be added to the result of saturation processing.

As described above, according to the embodiment of the present invention, the operation of (2 × | QF [i] | +1) is performed by providing the doubling / incrementing unit 5 and, so to speak, the saturation process in advance. The output of the multiplier 12 is 12 bits, that is, the input of the multiplier 12 is 12 bits, and the output of the multiplier 12 is 1
It can be 8 bits, and even with this, MPE
The second inverse quantization process and the saturation process required by the G-4 standard can be performed. By the way, in the inverse quantization circuit shown in FIG. 6, the input of the multiplication unit 3 is 13 bits, and the output of the multiplication unit 3 is 19 bits. Therefore, according to the embodiment of the present invention, it is possible to reduce wiring, reduce power consumption, and reduce the size of the inverse quantization circuit mounting chip.

In the recent miniaturization process,
It has been pointed out that if there are many wires, there is a disadvantage that it becomes difficult for signals to reach ("Performance-oriented circuit design").
1st, Circuit design in the wiring priority era, Design Wave MAGAZI
NE, JULY, 2001. CQ publisher). According to the embodiment of the present invention, the number of wirings can be reduced, so that such a problem can be avoided.

By the way, FIG. 5 is a circuit diagram showing a main part of an MPEG-4 decoder using an inverse quantization circuit according to an embodiment of the present invention. In FIG. 5, 23 is a variable length decoding circuit, 2
4 is an inverse quantization circuit of one embodiment of the present invention, 25 is an inverse DC
T circuit, 26 motion compensation processing circuit, 27 addition circuit, 2
Reference numeral 8 is a frame memory, and 29 is a display for displaying the image written in the frame memory 28.

In this MPEG-4 decoder, the variable length decoding circuit 23 converts the MPEG-4 encoded data into A
The C / DC quantized coefficient and the motion vector data are extracted, and the AC / DC quantized coefficient is processed by the inverse quantization circuit 24 and then subjected to the inverse DCT processing by the inverse DCT circuit 25. In addition, the motion vector data is stored in the motion compensation processing circuit 2
After passing through 6, the coefficient is added to the coefficient after the inverse DCT processing and written in the frame memory 28 to be decoded image data, and the decoded image data is displayed on the display 29.

[0036]

As described above, according to the present invention, in the first processing unit, (2 × | QF) necessary for the second inverse quantization processing is obtained.
The operation [i] | +1) can be performed with the saturation processing pre-empted and the output can be set to 12 bits, so wiring is reduced, power consumption is reduced, and the size of the chip with the inverse quantization circuit is reduced. Can be realized.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a main part of an embodiment of the present invention.

FIG. 2 is a diagram for explaining an operation of a double / increment unit included in an embodiment of the present invention.

FIG. 3 is a circuit diagram showing a main part of a multiplication unit included in an embodiment of the present invention.

FIG. 4 is a circuit diagram showing a main part of a saturation processing unit included in one embodiment of the present invention.

FIG. 5 is a circuit diagram showing a main part of an MPEG-4 decoder using an inverse quantization circuit according to an embodiment of the present invention.

FIG. 6 is a circuit diagram showing an example of a conventionally proposed inverse quantization circuit for an MPEG-4 decoder.

7 is a diagram for explaining operations of a shift unit and an increment unit included in the inverse quantization circuit shown in FIG.

[Explanation of symbols]

QF [i] ... AC / DC quantized coefficient F '[i] ... Dequantized coefficient

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 5C059 KK49 KK50 MA31 MC33 MC35                       MC38 ME01 UA05                 5J064 AA04 BA16 BC01 BC02 BC03                       BC09 BC16 BC25 BD02

Claims (4)

[Claims] 1. A bit 1 of an absolute value of an AC / DC quantized coefficient
1 and bit 10 are ORed with new bit 11
Of the absolute value of the AC / DC quantized coefficient is set as a new bit 10 to bit 1, and the new bit 0 is set to “1”. An inverse quantization circuit having. 2. An OR-processed value of the bit 17 to bit 12 portion of the multiplication value is set to bit 1 to bit 0 of the multiplication value of the output of the first processing unit and the quantization scale.
The inverse quantization circuit according to claim 1, further comprising a second processing unit that outputs a result added as 2. 3. The bit 11 to bit 0 of the output of the second processing unit are determined as the absolute value of the inverse quantization coefficient in accordance with the OR processed value of the bit 12 and bit 11 portions of the output of the second processing unit. 3. The inverse quantization circuit according to claim 2, further comprising a third processing unit for outputting the portion 2048 or 2047. 4. The inverse quantum according to claim 1, further comprising a scale table unit for drawing a DC scaler from the table, which is adapted to correspond to an inverse quantization process of a DC component of an intra macroblock. Circuit.