JP2003131934A - Memory control circuit and information processing system - Google Patents

Memory control circuit and information processing system

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Publication number
JP2003131934A
JP2003131934A JP2001328873A JP2001328873A JP2003131934A JP 2003131934 A JP2003131934 A JP 2003131934A JP 2001328873 A JP2001328873 A JP 2001328873A JP 2001328873 A JP2001328873 A JP 2001328873A JP 2003131934 A JP2003131934 A JP 2003131934A
Authority
JP
Japan
Prior art keywords
memory
control circuit
cpu
clear
instruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001328873A
Other languages
Japanese (ja)
Inventor
Kazuhiko Shimamoto
和彦 島本
Original Assignee
Seiko Epson Corp
セイコーエプソン株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, セイコーエプソン株式会社 filed Critical Seiko Epson Corp
Priority to JP2001328873A priority Critical patent/JP2003131934A/en
Publication of JP2003131934A publication Critical patent/JP2003131934A/en
Application status is Pending legal-status Critical

Links

Abstract

PROBLEM TO BE SOLVED: To provide a memory control circuit that more effectively uses a CPU capability. SOLUTION: A memory control circuit 12 has a memory clear control process to clear a memory region of a part of memory 13, which is specified by a memory clear instruction from a CPU 11, when the memory control circuit 12 receives the memory clear instruction from the CPU 11. The memory control circuit 12 starts to execute the memory clear process that does not require any instruction from the CPU 11 for executing the process, and also has a function to inform the CPU 11 the completion of the memory clear instruction when the memory clear control process is terminated.

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory and a CPU.
And an information processing apparatus including such a memory control circuit. 2. Description of the Related Art As is well known, in an information processing apparatus, a part or all of a memory is often cleared. Hereinafter, a memory clear procedure in a conventional information processing apparatus will be described using a printer having the configuration shown in FIG. 3 as an example. A print engine 27 included in the printer 20 is a mechanism for actually performing printing on paper, and an image processing circuit 26 includes image data for printing to be supplied to the print engine 27. And a circuit (ASIC) for performing image processing such as edge enhancement. The IO control circuit 25 is a circuit (ASIC) for controlling a host I / F (not shown) which is an interface with a host computer, an operation panel (not shown) provided on the upper surface of the printer 20, and the like. ). The CPU 21 controls the respective units in an integrated manner, thereby causing the print engine 27 to perform printing in accordance with the print data transmitted from the host computer (hereinafter, referred to as print control processing), an operation panel, and the like. Is a control circuit that performs a process of acquiring an instruction about a process to be executed from the user through an operation on the. [0005] The ROM 24 is a non-volatile memory that stores programs executed by the CPU 21, font data used by the CPU 21, and the like. The memory 23 is a memory used to generate data to be supplied to the print engine 27 (image processing circuit 26) based on the received print data. The memory 23 is also a memory in which the program is executed (the program stored in the ROM 24 is read). The memory control circuit 22 has a function of controlling the memory 23 and print data stored in the memory 2.
3 or a circuit (ASIC) having a function of executing a process of supplying data on the memory 23 to the image processing circuit 26 (that is, a simple data transfer process). [0006] In the printer 20, the processing of the procedure shown in FIG. 4 is performed by the CPU 21 as print control processing. That is, when the power is turned on, the CPU 21 first performs various initial settings (step S).
201). Next, the CPU 21 sets the memory control circuit 22
Clear area of the memory 23 (the print engine 27
White data (ALL1 data) in each address in the area that can store one page of image data to be supplied to
Are sequentially written (steps S202 and S203). That is, in the processing loop including steps S202 and S203, the CPU 21
2 is repeatedly executed to instruct white data to be written in the clear required area of the memory 23. When the clearing of the clear required area is completed (step S203; YES), the CPU 21
Waiting for print data to be received (step S
204), and if the print data is received (step S204; YES), the print engine 2 is converted from the print data using the cleared storage area of the memory 23.
The processing (steps S205 and S206) for generating one page of image data to be supplied to 7 is started. When the CPU 21 has generated image data of one page (step S206; YE
S) supplies the image data to the print engine 27 via the image processing circuit 26.
2 (step S207). And CPU2
1 executes the processing from step S202 again. [0010] The printer 20 described above.
As is clear from the print control processing procedure described above, the conventional information processing apparatus is an apparatus in which the CPU must clear the memory. If the CPU is restricted for simple processing such as clearing the memory, it is not possible to make full use of the CPU's capabilities. desired. [0011] The present invention has been made in view of such circumstances, and an object of the present invention is to solve the problem by using the CPU.
It is an object of the present invention to provide a memory control circuit that can make more effective use of the capability. Another object of the present invention is to
An object of the present invention is to provide an information processing apparatus capable of operating in a form that more effectively utilizes the capabilities of a CPU. According to the present invention, a memory control circuit for accessing a memory according to an instruction from a CPU is provided from the CPU.
When one memory area of the memory receives the memory clear instruction specified, the memory clear control processing for clearing the storage area of the memory specified by the memory clear instruction is started, and the memory clear control processing of the memory clear control processing is started. At the time of termination, a function of notifying the CPU that the memory clear has been completed is provided. By using this memory control circuit, the CPU can be controlled while the memory clear control process is being performed (before the memory clear instruction is issued and before the notification of the completion of the memory clear is issued). The processing can be executed. Therefore, if this memory control circuit is used,
The ability of the CPU can be used more effectively. In realizing the memory control circuit of the present invention, the memory clear control process is performed so that the CPU can access the memory while the memory control circuit is executing the memory clear control process. It is desirable that the processing be interrupted when the CPU requests access to the memory. The memory control circuit of the present invention may be configured so that data to be written in the memory clear control process cannot be specified.
The start address and end address of the storage area where the memory is to be cleared and the data to be written to each address in the storage area are designated as instructions, and the memory clear control processing is designated by the memory clear instruction. If the processing specified in the memory clear instruction is written to each address in the memory area of the memory defined by the start address and the end address, the specified memory can be specified without imposing a load on the CPU. A memory control circuit capable of writing the specified data in the area can be realized. An information processing apparatus according to the present invention is an information processing apparatus including a memory control circuit, a CPU, and a memory. The information processing apparatus includes the memory control circuit according to the present invention as a memory control circuit. After issuing a memory clear instruction designating one storage area of the memory to the memory control circuit, when the memory control circuit notifies the end of the memory clear, the processing using the storage area is started. It has a configuration in which the created program is executed. Therefore, the information processing device of the present invention functions as a device in which the capacity of the CPU is effectively used. Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows a block diagram of an information processing apparatus according to one embodiment of the present invention. The information processing apparatus 10 according to the present embodiment is a so-called laser beam printer.
The main components are a CPU 11 and a memory control circuit 1
2, a memory 13, a ROM 14, an IO control circuit 15, an image processing circuit 16, and a print engine 17. The basic function of each element constituting the information processing apparatus 10 is the same as the element of the same name included in the printer 20 already described with reference to FIG. However, the memory control circuit 12 has a function to execute a memory clear control process for clearing a part of the memory 13 and a notice to the effect that the memory clear is completed when the memory clear control process is completed. CPU11
And a notification function. In addition,
The memory control circuit 12 of the present embodiment uses a so-called interrupt to notify that the memory clear has been completed. The memory clear control process executed by the memory control circuit 12 specifies a start address and an end address of a storage area to be cleared in the memory 13 and data to be written to each address in the storage area. The processing is started when the specified memory clear instruction is given from the CPU 11, and at each address in the storage area of the memory 13 defined by the start address and the end address specified by the memory clear instruction. The process is to write the data specified by the clear instruction. Further, the memory control circuit 12 is configured to be able to receive an access request to the memory 13 from the CPU 11 during the execution of the memory clear control processing. Specifically, the memory control circuit 12 stores a predetermined amount of data in the memory 1 when executing the memory clear control process.
3 each time the CPU 11 writes another instruction (for example,
It is checked whether an instruction to read / write data from an area different from the area to be cleared of the memory 13 has been issued, and if another instruction has been issued,
The configuration is such that the memory clear control process is temporarily interrupted, control according to the instruction is performed on the memory 13, and then the memory clear control process is restarted. Since the memory control circuit 12 is mounted, the information processing apparatus 10 of the present embodiment
Is an apparatus that allows the CPU 11 to execute the print control process in the procedure as shown in FIG. That is, C which is executing the print control process
In steps S101 and S104 to S107, the PU 11 performs steps S201 and S201 in FIG.
The processing having the same contents as those in S204 to S207 is executed. However, when it is necessary to clear the memory 13, the CPU 11 itself performs a process for clearing the memory 13 (see steps S202 and S203).
Instead, the start address and the end address of the clear required area (the area capable of storing one page of image data to be supplied to the print engine 17) and the clear required area are notified to the memory control circuit 12. A memory clear instruction specifying data to be written (in this case, white data) is issued (step S102). The memory control circuit 12 which has received the memory clear instruction stores the memory clear in the storage area of the memory 13 specified by the start address and the end address specified in the memory clear instruction as described above. A memory clear control process for writing the data specified in the instruction is started. Then, at the time of the end, the memory control circuit 12 notifies the CPU 11 that the memory clear has ended. On the other hand, the CPU 11
Is notified of the completion of memory clear (step S1)
03; YES), the processing after step S104 is started. After the completion of step S102, until the step S104 is started, the CPU 11 is in a state where there is no processing to be executed. Therefore, the information processing apparatus 10 can cause the CPU 11 to execute other processing during this time. As a result, the information processing apparatus 10 functions as a device in which the capability of the CPU 11 is effectively used. Become. <Modifications> The information processing apparatus 10 according to the present embodiment can perform various modifications. For example,
Although the memory control circuit 12 can specify data to be written to the memory 13, the memory control circuit 12 cannot specify data to be written to the memory 13 (All1 data or All0 data).
The memory control circuit 12 may be configured so that data is always written to the memory 13). The information processing apparatus 10 according to the embodiment
Is a laser beam printer, but it goes without saying that the technology used in the information processing device 10 may be applied to a device different from the laser beam printer. According to the present invention, it is possible to obtain a memory control circuit and an information processing device which can more effectively utilize the capacity of the CPU.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a configuration of an information processing apparatus according to one embodiment of the present invention. FIG. 2 is a flowchart of a print control process executed by a CPU in the information processing apparatus according to the embodiment. FIG. 3 is a block diagram showing a configuration of a conventional printer. FIG. 4 is a flowchart of a print control process executed by a CPU in the printer shown in FIG. 3; [Description of Signs] 10 Information processing device (printer) 11, 21 CPU 12, 22 Memory control circuit 13, 23 Memory 14, 24 ROM 15, 25 IO control circuit 16, 26 Image processing circuit 17, 27 Print engine 20 Printer

Claims (1)

1. A memory control circuit for accessing a memory in accordance with an instruction from a CPU, wherein the memory control circuit receives a memory clear instruction designating one storage area of the memory from the CPU. A function of starting a memory clear control process for clearing a storage area of the memory designated by the memory clear instruction and notifying the CPU that the memory clear has been completed at the end of the memory clear control process. A memory control circuit, comprising: 2. The memory clear control process according to claim 2, wherein
2. The memory control circuit according to claim 1, wherein the processing is interrupted when an access to the memory from the U is requested. 3. The memory clear instruction is an instruction in which a start address and an end address of a storage area in which the memory is to be cleared and data to be written to each address in the storage area are specified. The memory clear control process is a process of writing data specified by the memory clear instruction to each address in the storage area of the memory defined by a start address and an end address specified by the memory clear instruction. 3. The memory control circuit according to claim 1, wherein: 4. An information processing apparatus comprising a memory control circuit, a CPU, and a memory, wherein the memory control circuit receives a memory clear instruction designating one storage area of the memory from the CPU. A function of initiating a memory clear control process for clearing a storage area of the memory designated by the memory clear instruction and notifying the CPU that the memory clear has been completed at the end of the memory clear control process. And the program executed by the CPU is the CP
U sends a memory clear instruction designating one storage area of the memory to the memory control circuit, and then uses the storage area when the memory control circuit notifies the memory control circuit of the end of the memory clear. An information processing apparatus characterized in that the information processing apparatus is created so as to start.
JP2001328873A 2001-10-26 2001-10-26 Memory control circuit and information processing system Pending JP2003131934A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001328873A JP2003131934A (en) 2001-10-26 2001-10-26 Memory control circuit and information processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001328873A JP2003131934A (en) 2001-10-26 2001-10-26 Memory control circuit and information processing system

Publications (1)

Publication Number Publication Date
JP2003131934A true JP2003131934A (en) 2003-05-09

Family

ID=19144865

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001328873A Pending JP2003131934A (en) 2001-10-26 2001-10-26 Memory control circuit and information processing system

Country Status (1)

Country Link
JP (1) JP2003131934A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009289117A (en) * 2008-05-30 2009-12-10 Fujitsu Ltd Memory clear mechanism
JP2010541103A (en) * 2007-10-02 2010-12-24 クゥアルコム・インコーポレイテッドQualcomm Incorporated Memory controller for performing memory block initialization and copying
JP2013532880A (en) * 2010-08-03 2013-08-19 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッドAdvanced Micro Devices Incorporated Processor support to fill memory area

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010541103A (en) * 2007-10-02 2010-12-24 クゥアルコム・インコーポレイテッドQualcomm Incorporated Memory controller for performing memory block initialization and copying
JP2009289117A (en) * 2008-05-30 2009-12-10 Fujitsu Ltd Memory clear mechanism
JP2013532880A (en) * 2010-08-03 2013-08-19 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッドAdvanced Micro Devices Incorporated Processor support to fill memory area

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