JP2003100864A - 二重ダマシーン構造体を形成する方法 - Google Patents

二重ダマシーン構造体を形成する方法

Info

Publication number
JP2003100864A
JP2003100864A JP2002199839A JP2002199839A JP2003100864A JP 2003100864 A JP2003100864 A JP 2003100864A JP 2002199839 A JP2002199839 A JP 2002199839A JP 2002199839 A JP2002199839 A JP 2002199839A JP 2003100864 A JP2003100864 A JP 2003100864A
Authority
JP
Japan
Prior art keywords
dielectric layer
layer
trench
etching
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002199839A
Other languages
English (en)
Japanese (ja)
Inventor
Abbas Ali
アリ アッバス
Ming Yang
ヤン ミン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of JP2003100864A publication Critical patent/JP2003100864A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H01L21/0276—Photolithographic processes using an anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2002199839A 2001-07-09 2002-07-09 二重ダマシーン構造体を形成する方法 Pending JP2003100864A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US901331 1992-06-19
US09/901,331 US6605540B2 (en) 2001-07-09 2001-07-09 Process for forming a dual damascene structure

Publications (1)

Publication Number Publication Date
JP2003100864A true JP2003100864A (ja) 2003-04-04

Family

ID=25413959

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002199839A Pending JP2003100864A (ja) 2001-07-09 2002-07-09 二重ダマシーン構造体を形成する方法

Country Status (4)

Country Link
US (2) US6605540B2 (fr)
EP (1) EP1280197B1 (fr)
JP (1) JP2003100864A (fr)
DE (1) DE60235338D1 (fr)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004356521A (ja) * 2003-05-30 2004-12-16 Nec Electronics Corp 半導体装置およびその製造方法
JP2007019258A (ja) * 2005-07-07 2007-01-25 Toshiba Corp 半導体装置
KR101016340B1 (ko) 2003-12-15 2011-02-22 매그나칩 반도체 유한회사 고주파 반도체 장치의 인덕터 제조방법
US8227339B2 (en) 2009-11-02 2012-07-24 International Business Machines Corporation Creation of vias and trenches with different depths

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EP1316108B9 (fr) * 2000-08-18 2007-10-03 Tokyo Electron Limited Procede de fabrication d'un dispositif semi-conducteur comprenant un film intermediaire de nitrure de silicium faiblement dielectrique
US6605540B2 (en) * 2001-07-09 2003-08-12 Texas Instruments Incorporated Process for forming a dual damascene structure
US7183201B2 (en) * 2001-07-23 2007-02-27 Applied Materials, Inc. Selective etching of organosilicate films over silicon oxide stop etch layers
JP2003209166A (ja) * 2002-01-17 2003-07-25 Seiko Epson Corp 半導体装置及びその製造方法
DE10219398B4 (de) * 2002-04-30 2007-06-06 Infineon Technologies Ag Herstellungsverfahren für eine Grabenanordnung mit Gräben unterschiedlicher Tiefe in einem Halbleitersubstrat
US20050059233A1 (en) * 2003-09-12 2005-03-17 Ming-Tsong Wang Process for forming metal damascene structure to prevent dielectric layer peeling
CN1299348C (zh) * 2003-09-28 2007-02-07 中芯国际集成电路制造(上海)有限公司 集成电路的倾斜镶嵌内连接结构的形成方法
US7504727B2 (en) * 2004-05-14 2009-03-17 International Business Machines Corporation Semiconductor interconnect structure utilizing a porous dielectric material as an etch stop layer between adjacent non-porous dielectric materials
US7235489B2 (en) * 2004-05-21 2007-06-26 Agere Systems Inc. Device and method to eliminate shorting induced by via to metal misalignment
US7067435B2 (en) * 2004-09-29 2006-06-27 Texas Instruments Incorporated Method for etch-stop layer etching during damascene dielectric etching with low polymerization
KR100641485B1 (ko) * 2004-12-28 2006-11-01 동부일렉트로닉스 주식회사 반도체 소자 제조 방법
US7394154B2 (en) * 2005-09-13 2008-07-01 International Business Machines Corporation Embedded barrier for dielectric encapsulation
US7416953B2 (en) * 2005-10-31 2008-08-26 Taiwan Semiconductor Manufacturing Co., Ltd. Vertical MIM capacitors and method of fabricating the same
US20070290347A1 (en) * 2006-06-19 2007-12-20 Texas Instruments Incorporated Semiconductive device having resist poison aluminum oxide barrier and method of manufacture
JP5128851B2 (ja) * 2007-05-30 2013-01-23 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法
US7994639B2 (en) * 2007-07-31 2011-08-09 International Business Machines Corporation Microelectronic structure including dual damascene structure and high contrast alignment mark
DE102008063430B4 (de) * 2008-12-31 2016-11-24 Advanced Micro Devices, Inc. Verfahren zur Herstellung eines Metallisierungssystem eines Halbleiterbauelements mit zusätzlich verjüngten Übergangskontakten
CN101905854B (zh) * 2009-06-04 2012-08-22 台湾积体电路制造股份有限公司 电子元件及其制法、电子系统
US10586689B2 (en) * 2009-07-31 2020-03-10 Guardian Europe S.A.R.L. Sputtering apparatus including cathode with rotatable targets, and related methods
US20130288474A1 (en) * 2012-04-27 2013-10-31 Applied Materials, Inc. Methods for fabricating dual damascene interconnect structures
US8986921B2 (en) * 2013-01-15 2015-03-24 International Business Machines Corporation Lithographic material stack including a metal-compound hard mask
US9390964B2 (en) 2013-03-15 2016-07-12 Applied Materials, Inc. Methods for fabricating dual damascene structures in low temperature dielectric materials
US9917027B2 (en) * 2015-12-30 2018-03-13 Globalfoundries Singapore Pte. Ltd. Integrated circuits with aluminum via structures and methods for fabricating the same
KR102285787B1 (ko) * 2017-03-03 2021-08-04 삼성전자 주식회사 3차원 반도체 소자

Family Cites Families (19)

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US6303523B2 (en) * 1998-02-11 2001-10-16 Applied Materials, Inc. Plasma processes for depositing low dielectric constant films
US6380096B2 (en) * 1998-07-09 2002-04-30 Applied Materials, Inc. In-situ integrated oxide etch process particularly useful for copper dual damascene
US6103456A (en) 1998-07-22 2000-08-15 Siemens Aktiengesellschaft Prevention of photoresist poisoning from dielectric antireflective coating in semiconductor fabrication
KR20000013397A (ko) * 1998-08-07 2000-03-06 윤종용 트렌치 격리 형성 방법
US6060380A (en) 1998-11-06 2000-05-09 Advanced Micro Devices, Inc. Antireflective siliconoxynitride hardmask layer used during etching processes in integrated circuit fabrication
KR100300628B1 (ko) * 1999-02-08 2001-09-26 윤종용 실리콘 옥시나이트라이드 보호층을 갖는 반도체 장치 및 그 제조 방법
US6228760B1 (en) * 1999-03-08 2001-05-08 Taiwan Semiconductor Manufacturing Company Use of PE-SiON or PE-OXIDE for contact or via photo and for defect reduction with oxide and W chemical-mechanical polish
US6235653B1 (en) 1999-06-04 2001-05-22 Taiwan Semiconductor Manufacturing Company Ar-based si-rich oxynitride film for dual damascene and/or contact etch stop layer
US6326301B1 (en) * 1999-07-13 2001-12-04 Motorola, Inc. Method for forming a dual inlaid copper interconnect structure
CN1192427C (zh) 1999-08-25 2005-03-09 因芬尼昂技术股份公司 制造具有至少一个金属化平面的集成电路的方法
US6391761B1 (en) * 1999-09-20 2002-05-21 Taiwan Semiconductor Manufacturing Company Method to form dual damascene structures using a linear passivation
US6429119B1 (en) * 1999-09-27 2002-08-06 Taiwan Semiconductor Manufacturing Company Dual damascene process to reduce etch barrier thickness
US6222241B1 (en) * 1999-10-29 2001-04-24 Advanced Micro Devices, Inc. Method and system for reducing ARC layer removal by providing a capping layer for the ARC layer
US6329281B1 (en) * 1999-12-03 2001-12-11 Agere Systems Guardian Corp. Methods for fabricating a multilevel interconnection for an integrated circuit device utilizing a selective overlayer
US6342448B1 (en) * 2000-05-31 2002-01-29 Taiwan Semiconductor Manufacturing Company Method of fabricating barrier adhesion to low-k dielectric layers in a copper damascene process
US6410437B1 (en) * 2000-06-30 2002-06-25 Lam Research Corporation Method for etching dual damascene structures in organosilicate glass
US6475929B1 (en) * 2001-02-01 2002-11-05 Advanced Micro Devices, Inc. Method of manufacturing a semiconductor structure with treatment to sacrificial stop layer producing diffusion to an adjacent low-k dielectric layer lowering the constant
US6511922B2 (en) * 2001-03-26 2003-01-28 Applied Materials, Inc. Methods and apparatus for producing stable low k FSG film for HDP-CVD
US6605540B2 (en) * 2001-07-09 2003-08-12 Texas Instruments Incorporated Process for forming a dual damascene structure

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004356521A (ja) * 2003-05-30 2004-12-16 Nec Electronics Corp 半導体装置およびその製造方法
US7807567B2 (en) 2003-05-30 2010-10-05 Nec Electronics Corporation Semiconductor device with interconnection structure for reducing stress migration
JP4571785B2 (ja) * 2003-05-30 2010-10-27 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
KR101016340B1 (ko) 2003-12-15 2011-02-22 매그나칩 반도체 유한회사 고주파 반도체 장치의 인덕터 제조방법
JP2007019258A (ja) * 2005-07-07 2007-01-25 Toshiba Corp 半導体装置
JP4550678B2 (ja) * 2005-07-07 2010-09-22 株式会社東芝 半導体装置
US8227339B2 (en) 2009-11-02 2012-07-24 International Business Machines Corporation Creation of vias and trenches with different depths
US8703604B2 (en) 2009-11-02 2014-04-22 International Business Machines Corporation Creation of vias and trenches with different depths
US8907458B2 (en) 2009-11-02 2014-12-09 International Business Machines Corporation Creation of vias and trenches with different depths

Also Published As

Publication number Publication date
US20030008512A1 (en) 2003-01-09
US6605540B2 (en) 2003-08-12
EP1280197B1 (fr) 2010-02-17
EP1280197A1 (fr) 2003-01-29
DE60235338D1 (fr) 2010-04-01
US20040092113A1 (en) 2004-05-13
US7112532B2 (en) 2006-09-26

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