JP2003096573A - Method for deposition of electroless plating film - Google Patents

Method for deposition of electroless plating film

Info

Publication number
JP2003096573A
JP2003096573A JP2001288395A JP2001288395A JP2003096573A JP 2003096573 A JP2003096573 A JP 2003096573A JP 2001288395 A JP2001288395 A JP 2001288395A JP 2001288395 A JP2001288395 A JP 2001288395A JP 2003096573 A JP2003096573 A JP 2003096573A
Authority
JP
Japan
Prior art keywords
semiconductor substrate
electroless plating
plating
film
potential
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2001288395A
Other languages
Japanese (ja)
Other versions
JP2003096573A5 (en
JP4647159B2 (en
Inventor
Hiroaki Nagakubo
永久保  浩章
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Citizen Watch Co Ltd
Original Assignee
Citizen Watch Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Watch Co Ltd filed Critical Citizen Watch Co Ltd
Priority to JP2001288395A priority Critical patent/JP4647159B2/en
Publication of JP2003096573A publication Critical patent/JP2003096573A/en
Publication of JP2003096573A5 publication Critical patent/JP2003096573A5/ja
Application granted granted Critical
Publication of JP4647159B2 publication Critical patent/JP4647159B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods

Abstract

PROBLEM TO BE SOLVED: To provide a method for depositing an electroless plating film of uniform film thickness onto pad electrodes of a semiconductor substrate without applying plating resist to the back and sides of the semiconductor substrate. SOLUTION: A zinc immersion film 23 is deposited by using a zinc immersion process onto the pad electrode 21. After washed with pure water, the semiconductor substrate 15 as a substrate to be plated is immersed in an oxidation- reduction type electroless nickel plating solution using a nickel-plated stainless- steel bar as a counter electrode 12 and using this counter electrode 12 as a negative electrode while applying a minute positive potential to the semiconductor substrate 15. By this method, a bump 16 composed of an electroless nickel plating film of uniform film thickness can be formed on a plurality of pieces of the pad electrode 21 while obviating the necessity of the application of plating-resist to the back and sides of the semiconductor substrate 15.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、半導体基板のパッ
ド電極上に選択的、且つ均一にめっき金属を析出させる
ための無電解めっき皮膜の形成方法に関するものであ
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an electroless plating film for selectively and uniformly depositing a plating metal on a pad electrode of a semiconductor substrate.

【0002】[0002]

【従来の技術】半導体基板の能動素子面に形成されたア
ルミニウムを主成分としたパッド電極上に無電解めっき
によってバリアメタル、或いは突起電極を形成しようと
する場合、該パッド電極上に選択的に、且つ半導体基板
上の複数個のパッド電極に対して均一に無電解めっき反
応が開始、継続することが要求される。
2. Description of the Related Art When a barrier metal or a bump electrode is to be formed by electroless plating on a pad electrode composed mainly of aluminum formed on the active element surface of a semiconductor substrate, the pad electrode is selectively formed on the pad electrode. In addition, it is required that the electroless plating reaction be uniformly started and continued for a plurality of pad electrodes on the semiconductor substrate.

【0003】そこで前記パッド電極上に選択的、且つ均
一に無電解めっき皮膜を形成するために、そのパッド電
極上のみに亜鉛置換処理やパラジウム等の触媒を付与し
て活性化させる方法が用いられるが、以下に亜鉛置換法
を用いた突起電極の形成方法について、図3を参照しな
がら説明する。
Therefore, in order to selectively and uniformly form an electroless plating film on the pad electrode, a method of activating zinc plating treatment or applying a catalyst such as palladium only on the pad electrode is used. However, a method of forming a protruding electrode using the zinc substitution method will be described below with reference to FIG.

【0004】図3(a)〜(e)は、従来の半導体基板
の電極形成方法を示した工程断面図である。この工程図
は半導体基板上の1個の電極の製造方法について示して
いるが、この工程において、多数の電極を一度に形成で
きることを理解されたい。まず、図3(a)に示すよう
に半導体基板15のアルミニウムを主成分とするパッド
電極21と、該パッド電極上に開口部を有するパッシベ
ーション膜22が形成される。前記開口部は、大気にさ
らされると直ぐに自然酸化皮膜が形成されるので、該自
然酸化皮膜を酸性液あるいはアルカリ性液に浸漬してエ
ッチング除去する。次に、図3(b)に示すように、半
導体基板15の裏面及び側面にめっきレジスト31をス
ピンコート法で塗布する。これは半導体基板裏面及び側
面でのめっき反応を防止するためである。
3A to 3E are process sectional views showing a conventional method for forming electrodes on a semiconductor substrate. Although this process diagram shows a method of manufacturing one electrode on a semiconductor substrate, it should be understood that in this process, many electrodes can be formed at one time. First, as shown in FIG. 3A, a pad electrode 21 containing aluminum as a main component of the semiconductor substrate 15 and a passivation film 22 having an opening on the pad electrode are formed. Since a natural oxide film is formed in the opening immediately after being exposed to the atmosphere, the natural oxide film is removed by etching by immersing the natural oxide film in an acid solution or an alkaline solution. Next, as shown in FIG. 3B, a plating resist 31 is applied to the back surface and side surfaces of the semiconductor substrate 15 by spin coating. This is to prevent the plating reaction on the back and side surfaces of the semiconductor substrate.

【0005】次に、前記めっきレジストが塗布された半
導体基板15をアルカリ性あるいは弱酸性の亜鉛酸塩水
溶液に浸漬して、図3(c)に示すように、自然酸化皮
膜が除去されたパッド電極21表面上に亜鉛置換皮膜2
3を置換析出させる。必要に応じて希硝酸等に浸漬して
一度析出した亜鉛置換皮膜23をエッチング除去した
後、再度前記亜鉛酸塩水溶液に浸漬してあらためて2度
目の亜鉛置換皮膜を形成させることもある。これは、よ
り均一かつ緻密な亜鉛置換被膜23を得るための手法で
あり、必要に応じて亜鉛置換皮膜のエッチング工程と亜
鉛置換工程がさらに繰り返される場合もある。
Next, the semiconductor substrate 15 coated with the plating resist is dipped in an alkaline or weakly acidic zincate aqueous solution to remove the natural oxide film, as shown in FIG. 3 (c). 21 Zinc substitution film 2 on the surface
3 is deposited by substitution. If necessary, the zinc substitution film 23 may be immersed in dilute nitric acid or the like to remove the deposited zinc substitution film 23 by etching, and then again immersed in the zincate aqueous solution to form a second zinc substitution film. This is a method for obtaining a more uniform and dense zinc substitution coating 23, and the zinc substitution coating etching step and the zinc substitution step may be further repeated if necessary.

【0006】次いで、半導体基板15を酸化還元型の無
電解めっき液に浸漬して、めっき金属によるバリアメタ
ルあるいは突起電極の形成を行うわけであるが、ここで
は無電解ニッケルめっきを用いる場合について説明す
る。図3(d)に示すように、亜鉛置換法の場合、半導
体基板15を無電解ニッケルめっき液に浸漬すると、前
記亜鉛置換皮膜23が溶解し、パッド電極21表面近傍
でニッケルの置換析出が起こり、その後はニッケルの自
己触媒作用によって無電解めっき反応が継続し、一定時
間浸漬しておくことにより図3(d)のように突起電極
16を形成することができる。
Next, the semiconductor substrate 15 is dipped in an oxidation-reduction type electroless plating solution to form a barrier metal or a bump electrode with a plating metal. Here, the case of using electroless nickel plating will be described. To do. As shown in FIG. 3D, in the case of the zinc substitution method, when the semiconductor substrate 15 is immersed in an electroless nickel plating solution, the zinc substitution film 23 is dissolved and substitution precipitation of nickel occurs near the surface of the pad electrode 21. After that, the electroless plating reaction is continued by the autocatalytic action of nickel, and the protruding electrodes 16 can be formed as shown in FIG.

【0007】最後に前記半導体基板15をレジスト剥離
液に浸漬して、図3(e)に示すように、半導体基板1
5の裏面及び側面に塗布しためっきレジスト31を剥離
する。
Finally, the semiconductor substrate 15 is dipped in a resist stripping solution, and as shown in FIG.
The plating resist 31 applied to the back surface and the side surface of 5 is peeled off.

【0008】[0008]

【発明が解決しようとする課題】従来の方法において、
半導体基板15の裏面及び側面にめっきレジストを塗布
しないで該半導体基板15を無電解めっき液に浸漬した
場合、無電解めっき液に対して活性化されていないシリ
コン等からなる半導体基板15の裏面及び側面では、本
来無電解めっき反応は発生しないはずであるが、前記亜
鉛置換処理後の水洗が不十分だった場合の亜鉛の残査や
無電解めっき液中の浮遊物等が核になって、半導体基板
15の裏面及び側面でも無電解めっき反応が発生するこ
とがある。しかし、この半導体基板15裏面及び側面は
活性化されていないため、均一なめっき皮膜は形成でき
ず、めっきが析出する部位とめっき未着の部位とが生じ
てしまう。
SUMMARY OF THE INVENTION In the conventional method,
When the semiconductor substrate 15 is immersed in the electroless plating solution without applying the plating resist to the back surface and the side surfaces of the semiconductor substrate 15, the back surface and the back surface of the semiconductor substrate 15 made of silicon or the like which is not activated by the electroless plating solution and On the side surface, the electroless plating reaction should not occur originally, but the residue of zinc and the suspended matter in the electroless plating solution are the core when the washing with water after the zinc substitution treatment is insufficient, Electroless plating reaction may occur on the back and side surfaces of the semiconductor substrate 15. However, since the back surface and the side surface of the semiconductor substrate 15 are not activated, a uniform plating film cannot be formed, and a portion where plating is deposited and a portion where plating is not adhered occur.

【0009】前記、半導体基板15の裏面及び側面で無
電解めっき反応が発生した部位では、無電解めっきの酸
化還元反応によって部分的な電位の低下が起こり、結果
として半導体基板15全体に電位のばらつきを生じさせ
ることとなる。この電位のバラツキは半導体基板15の
複数個のパッド電極21にも影響して、これら複数個の
パッド電極21上の無電解めっき皮膜の膜厚の不均一、
一部のパッド電極21へのめっき不着等の不良が発生
し、パッド電極21上への選択性を損なう要因となって
いた。
At the site where the electroless plating reaction occurs on the back surface and the side surface of the semiconductor substrate 15, a partial reduction in potential occurs due to the redox reaction of the electroless plating, and as a result, the variation in potential across the semiconductor substrate 15 occurs. Will be caused. This variation in potential also affects the plurality of pad electrodes 21 of the semiconductor substrate 15, resulting in non-uniform thickness of the electroless plating film on the plurality of pad electrodes 21.
A defect such as non-adhesion of plating to some of the pad electrodes 21 occurred, which was a factor of impairing the selectivity to the pad electrodes 21.

【0010】たとえ、半導体基板15裏面及び側面への
めっきレジストが塗布された半導体基板15であって
も、その半導体基板15の能動素子面のパシベーション
膜22下に形成されている内部配線(図示しない)を経
由してパッド電極21で発生した電子が移動して、他の
パッド電極との間に電位の差を生じさせることがある。
この影響により、パッド電極21が負電荷を帯びてしま
うのであるが、このパッド電極上へは金属めっきは形成
されないので、これもパッド電極21上の無電解めっき
皮膜の膜厚の不均一、一部のパッド電極21へのめっき
不着等の不良の原因となってしまう。
Even if the semiconductor substrate 15 is coated with plating resist on the back and side surfaces of the semiconductor substrate 15, internal wiring (not shown) formed under the passivation film 22 on the active element surface of the semiconductor substrate 15 is not shown. ), The electrons generated in the pad electrode 21 may move and cause a potential difference with other pad electrodes.
Due to this effect, the pad electrode 21 is negatively charged, but since metal plating is not formed on this pad electrode, this also causes non-uniformity of the film thickness of the electroless plating film on the pad electrode 21. This causes a defect such as non-adhesion of plating to the pad electrode 21 of the portion.

【0011】さらに、無電解めっき皮膜が半導体基板1
5の裏面で成長すると、半導体基板15裏面から側面を
経由して半導体基板15の能動素子面のパッシベーショ
ン膜22上にもめっき反応が伝搬してしまうので、これ
もパッド電極21上への選択性を損なう要因となってい
た。
Further, the electroless plating film has a semiconductor substrate 1
When grown on the back surface of the semiconductor substrate 5, the plating reaction also propagates from the back surface of the semiconductor substrate 15 to the passivation film 22 on the active element surface of the semiconductor substrate 15 via the side surface. Was a factor that undermines.

【0012】前記の理由により、従来の方法では半導体
基板15裏面及び側面へのめっきレジスト31の塗布は
必須であって、その上、このめっきレジスト31はめっ
き処理後に剥離工程を必要としていた。
[0012] For the above-mentioned reason, in the conventional method, it is indispensable to apply the plating resist 31 to the back surface and the side surface of the semiconductor substrate 15, and furthermore, the plating resist 31 requires a peeling step after the plating treatment.

【0013】そこで本発明の目的は、上記従来技術の課
題を改良し、半導体基板裏面及び側面にめっきレジスト
を塗布することなく、該半導体基板の複数個のパッド電
極上に均一な無電解めっき皮膜を形成する新規の方法を
提供するものである。
Therefore, an object of the present invention is to improve the above-mentioned problems of the prior art, and to form a uniform electroless plating film on a plurality of pad electrodes of a semiconductor substrate without applying a plating resist on the back and side surfaces of the semiconductor substrate. Is provided.

【0014】[0014]

【課題を解決するための手段】上記課題を解決するた
め、本発明においては下記記載の無電解めっき皮膜の形
成方法を採用する。
In order to solve the above problems, in the present invention, the following electroless plating film forming method is adopted.

【0015】すなはち、本発明において上記課題を解決
するための第1の手段は、半導体基板のパッド電極上に
無電解めっき皮膜を形成する方法であって、そのパッド
電極を選択的に活性化する工程と、前記半導体基板を無
電解めっき液に浸漬すると同時に、外部電源により前記
半導体基板に電位を印加しながら無電解めっき皮膜を析
出させる工程とを有する。さらに、第1の手段におけ
る、前記活性化する工程が、触媒付与法と亜鉛置換法の
いずれかであることが望ましい。また、第1または2の
手段における、前記半導体基板に電位を印加しながら無
電解めっき皮膜を析出させる工程において、その印加す
る電位が、めっき金属イオンの酸化還元電位と無電解め
っき液に使用される還元剤の酸化還元電位との差の値未
満の正電位であることが望ましい。
That is, the first means for solving the above problems in the present invention is a method of forming an electroless plating film on a pad electrode of a semiconductor substrate, and the pad electrode is selectively activated. And a step of immersing the semiconductor substrate in an electroless plating solution and simultaneously depositing an electroless plating film while applying a potential to the semiconductor substrate by an external power source. Further, it is desirable that the activation step in the first means is either a catalyst application method or a zinc substitution method. In the first or second means, in the step of depositing the electroless plating film while applying a potential to the semiconductor substrate, the applied potential is used for the redox potential of the plating metal ion and the electroless plating solution. It is desirable that the positive potential is less than the difference from the redox potential of the reducing agent.

【0016】(作用)本発明の無電解めっき皮膜の形成
方法は、めっき反応を部分的に抑制したい半導体基板に
対して、外部電源から正電位を印加することによって部
分的に無電解めっき皮膜の形成を抑制しながら、必要な
部分にのみ選択的に無電解めっき皮膜を形成させる方法
である。
(Function) In the method of forming an electroless plating film of the present invention, a positive potential is applied from an external power source to a semiconductor substrate whose plating reaction is to be partially suppressed, so that the electroless plating film is partially formed. It is a method of selectively forming an electroless plating film only on a necessary portion while suppressing the formation.

【0017】例として次亜燐酸塩を還元剤とした酸化還
元型の無電解ニッケルめっきについて説明する。この無
電解ニッケルめっきは、次亜燐酸イオンの酸化還元電位
である−0.80V(pH5.0、25℃、 NHE基
準)とニッケルイオン(Ni2+)の酸化還元電位である
−0.25V(pH5.0、25℃、 NHE基準)と
の差が起電力となり無電解めっき反応が開始、継続され
る。この起電力を損なわない範囲の微小電位であれば、
半導体基板を正電極として外部電源からめっき反応とは
逆の電位を印加したとしても無電解めっき反応を継続さ
せることができる。
As an example, redox electroless nickel plating using hypophosphite as a reducing agent will be described. This electroless nickel plating has a redox potential of -0.80 V (pH 5.0, 25 ° C, NHE standard) of hypophosphite ion and a -0.25 V (pH 5) of nickel ion (Ni2 +). 0.0, 25 ° C, NHE standard) becomes the electromotive force, and the electroless plating reaction starts and continues. If it is a minute potential within the range that does not impair this electromotive force,
Even if the semiconductor substrate is used as a positive electrode and a potential opposite to the plating reaction is applied from an external power source, the electroless plating reaction can be continued.

【0018】さらに、前記半導体基板内部に形成されて
いる内部配線によって複数個のパッド電極表面に電位差
を生じることがあるが、該半導体基板全体に外部電源か
ら微少な電位を印加することにより複数個のパッド電極
表面の電位を均一化することができ、均一な膜厚の無電
解めっき皮膜を得ることができる。
Further, the internal wiring formed inside the semiconductor substrate may cause a potential difference on the surface of a plurality of pad electrodes. However, by applying a minute potential from an external power source to the entire semiconductor substrate, a plurality of potential differences can be produced. The potential of the pad electrode surface can be made uniform, and an electroless plating film having a uniform film thickness can be obtained.

【0019】[0019]

【発明の実施の形態】本発明による無電解めっき皮膜の
形成方法は、半導体基板とその対極となる不溶性電極を
無電解めっき液に浸漬して、該半導体基板と該不溶性電
極との間に外部電源から一定の電位差を一定時間印加し
ながら無電解めっき皮膜を形成させる方法である。
BEST MODE FOR CARRYING OUT THE INVENTION A method for forming an electroless plating film according to the present invention is a method in which a semiconductor substrate and an insoluble electrode serving as a counter electrode thereof are immersed in an electroless plating solution to form an external layer between the semiconductor substrate and the insoluble electrode. This is a method of forming an electroless plating film while applying a constant potential difference from a power source for a fixed period of time.

【0020】以下、本発明の無電解めっき皮膜の形成方
法による半導体基板の電極形成方法について、図面を用
いて説明する。
A method for forming electrodes on a semiconductor substrate by the method for forming an electroless plating film according to the present invention will be described below with reference to the drawings.

【0021】図2(a)に示すように、従来の製造方法
と同様に半導体基板15上のアルミニウムを主成分とす
るパッド電極21と、該パッド電極21上に開口部を有
するパッシベーション膜22を形成する。さらにパッド
電極21上に形成されている自然酸化皮膜を、酸溶液あ
るいはアルカリ溶液によってエッチング除去する。その
エッチング液としては、水酸化ナトリウムの希薄溶液や
希硫酸を用いることが出来る。酸化皮膜を除去するとと
もに薄い不働態皮膜を形成させるためには硝酸を用いる
のがよい。
As shown in FIG. 2A, a pad electrode 21 containing aluminum as a main component and a passivation film 22 having an opening on the pad electrode 21 are formed on the semiconductor substrate 15 as in the conventional manufacturing method. Form. Further, the natural oxide film formed on the pad electrode 21 is removed by etching with an acid solution or an alkaline solution. As the etching solution, a dilute solution of sodium hydroxide or dilute sulfuric acid can be used. It is preferable to use nitric acid in order to remove the oxide film and form a thin passive film.

【0022】次に、図2(b)に示すように、酸化皮膜
が除去されたパッド電極21上に亜鉛置換法により亜鉛
置換皮膜23を置換析出させる。この亜鉛置換法は、イ
オン化傾向によってアルミニウムが溶出した部位にのみ
亜鉛が析出するため、アルミニウムを主成分とするパッ
ド電極21上に選択的に亜鉛置換皮膜を形成させること
ができる。具体的には、市販のジンケート処理液を用い
て室温で30秒から60秒浸漬する。次いで純水洗浄し
た後、さらに必要に応じて希硝酸等に浸漬して一度析出
した亜鉛置換皮膜23をエッチング除去した後、再度前
記ジンケート処理液に浸漬して2度目の亜鉛置換皮膜を
析出させてもよい。
Next, as shown in FIG. 2B, a zinc substitution film 23 is deposited by substitution on the pad electrode 21 from which the oxide film has been removed by the zinc substitution method. In this zinc substitution method, zinc is deposited only on the site where aluminum is eluted due to the ionization tendency, so that the zinc substitution film can be selectively formed on the pad electrode 21 containing aluminum as a main component. Specifically, it is immersed at room temperature for 30 to 60 seconds using a commercially available zincate treatment liquid. Then, after washing with pure water, if necessary, further dipping in dilute nitric acid or the like to remove the zinc substitution film 23 once deposited by etching, and then dipping in the zincate treatment liquid again to deposit a second zinc substitution film. May be.

【0023】次いで純水で洗浄した後、図1に示すよう
に半導体基板15の裏面側に外部電源11から直流電位
を印加しながら、酸化還元型の無電解ニッケルめっき液
14に浸漬するわけであるが、本実施例では対極12に
ステンレスの棒材にニッケルめっきを施したものを用
い、対極12を負電極として被めっき基板である半導体
基板15に+0.1から0.2Vの正電位を印加しなが
ら無電解ニッケルめっき液14に浸漬することにより、
図2(c)に示すような無電解ニッケルめっきによる突
起電極16の形成を行った。
Then, after washing with pure water, as shown in FIG. 1, the semiconductor substrate 15 is immersed in the redox electroless nickel plating solution 14 while applying a DC potential from the external power source 11 to the back side thereof. However, in the present embodiment, the counter electrode 12 is made of a stainless steel rod plated with nickel, and the counter electrode 12 is used as a negative electrode to apply a positive potential of +0.1 to 0.2 V to the semiconductor substrate 15, which is the substrate to be plated. By immersing in electroless nickel plating solution 14 while applying
The protruding electrodes 16 were formed by electroless nickel plating as shown in FIG. 2 (c).

【0024】めっき皮膜の形成速度は従来の方法に比べ
て遅くなるが、本発明の方法によれば、複数個のパッド
電極上に均一なめっき皮膜を形成することができる。
尚、対極12にニッケルめっきが析出することとなる
が、その反応によりパッド電極21上への無電解ニッケ
ルめっきに影響を与えるものではない。
Although the plating film formation rate is slower than that of the conventional method, the method of the present invention can form a uniform plating film on a plurality of pad electrodes.
Although nickel plating is deposited on the counter electrode 12, the reaction does not affect the electroless nickel plating on the pad electrode 21.

【0025】本実施例では、次亜燐酸塩を還元剤とする
市販の酸化還元型無電解ニッケルーリン合金めっき液を
用い、pH5.0±0.1、90℃、30分の浸漬処理
によって、半導体基板15の裏面及び側面にはめっき皮
膜を析出させることなく、該半導体基板15の全てのパ
ッド電極21上に均一な5〜6μmのニッケル突起電極
を形成させることが出来た。本発明の方法によれば、半
導体基板15を無電解めっき液14に浸漬する時間をさ
らに延長することによって、めっき皮膜がより厚い突起
電極16を形成することが可能である。
In this example, a commercially available redox electroless nickel-phosphorus alloy plating solution using hypophosphite as a reducing agent was used, and the pH was 5.0 ± 0.1 at 90 ° C. for 30 minutes. It was possible to form uniform nickel protrusion electrodes of 5 to 6 μm on all the pad electrodes 21 of the semiconductor substrate 15 without depositing a plating film on the back surface and the side surfaces of the semiconductor substrate 15. According to the method of the present invention, the projection electrode 16 having a thicker plating film can be formed by further extending the time for immersing the semiconductor substrate 15 in the electroless plating solution 14.

【0026】また本実施例では、被メッキ基板である半
導体基板15に、対極12に対して正電位を印加して無
電解めっきによる突起電極16の形成を行ったが、従来
の方法のように半導体基板15の裏面及び側面にめっき
レジストを塗布する必要はあるが、半導体基板15の複
数個のパッド電極21表面の電位を均一化することのみ
を目的として、被メッキ基板である半導体基板15に微
小の負電位を印加することもできる。
Further, in this embodiment, the positive electrode is applied to the counter electrode 12 to form the protruding electrode 16 on the semiconductor substrate 15 which is the substrate to be plated by electroless plating, but like the conventional method. Although it is necessary to apply a plating resist to the back surface and the side surface of the semiconductor substrate 15, the semiconductor substrate 15 to be plated is provided only for the purpose of equalizing the potential of the surface of the pad electrodes 21 of the semiconductor substrate 15. It is also possible to apply a small negative potential.

【0027】また、本発明の手段によれば、無電解めっ
き液の還元剤の酸化還元電位とめっき金属イオンの酸化
還元電位の差の値未満の電位差で、外部電源から半導体
基板15へ印加する電位差を選択することにより、パッ
ド電極21上に銅、コバルト、及びその合金等のめっき
皮膜も同様に形成することが可能である。
According to the means of the present invention, a potential difference less than the difference between the redox potential of the reducing agent of the electroless plating solution and the redox potential of the plating metal ions is applied to the semiconductor substrate 15 from the external power source. By selecting the potential difference, it is possible to similarly form a plating film of copper, cobalt, or an alloy thereof on the pad electrode 21.

【0028】さらに、活性化処理として亜鉛以外の他の
活性金属を置換させる方法やパラジウム等の触媒を付与
する活性化方法を用いても同様に、半導体基板15のパ
ッド電極21上に均一なめっき皮膜を形成することがで
きることは云うまでもない。
Further, even if a method of substituting an active metal other than zinc or an activation method of applying a catalyst such as palladium is used as the activation treatment, the plating on the pad electrode 21 of the semiconductor substrate 15 is similarly performed. It goes without saying that a film can be formed.

【0029】[0029]

【発明の効果】以上のように、本発明によれば半導体基
板裏面及び側面へのめっきレジスト塗布、及び後工程で
の該レジスト剥離工程を不要とし、半導体基板裏面及び
側面にめっき皮膜を析出させることなく簡単な操作で半
導体基板の複数個のパッド電極上に、均一な膜厚のバリ
アメタル、或いは突起電極を形成することができる。
As described above, according to the present invention, the plating resist is applied to the back surface and the side surface of the semiconductor substrate, and the resist stripping step in the subsequent step is unnecessary, and the plating film is deposited on the back surface and the side surface of the semiconductor substrate. It is possible to form a barrier metal or a bump electrode having a uniform film thickness on a plurality of pad electrodes of a semiconductor substrate without any operation.

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明の無電解めっき皮膜の形成方法を示す
模式図である。
FIG. 1 is a schematic view showing a method for forming an electroless plating film of the present invention.

【図2】 本発明の半導体基板への電極形成方法を示す
工程断面図である。
FIG. 2 is a process sectional view showing an electrode forming method on a semiconductor substrate of the present invention.

【図3】 従来の半導体基板への電極形成方法を示す工
程断面図である。
FIG. 3 is a process cross-sectional view showing a conventional method for forming an electrode on a semiconductor substrate.

【符号の説明】[Explanation of symbols]

11 外部電源 12 対極 13 めっき槽 14 無電解めっき液 15 半導体基板 16 突起電極 21 パッド電極 22 パッシベーション膜 23 亜鉛置換皮膜 31 めっきレジスト 11 External power supply 12 opposite poles 13 plating tank 14 Electroless plating solution 15 Semiconductor substrate 16 protruding electrode 21 Pad electrode 22 Passivation film 23 Zinc substitution film 31 Plating resist

フロントページの続き (51)Int.Cl.7 識別記号 FI テーマコート゛(参考) H01L 21/92 604M Continuation of front page (51) Int.Cl. 7 Identification code FI theme code (reference) H01L 21/92 604M

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板のパッド電極上に無電解めっ
き皮膜を形成する方法であって、そのパッド電極を選択
的に活性化する工程と、前記半導体基板を無電解めっき
液に浸漬すると同時に、外部電源により前記半導体基板
に電位を印加しながら無電解めっき皮膜を析出させる工
程とを有する無電解めっき皮膜の形成方法。
1. A method of forming an electroless plating film on a pad electrode of a semiconductor substrate, comprising the step of selectively activating the pad electrode, and immersing the semiconductor substrate in an electroless plating solution, And a step of depositing an electroless plating film while applying a potential to the semiconductor substrate by an external power source.
【請求項2】 前記活性化する工程が、触媒付与法と亜
鉛置換法のいずれかであることを特徴とする請求項1に
記載の無電解めっき皮膜の形成方法。
2. The method for forming an electroless plating film according to claim 1, wherein the activating step is either a catalyst application method or a zinc substitution method.
【請求項3】 前記半導体基板に電位を印加しながら無
電解めっき皮膜を析出させる工程において、その印加す
る電位が、めっき金属イオンの酸化還元電位と無電解め
っき液に使用される還元剤の酸化還元電位との差の値未
満の正電位であることを特徴とする請求項1または2に
記載の無電解めっき皮膜の形成方法。
3. The step of depositing an electroless plating film while applying a potential to the semiconductor substrate, wherein the applied potential is the oxidation-reduction potential of the plating metal ion and the oxidation of the reducing agent used in the electroless plating solution. The electroless plating film forming method according to claim 1 or 2, wherein the positive potential is less than the difference from the reduction potential.
JP2001288395A 2001-09-21 2001-09-21 Formation method of electroless plating film Expired - Fee Related JP4647159B2 (en)

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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8198104B2 (en) 2009-03-23 2012-06-12 Fuji Electric Co., Ltd. Method of manufacturing a semiconductor device
JP2012157833A (en) * 2011-02-01 2012-08-23 Toyota Motor Corp Method for producing catalytic fine particle, catalytic fine particle produced thereby, and catalytic fine particle-containing electrode catalyst for fuel cell
JP2012192334A (en) * 2011-03-16 2012-10-11 Toyota Motor Corp Method for manufacturing catalyst fine particle
JP2012237038A (en) * 2011-05-12 2012-12-06 Toyota Motor Corp Method for partially plating
JP2013087298A (en) * 2011-10-13 2013-05-13 Denso Corp Method for manufacturing semiconductor device
JP2015193880A (en) * 2014-03-31 2015-11-05 三菱マテリアル株式会社 Method for manufacturing power module substrate having heat sink
JP2016176098A (en) * 2015-03-19 2016-10-06 三菱マテリアル株式会社 Method for manufacturing plated power module substrate

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000038682A (en) * 1998-07-24 2000-02-08 Fujitsu Ltd Nickel plating method and semiconductor device
JP2001240976A (en) * 2000-02-29 2001-09-04 Toshiba Tec Corp Electroless plating method, method for manufacturing ink jet head and electrode substrate

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62250178A (en) * 1986-04-22 1987-10-31 Oki Electric Ind Co Ltd Initial deposition method for electroless plating
JPH03215676A (en) * 1990-01-20 1991-09-20 Tokin Corp Electroless plating agent and method for electroless plating using the same
JP3726500B2 (en) * 1997-07-28 2005-12-14 株式会社日立製作所 Wiring board, manufacturing method thereof, and electroless plating method
JPH11214421A (en) * 1997-10-13 1999-08-06 Matsushita Electric Ind Co Ltd Method for forming electrode of semiconductor element

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000038682A (en) * 1998-07-24 2000-02-08 Fujitsu Ltd Nickel plating method and semiconductor device
JP2001240976A (en) * 2000-02-29 2001-09-04 Toshiba Tec Corp Electroless plating method, method for manufacturing ink jet head and electrode substrate

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8198104B2 (en) 2009-03-23 2012-06-12 Fuji Electric Co., Ltd. Method of manufacturing a semiconductor device
JP2012157833A (en) * 2011-02-01 2012-08-23 Toyota Motor Corp Method for producing catalytic fine particle, catalytic fine particle produced thereby, and catalytic fine particle-containing electrode catalyst for fuel cell
JP2012192334A (en) * 2011-03-16 2012-10-11 Toyota Motor Corp Method for manufacturing catalyst fine particle
JP2012237038A (en) * 2011-05-12 2012-12-06 Toyota Motor Corp Method for partially plating
JP2013087298A (en) * 2011-10-13 2013-05-13 Denso Corp Method for manufacturing semiconductor device
JP2015193880A (en) * 2014-03-31 2015-11-05 三菱マテリアル株式会社 Method for manufacturing power module substrate having heat sink
JP2016176098A (en) * 2015-03-19 2016-10-06 三菱マテリアル株式会社 Method for manufacturing plated power module substrate

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