JP2003086711A - Semiconductor storage - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide at an inexpensive semiconductor storage having a large capacity. SOLUTION: In a memory cell MC included in a memory circuit 3 of a system LSI, the gate electrode 43 of an N-channel MOS transistor Q and the cell plate electrode 48 of a capacitor C are formed out of a single wiring layer. Therefore, since the system LSI can be created only in CMOS logic processes, the system LSI including the memory circuit 3 having a relatively large capacity can be created at a low cost.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device formed on a semiconductor substrate.

[0002]

2. Description of the Related Art In recent years, in a dynamic random access memory (hereinafter referred to as a DRAM), as a result of high integration, a memory cell capacitor has a complicated three-dimensional structure. In order to mount such a DRAM on a system LSI, in addition to a normal CMOS logic process, a process step for forming a capacitor of a memory cell of the DRAM and a step between a capacitor having a three-dimensional structure and a peripheral circuit section are required. A flattening step to reduce is required. Therefore, when the DRAM is mounted on the system LSI, there is a problem that the process steps are significantly increased and the chip cost is increased.

On the other hand, a memory cell of a static random access memory (hereinafter referred to as SRAM) does not have a capacitor and is formed only by a CMOS logic process. Therefore, if the SRAM is mounted on the system LSI, the problems in mounting the DRAM on the system LSI are solved.

[0004]

However, the SRAM has the following problems. That is, in the DRAM, the miniaturization of the memory cell is being advanced along with the progress of the fine processing technology, and for example, in the 0.18 μm DRAM process, the memory cell of 0.3 square μm is realized. On the other hand, in the SRAM, the memory cell has two P-channel MOs.
It is composed of an S-transistor and four N-channel MOS transistors, and is subject to restrictions on the separation distance between the P-type well and the N-type well. Reduction is not progressing. For example, an SRAM memory cell using a 0.18 μm CMOS logic process has a size of about 7 square μm, which is 20 times or more that of a DRAM memory cell. Therefore, in the SRAM, as the memory capacity increases, the chip size increases significantly, which makes it extremely difficult to mount the SRAM having a memory capacity of 4 Mbits or more on the system LSI.

For this reason, the SRAM has been conventionally used as a cache memory, a register file memory, etc. for a processor, but since a complicated memory control for refreshing data, which is indispensable for a DRAM, is unnecessary, a portable information terminal, etc. Is also used as a main memory.

However, even in the portable information terminal, the moving image has been handled and the function has been greatly improved, and a large capacity memory is required.

Therefore, a main object of the present invention is to provide a large-capacity semiconductor memory device at low cost.

[0008]

A semiconductor memory device according to the present invention is a semiconductor memory device formed on a semiconductor substrate and has a MOS transistor and a capacitor connected in series, and stores a data signal. Memory cells. The MOS transistor includes a gate insulating film formed on the surface of the semiconductor substrate, a gate electrode formed on the surface of the gate insulating film, and impurity diffusion regions formed on the surface of the semiconductor substrate on both sides of the gate electrode. Including. The capacitor includes an impurity diffusion region formed on the surface of the semiconductor substrate, an insulating film formed on the surface of the impurity diffusion region, and a flat plate electrode formed on the surface of the insulating film and receiving a reference potential. Here, the gate electrode of the MOS transistor and the plate electrode of the capacitor are formed in the same wiring layer.

Preferably, the semiconductor memory device is formed on a semiconductor substrate together with a logic circuit including MOS transistors. The gate electrode of the MOS transistor of the logic circuit, the gate electrode of the MOS transistor of the memory cell, and the plate electrode of the capacitor are formed in the same wiring layer.

Preferably, the MOS transistor of the memory cell is an N channel MOS transistor.
The semiconductor memory device further includes a word line connected to the gate of the N-channel MOS transistor, first and second bit lines of which one of them is connected to the source of the N-channel MOS transistor, and A first P-channel MOS transistor connected between the first bit line and the first node, and a second P-channel MOS transistor connected between the second bit line and the second node , And a write circuit for writing a data signal in the memory cell. The write circuit includes a step of applying a ground potential to the gates of the first and second P-channel MOS transistors to make the first and second P-channel MOS transistors conductive, and a boosted potential higher than the power supply potential on the word line. To render the N-channel MOS transistor of the memory cell conductive, and according to a write data signal externally applied, one of the first and second nodes is set to the power supply potential and the other node is set to the power supply potential. The step of bringing the node to the ground potential, and the first and second P
The step of applying a negative potential lower than the ground potential to the gate of the channel MOS transistor and applying the power supply potential to the word line is executed.

Further preferably, the absolute value of the threshold voltage of each of the first and second P-channel MOS transistors is set to be substantially equal to the voltage of the difference between the boosted potential and the power supply potential.

Preferably, two memory cells are provided and one memory cell stores one data signal.
Two word lines are provided, the gates of the N-channel MOS transistors of the two memory cells are connected to the two word lines, and the sources of the N-channel MOS transistors of the two memory cells are the first and second bits, respectively. Connected to the wire.

Preferably, two memory cells are provided and one memory cell stores one data signal.
The gates of the N-channel MOS transistors of the two memory cells are both connected to the word line, and the sources of the N-channel MOS transistors of the two memory cells are respectively the first
And a second bit line.

Preferably, the MOS transistor of the memory cell is a P channel MOS transistor. The semiconductor memory device further includes a word line connected to the gate of the P-channel MOS transistor, first and second bit lines each of which is connected to the source of the P-channel MOS transistor. A first N channel M connected between the first bit line and the first node
An OS transistor, a second N-channel MOS transistor connected between the second bit line and the second node, and a write circuit for writing a data signal in the memory cell are provided. This write circuit applies a power supply potential to the gates of the first and second N-channel MOS transistors to make the first
And a step of turning on the second N-channel MOS transistor, a step of applying a negative potential lower than the ground potential to the word line to turn on the P-channel MOS transistor of the memory cell, and a step of applying a write data signal externally applied. , A step of setting one of the first and second nodes to the power supply potential and the other node to the ground potential, the gates of the first and second N-channel MOS transistors being set to the power supply potential higher than the power supply potential. And a step of applying a ground potential to the word line while applying a high boosted potential.

Further preferably, the threshold voltages of the first and second N-channel MOS transistors are set to be substantially equal to the difference between the ground potential and the negative potential.

Further, preferably, two memory cells are provided and one memory cell stores one data signal.
Two word lines are provided, the gates of the P channel MOS transistors of the two memory cells are respectively connected to the two word lines, and the sources of the P channel MOS transistors of the two memory cells are the first and second bits, respectively. Connected to the wire.

Further, preferably, two memory cells are provided and one memory cell stores one data signal.
The gates of the P-channel MOS transistors of the two memory cells are both connected to the word line, and the sources of the P-channel MOS transistors of the two memory cells are respectively the first
And a second bit line.

Further preferably, the MOS transistor of the memory cell is an N channel MOS transistor. The semiconductor memory device further includes a word line connected to the gate of the N-channel MOS transistor, first and second bit lines each of which is connected to the source of the N-channel MOS transistor, and a memory. And a write circuit for writing a data signal in the cell. This writing circuit applies a boosted potential higher than a power supply potential to a word line to make an N-channel MOS transistor of a memory cell conductive, a step of applying a power supply potential to first and second bit lines, and a word line. According to the step of applying the power supply potential to the
The step of setting one of the first and second bit lines to the power supply potential and the other bit line to the ground potential is executed.

Further, preferably, two memory cells are provided and one memory cell stores one data signal.
Two word lines are provided, the gates of the N-channel MOS transistors of the two memory cells are connected to the two word lines, and the sources of the N-channel MOS transistors of the two memory cells are the first and second bits, respectively. Connected to the wire.

Further, preferably, two memory cells are provided and one memory cell stores one data signal.
The gates of the N-channel MOS transistors of the two memory cells are both connected to the word line, and the sources of the N-channel MOS transistors of the two memory cells are respectively the first
And a second bit line.

Further preferably, the MOS transistor of the memory cell is a P-channel MOS transistor. The semiconductor memory device further includes a word line connected to the gate of the P-channel MOS transistor, first and second bit lines in which one of them is connected to the source of the P-channel MOS transistor, and a memory. And a write circuit for writing a data signal in the cell. This write circuit applies a negative potential lower than a ground potential to a word line to render an N-channel MOS transistor of a memory cell conductive, a step of applying a ground potential to first and second bit lines, and a word line. To one of the first and second bit lines to the power supply potential and the other bit line to the ground potential according to the step of applying the ground potential to the Perform steps and

Further, preferably, two memory cells are provided and one memory cell stores one data signal.
Two word lines are provided, the gates of the P channel MOS transistors of the two memory cells are respectively connected to the two word lines, and the sources of the P channel MOS transistors of the two memory cells are the first and second bits, respectively. Connected to the wire.

Further, preferably, two memory cells are provided and one memory cell stores one data signal.
The gates of the P-channel MOS transistors of the two memory cells are both connected to the word line, and the sources of the P-channel MOS transistors of the two memory cells are respectively the first
And a second bit line.

Further, preferably, two memory cells are provided, and two memory cells store one data signal.
The MOS transistor of one of the two memory cells is an N-channel MOS transistor, and the MOS transistor of the other memory cell is a P-channel MO transistor.
It is an S transistor. The semiconductor memory device further includes a gate of an N-channel MOS transistor and a P-channel MOS transistor, respectively.
First connected to gate of channel MOS transistor
And a second word line, first and second bit lines, one of which is connected to the source of the N-channel MOS transistor and the source of the P-channel MOS transistor, and a data signal to two memory cells. And a writing circuit for writing. This write circuit applies a power supply potential and a ground potential to the first and second word lines respectively to render the N-channel MOS transistor and the P-channel MOS transistor conductive, and according to a write data signal applied from the outside, The step of setting one of the first and second bit lines to the power supply potential and the other bit line to the ground potential is executed.

[0025]

[First Embodiment] FIG. 1 is a block diagram showing a configuration of a system LSI 1 according to a first embodiment of the present invention. In FIG. 1, this system LSI
1 includes a logic circuit unit 2 and a memory circuit unit 3 formed on a single silicon substrate.

The logic circuit section 2 has an external clock signal C.
It operates in synchronization with LK and has external control signals CNT0 to CNT.
A predetermined operation is performed according to m and external data signals D0 to Dn (where m and n are integers of 0 or more). The memory circuit unit 3 is controlled by the logic circuit unit 2,
The data given from the logic circuit unit 2 is stored and the read data is given to the logic circuit unit 2.

FIG. 2 is a block diagram showing the configuration of the memory circuit section 3 shown in FIG. In FIG. 2, the memory circuit unit 3 is composed of a synchronous DRAM, and has a clock buffer 4, a control signal buffer 5, an address buffer 6, a control circuit 8 and four memory arrays 9 to 12 (banks # 0 to # 3). , And an IO buffer 13.

The clock buffer 4 includes the logic circuit section 2
Is activated by a control signal CKE from C.sub.1 to transmit an external clock signal CLK to control signal buffer 5, address buffer 6 and control circuit 8. Control signal buffer 5
Is an external clock signal CLK from the clock buffer 4.
In synchronization with the control signal / CS from the logic circuit unit 2,
/ RAS, / CAS, / WE, DQM are latched and given to the control circuit 8. The address buffer 6 is synchronized with the external clock signal CLK from the clock buffer 4, and the address signals A0 to Ai from the logic circuit unit 2 (however,
i is an integer of 0 or more) and the bank selection signal BA
0 and BA1 are latched and given to the control circuit 8.

Each of memory arrays 9 to 12 includes a plurality of memory cells arranged in a matrix and each storing 1-bit data. The plurality of memory cells are previously j + 1
Each group (where j is an integer of 0 or more) is grouped.

The control circuit 8 generates various internal signals according to the signals from the clock buffer 4, the control signal buffer 5 and the address buffer 6 and controls the entire memory circuit section 3. Control circuit 8 selects one of the four memory arrays 9 to 12 according to bank select signals BA0 and BA1 during the write operation and the read operation, and the memory array according to address signals A0 to Ai. Of these, j + 1 memory cells are selected. The selected j + 1 memory cells are activated and coupled to the IO buffer 13.

IO buffer 13 applies externally applied data D0-Dj to selected j + 1 memory cells during a write operation, and read data Q0-Qj of j + 1 memory cells during a read operation. Output to the outside.

FIG. 3 is a block diagram showing a configuration of the memory array 9 shown in FIG. 2 and a portion related thereto. Figure 3
In, the memory array 9 has a plurality of memory array blocks MA0 to MAk (where k is an integer of 0 or more).
Is divided into a plurality of memory array blocks MA0 to MA
A plurality of sense amplifier bands SA0 to S on both sides of k
Ak + 1 is arranged. Memory array block MA0
MAk and sense amplifier bands SA0 to SAk + 1 form a rectangular memory mat 14.

The memory array block MAk includes a plurality of memory cells MC arranged in a matrix as shown in FIG.
And a word line WL provided corresponding to each row and a bit line pair BL, / BL provided corresponding to each column.
This memory cell MC is arranged at any one of two intersections of two bit lines BL, / BL and one word line WL orthogonal thereto.

Each memory cell MC includes an N-channel MOS transistor Q for access and a capacitor C for information storage.
Including and N channel MOS transistor Q and capacitor C are connected in series between corresponding bit line BL or / BL and the line of cell potential VCP, and N channel M transistor Q and capacitor C are connected in series.
The gate of the OS transistor Q is connected to the corresponding word line WL. The node between N-channel MOS transistor Q and capacitor C is called storage node SN.

As shown in FIG. 5, sense amplifier band SAk includes data input / output line pair IO, / IO, column select line CSL provided corresponding to each odd column of memory array block MAk, and transfer gate 21. , 36, a column selection gate 24, a sense amplifier 27, and an equalizer 32. Transfer gate 2 on each even column of memory array block MAk
1, 36, the column selection gate 24, the sense amplifier 27, and the equalizer 32 are provided in the sense amplifier band SAk + 1.

Transfer gate 21 includes P channel MOS transistors 22 and 23. P channel MOS transistors 22 and 23 are connected between input / output nodes N1 and N2 of sense amplifier 27 and corresponding bit line pair BL and / BL of memory array block MAk-1, respectively, and their gates are block select signals. Receive BLIR.

Transfer gate 36 includes P channel MOS transistors 37 and 38. P-channel MOS transistors 37 and 38 are provided for I / O nodes N1 and N2 and corresponding bit line pairs BL and BL of memory array block MAk, respectively.
/ BL, and its gate receives a block selection signal BLIL.

The circuits in the sense amplifier band SAk are shared by the two memory array blocks MAk-1 and MAk on both sides thereof. When memory array block MAk is selected, signal BLIR is at the "H" level and transfer gate 21 is cut off. When memory array block MAk-1 is selected, signal BLIL is at the "H" level. The transfer gate 36 is cut off.

Column select gate 24 includes N channel MOS transistors 25 and 26 connected between input / output nodes N1 and N2 and data input / output lines IO and / IO, respectively. The gates of N-channel MOS transistors 25 and 26 are connected to column select line CSL. When the column selection line CSL is raised to the selection level "H" level, the N channel M
The OS transistors 25 and 26 become conductive, and the input / output node N
1, N2, that is, the bit line pair BL, / BL of the memory array block MAk-1 or MAk and the data input / output line pair IO, / IO are coupled. Data input / output line pair IO,
The other end of / IO is connected to one end of global data input / output line pair GIO, / GIO via a block selection switch (not shown). Global data input / output line pair GIO,
The other end of / GIO is connected to IO buffer 13 via a preamplifier / write driver and a data bus.

Sense amplifier 27 is connected between input / output nodes N1 and N2 and node N3, and P-channel MOS transistors 28 and 29 connected between input / output nodes N1 and N2 and node N4, respectively. And N-channel MOS transistors 30 and 31. The gates of MOS transistors 28 and 30 are both connected to node N2, and the gates of MOS transistors 29 and 31 are both connected to node N1. Nodes N3 and N4 receive sense amplifier activation signals SE and / SE, respectively. The sense amplifier 27 uses the sense amplifier activation signals SE and / S.
In response to E becoming "H" level and "L" level, respectively, the bit line pair BL, between the nodes N1 and N2, that is, the memory array block MAk-1 or MAk.
A small potential difference between / BL is amplified to the power supply voltage VCC.

The equalizer 32 includes input / output nodes N1 and N1.
N-channel MOS transistor 33 connected between 2
And N-channel MOS transistors 34 and 3 connected between the input / output nodes N1 and N2 and the node N6, respectively.
Including 5 and. N-channel MOS transistors 33-35
Are both connected to the node N5. Node N5
Receives the bit line equalize signal BLEQ and receives the node N6
Receives a bit line precharge potential VBL (= VCC / 2). The equalizer 32 uses the bit line equalize signal B.
In response to the activation level "L" of LEQ, the potential difference between nodes N1 and N2, that is, bit lines BL and / B of memory array block MAk-1 or MAk.
The potential difference of L is equalized to the bit line precharge potential VBL.

Returning to FIG. 3, the rectangular memory mat 14 is used.
The row decoders 15 are arranged along the long sides of the columns and the column decoders 16 are arranged along the short sides of the memory mats 14. Row decoder 15 includes row address signals RA0-RAi (address signals A0-A when signal / RAS is at "L" level).
i), a plurality of memory array blocks MA0 to M
Any memory array block (eg, MAk) of Ak and any one of the plurality of word lines WL belonging to the memory array block MAk
Are selected, and the word line WL is set to the selection level "H" level to activate the corresponding memory cells MC.

The column decoder 16 receives the column address signal CA0.
.About.CAi '(address signals A0 to Ai' when signal / CAS is at "L" level), a plurality of column selection lines CS
One of the L column selection lines CSL is selected, and the column selection line CSL is set to the “H” level of the selection level to turn on the corresponding column selection gate 24. However, i'is an integer of 0 or more and i or less.

Next, the memory circuit section 3 shown in FIGS.
The operation of will be described. In the standby mode, the signals BLIR and BLIL are both at the “L” level, the signal BLEQ is at the “H” level, the signals SE and / SE are both at the intermediate level (VCC / 2), and the bit line BL , / BL are equalized to the bit line precharge potential VBL. Further, the word line WL and the column selection line CSL are at the “L” level which is the non-selection level.

In the write mode, the bit line equalize signal BLEQ is first lowered to the "L" level,
Equalization of bit lines BL and / BL is stopped. Then, the row decoder 15 causes the row address signals RA0 to RA0.
A memory array block (for example, MAk) designated by RAi is selected, signals BLIR and BLIL are set to “H” level and “L” level, respectively, and memory array block MAk and sense amplifier bands SAk and SAk are set.
+1 and are combined. Also, by the row decoder 15,
Word line W in a row corresponding to row address signals RA0-RAi
L is raised to the selected level of "H", and N channel MOS transistor Q of memory cell MC in that row is rendered conductive.

Next, the column decoder 16 causes the column selection line CSL of the column corresponding to the column address signals CA0 to CAi '.
Is raised to the selection level of "H", and the selection gate 24 of that column is rendered conductive. The write data signal Di supplied from the logic circuit section 2 is applied to the bit line pair of the column selected via the IO buffer 13, the global data input / output line pair GIO, / GIO and the data input / output line pair IO, / IO. Given to BL, / BL. In accordance with the write data signal Dj, the sense amplifier 27 causes the potentials of the bit lines BL and / BL to have a full amplitude. The potential (“H”) of the bit line BL or / BL is applied to the capacitor C of the selected memory cell MC.
The amount of electric charge corresponding to the level or the “L” level) is stored.

In the read mode, the bit line equalize signal BLEQ is first lowered to the "L" level,
Equalization of bit lines BL and / BL is stopped. Next, for example, memory array block MAk is selected by row decoder 15 and signals BLIR and BLIL are set to “H” level and “L” level, respectively, and memory array block MAk and sense amplifier bands SAk and SAk are set.
+1 is coupled and row address signals RA0 to RA
The word line WL in the row corresponding to Ai is at the selection level "H"
Can be raised to a level. As a result, the bit lines BL, /
The potential of BL changes by a minute amount according to the charge amount of the capacitor C of the activated memory cell MC.

Then, the sense amplifier activation signals SE, /
SE becomes "H" level and "L" level, respectively, and the sense amplifier 27 is activated. When the potential of the bit line BL is slightly higher than the potential of the bit line / BL, the resistance values of the MOS transistors 28 and 31 become smaller than the resistance values of the MOS transistors 29 and 30, and the potential of the bit line BL becomes " The potential of bit line / BL is lowered to the "L" level (ground potential GND) while being raised to the "H" level (power supply potential VCC).
Conversely, when the potential of the bit line / BL is slightly higher than the potential of the bit line BL, the MOS transistors 29, 30
Becomes smaller than the resistance values of the MOS transistors 28 and 30, the potential of the bit line / BL is raised to the "H" level and the potential of the bit line BL is lowered to the "L" level.

Next, the column decoder 16 raises the column selection line CSL of the column corresponding to the column address signals CA0 to CAi to the "H" level of the selection level, and the column selection gate 24 of that column is rendered conductive. Bit line pair B of the selected column
The data signals Qj of L and / BL are output to the logic circuit section 2 through the column selection gate 21, the data input / output line pair IO, / IO, the global data input / output line pair GIO, / GIO, and the IO buffer 13. .

The memory cell M, which is a feature of the present invention, will be described below.
The configuration of C and the method of writing data will be described in detail. 6A and 6B are diagrams showing the configuration of the memory cell MC of the memory circuit unit 3. FIG. 6B is the same as FIG.
It is the ZZ 'sectional view taken on the line of (a), and the bit line BL is abbreviate | omitted in FIG. 6 (a).

In FIGS. 6A and 6B, P-type wells 41 are formed on both sides of the crystalline silicon substrate 40, and N-channel MOS transistors Q and capacitors C are formed on the surfaces of the P-type wells 41. In the N-channel MOS transistor Q, a gate electrode 43 is formed on the surface of a P-type well 41 via a gate insulating film 42, and a source region 44 and a drain region 45 are formed on both sides of the gate electrode 43. The gate electrode 43 constitutes a part of the word line WL.
The source region 44 and the drain region 45 are composed of N-type diffusion layers. The capacitor C has a so-called planar type capacitor structure, and an N-type capacitor is formed on the surface of the P-type well 41.
Type diffusion layer (or inversion layer) 46 (storage node S
N) is formed, and the cell plate electrode 48 is formed on the surface thereof via the insulating layer 47.

Here, the N channel MO of the memory cell MC
The gate electrode 43 (word line WL) of the S transistor Q and the cell plate electrode 48 of the capacitor C are formed in the same wiring layer. This wiring layer may be formed of polycrystalline silicon (doped polysilicon) having impurities introduced therein, or may be formed of polycide using WSix, CoSix, or the like, or formed by a so-called salicide technique. Good. This wiring layer is also used as the gate electrode of the MOS transistor in the CMOS logic process.

Above the N-channel MOS transistor Q and the capacitor C, a bit line B is provided via an insulating layer 49.
L is formed. Such a structure is called a CBU structure. The bit line BL is formed of the first metal wiring layer. Source region 44 of N-channel MOS transistor Q
Are connected to the bit line BL via the contact hole 50.

The plurality of memory cells MC connected to one bit line BL are grouped in groups of two. The two memory cells MC forming a pair have an N channel M
The source region 44 and the contact hole 50 of the OS transistor Q are provided in common. The memory cell MC connected to the bit line BL and the memory cell MC connected to another bit line / BL are separated by the element separation layer 51.

In the first embodiment, firstly, since the planar type capacitor C is adopted and the cell plate electrode 48 and the word line WL are formed in the same wiring layer, the cell plate electrode and the storage node are formed. It is not necessary to separately provide a wiring layer of, and a step does not occur between the memory arrays 9 to 12 and the peripheral circuit section. Therefore, the system LSI 1 can be formed only by the CMOS logic process, and the cost of the system LSI 1 can be reduced.

By the way, the data signal of "H" level (power supply potential VCC) is sufficiently written in the storage node SN of the memory cell MC, or the data signal of "H" level is sufficiently written from the storage node SN of the memory cell MC. For reading, a potential VPP sufficiently higher than a potential VCC + Vtn obtained by adding the threshold voltage Vtn of the N-channel MOS transistor Q of the memory cell MC to the power supply potential VCC.
Must be applied to the word line WL. As shown in FIG. 7, the boosted potential VPP is applied to the word line WL, and the bit line BL is grounded by the sense amplifier 27 to the ground potential GND (0
V), Vgs = VPP is applied to the gate insulating film of the N-channel MOS transistor Q. Therefore, the film thickness of the gate insulating film of N channel MOS transistor Q must be set thick so as to withstand high voltage VPP. On the other hand, the insulating film of the capacitor C needs to be thin so that a large capacitance can be obtained.

For this purpose, a dual gate insulating film process in which gate insulating films having different film thicknesses are mixed is adopted,
As shown in FIG. 8, it is necessary to form a thick insulating film in the region A of the N-channel MOS transistor Q and a thin insulating film in the region of the capacitor C. However, if such a structure is adopted, it is necessary to increase the distance between the word line WL and the cell plate electrode 48, and the memory cell M
The size of C will increase.

Therefore, in the first embodiment, secondly,
A data writing method is adopted so that even if the gate insulating film 42 of the N-channel MOS transistor Q is set to have the same thin film thickness as the insulating film 47 of the capacitor C, the gate insulating film 42 of the N-channel MOS transistor Q is not broken down. , To prevent the memory cell MC from increasing in size.

FIG. 9 is a circuit diagram showing the structure of the word driver 55 of the memory circuit section 3. Word driver 5
Reference numeral 5 denotes a circuit included in the row decoder 15 of FIG. 3, which is provided corresponding to each word line WL. The word driver 55 includes a level shifter 56, a switching circuit 57 and an inverter 58.

The level shifter 56 outputs the signal Xa whose "H" level is the power supply potential VCC and whose "L" level is the ground potential GND.
Is converted into a signal in which the “H” level is the boosted potential VPP and the “L” level is the ground potential GND, and the signal is further inverted. Signal Xa is a signal which is predecoded and activated when row address signals RA0 to RAi designating a corresponding word line WL are input.

That is, level shifter 56 includes P channel MOS transistors 59 and 60, N channel MOS transistors 64 and 65, and an inverter 67. P channel MOS transistors 59 and 60 are connected between the line of boosted potential VPP and nodes N59 and N60, respectively, and their gates are connected to nodes N60 and N59, respectively.
Connected to. N-channel MOS transistors 64, 6
5 is the nodes N59 and N60 and the ground potential GND, respectively.
Connected between the line and. The signal Xa is directly input to the gate of the N-channel MOS transistor 64 and also input to the gate of the N-channel MOS transistor 65 via the inverter 67. The signal appearing at node N59 becomes the output signal φP of level shifter 56.

When signal Xa is at the inactive level of "L", N channel MOS transistor 64 is rendered non-conductive and N channel MOS transistor 65 is rendered conductive. As a result, node N60 attains the "L" level to render P channel MOS transistor 59 conductive, and the potential of node N59, that is, signal φP attains boosted potential VPP, rendering P channel MOS transistor 60 non-conductive.

When signal Xa is at the active level of "H", N channel MOS transistor 64 is rendered conductive and N channel MOS transistor 65 is rendered non-conductive. As a result, the signal φP becomes the “L” level and P
The channel MOS transistor 60 becomes conductive, and the node N6
0 becomes the boosted potential VPP and the P-channel MOS transistor 59 becomes non-conductive.

Switching circuit 57 includes P channel MOS transistors 61 and 62 and an inverter 68. P-channel MOS transistor 61 is connected between the line of boosted potential VPP and power supply node N63 of inverter 58. P channel MOS transistor 62 is connected between the line of power supply potential VCC and power supply node N63 of inverter 58. The signal φACT is a P channel MOS
It is directly input to the gate of the transistor 61 and
It is input to the gate of the P-channel MOS transistor 62 via the inverter 68.

When the signal φACT is at "H" level, P
Channel MOS transistor 61 is rendered non-conductive, P channel MOS transistor 62 is rendered conductive, and power supply potential VCC is applied to power supply node N63 of inverter 58. When signal φACT is at "L" level, P-channel MOS transistor 61 becomes conductive and P-channel MOS transistor 62 becomes non-conductive, and boosted potential V
PP is applied to power supply node N63 of inverter 58.

Inverter 58 includes P channel MOS transistor 63 and N channel MOS transistor 66.
including. P channel MOS transistor 63 is connected between power supply node N63 and corresponding word line WL, and its gate receives output signal φP of level shifter 56. N
The channel MOS transistor 66 has a corresponding word line W.
It is connected between L and the line of ground potential GND, and its gate receives signal φP.

When signal φP is at "L" level, P-channel MOS transistor 63 is rendered conductive and N-channel MOS transistor 66 is rendered non-conductive, and potential VPP or VCC of power supply node N63 is applied to word line WL. When signal φP is at "H" level, P-channel MOS transistor 63 becomes non-conductive, N-channel MOS transistor 66 becomes conductive, and ground potential GN
D is applied to word line WL.

FIG. 10 shows the word driver 5 shown in FIG.
6 is a time chart showing the operation of FIG. In the standby state, signal φACT is at the “H” level, P-channel MOS transistor 61 becomes non-conductive and P-channel MOS transistor 62 becomes conductive, and power supply potential VCC is applied to power supply node N63 of inverter 58. ing. Further, the signal Xa is set to the “L” level, the signal φP becomes the boosted potential VPP, and the P channel MO
The S-transistor 63 becomes non-conductive, the N-channel MOS transistor 66 becomes conductive, and the word line WL is set to the ground potential GND.

At a certain time, control signals / RAS, / CA
When an active command ACT is input by S, ..., The selected memory array block (for example, MA
In k), signal φACT falls to "L" level. As a result, P-channel MOS transistor 61 becomes conductive and P-channel MOS transistor 62 becomes non-conductive, and boosted potential VPP is applied to power supply node N63 of inverter 58.

After a lapse of a predetermined time from the input of active command ACT, signal Xa is raised to the activation level "H" level and signal φP is lowered to "L" level. As a result, the N-channel MOS transistor 66
Becomes non-conductive, the P-channel MOS transistor 63 becomes conductive, and the word line WL is set to the boosted potential VPP.

In this memory circuit section 3, as shown in FIG. 11, a local control circuit 70 is provided corresponding to each memory array block MA, and each sense amplifier band SA is provided.
Two signal generating circuits 71 and 72 are provided corresponding to the above. In FIG. 11, memory array blocks MAk-1, Mk
The local control circuits 70. k-
1,70. k are provided, and signal generation circuits 71.k are provided corresponding to sense amplifier band SAk. k, 72. The state in which k is provided is shown.

Local control circuit 70. k-1 is signal φE in response to selection of corresponding memory array block MAk-1 by row address signals RA0 to RAi.
Each of k−1 and φFk−1 is set to the activation level “H” level at a predetermined timing.

Local control circuit 70. k corresponds to signals φEk and φF in response to selection of corresponding memory array block MAk by row address signals RA0 to RAi.
Each of k is set to an activation level of "H" at a predetermined timing.

Signal generating circuit 71. k is the signal φEk, φ
When Fk-1 is at the "L" level, the signal BLIR is set to the ground potential GND, and when the signal φEk is set to the "H" level, the signal BLIR is set to the power supply potential VCC and the signal φFk-1 is set.
Is set to the “H” level, the signal BLIR is set to the negative potential V
Turn it into BB.

Signal generating circuit 72. k is the signal φEk−
1, when φFk is at the “L” level, the signal BLIL is set to the ground potential GND, and when the signal φEk−1 is set to the “H” level, the signal BLIL is set to the power supply potential VCC, and the signal φF is set.
When k is set to "H" level, signal BLIL is set to negative potential VBB.

FIG. 12 shows signal generation circuits 71. It is a circuit block diagram which shows the structure of k. 12, signal generation circuits 71. k is an inverter 73, 74, P channel M
It includes an OS transistor 75, N channel MOS transistors 76 to 78 and a level shifter 79. MOS transistors 75 to 77 are connected in series between the line of power supply potential VCC and the line of ground potential GND. The N-channel MOS transistor 78 is the MOS transistor 7
It is connected between node N78 between 5 and 76 and the line of negative potential VBB. The signal φEk is input to the gates of the MOS transistors 75 and 76 via the inverter 73. Signal φFk−1 is input to the gate of N channel MOS transistor 77 via inverter 74 and to the gate of N channel MOS transistor 78 via level shifter 79. Note that the negative potential VB
B may be the same as the potential applied to the P-type well 41 in FIG. 6 or may be a different potential level.

The level shifter 79 outputs a signal φF whose “H” level is the power supply potential VCC and whose “L” level is the ground potential GND.
k-1 is converted into a signal φ79 in which the "H" level is the power supply potential VCC and the "L" level is the negative potential VBB.

That is, as shown in FIG. 13, the level shifter 79 includes P-channel MOS transistors 80 and 81,
Includes N channel MOS transistors 82 and 83 and an inverter 84. P-channel MOS transistor 80,
81 denotes a line of the power supply potential VCC and a node N8, respectively.
0, N81. The signal φFk−1 is P
It is directly input to the gate of the channel MOS transistor 80, and also a P channel MO
It is input to the gate of the S transistor 81. N-channel MOS transistors 82 and 83 are connected to node N8, respectively.
Connected between 0, N81 and the line of negative potential VBB,
Their gates are connected to nodes N81 and N80, respectively. The signal appearing at node N81 becomes the output signal φ79 of level shifter 79.

When the signal φFk-1 is at "L" level,
P-channel MOS transistor 80 becomes conductive and P-channel MOS transistor 81 becomes non-conductive. As a result, the node N80 goes high and the N-channel MOS transistor 83 becomes conductive, and the node N81 goes low (negative potential VBB) to bring the N-channel MO transistor into operation.
The S transistor 82 becomes non-conductive. Therefore, the signal φ79 becomes the negative potential VBB.

When the signal φFk-1 is at "H" level,
The P-channel MOS transistor 80 becomes non-conductive and the P-channel MOS transistor 81 becomes conductive. This causes the node N81 to go to the “H” level (power supply potential VC
C), the N-channel MOS transistor 82 becomes conductive, the node N80 goes to "L" level and the N-channel M
The OS transistor 83 becomes non-conductive. Therefore, the signal φ79 becomes the power supply potential VCC.

Returning to FIG. 12, the signals φEk, φFk−1.
Are both at the "L" level, the N-channel MOS transistors 76 and 77 are turned on and the P-channel MO transistor is turned on.
S transistor 75 and N channel MOS transistor 78 are rendered non-conductive, and signal BLIR is at ground potential GND.
become. When signals φEk and φFk−1 are at “H” level and “L” level, respectively, P-channel MOS transistor 75 and N-channel MOS transistor 77.
Is turned on and the N-channel MOS transistor 7 is turned on.
6, 78 become non-conductive, the signal BLIR is the power supply potential VC
Become C. When signals .phi.Ek and .phi.Fk-1 are at "L" level and "H" level, respectively, N-channel MOS transistors 76 and 78 become conductive and P-channel M.
The OS transistor 75 and the N-channel MOS transistor 77 become non-conductive, and the signal BLIR has the negative potential VBB.
become. Signals .phi.Ek and .phi.Fk-1 are not both at "H" level.

Signal generating circuit 72. 14, the signal generating circuits 71.k. It has the same configuration as k. However, instead of the signals φEk and φFk−1, the signal φ
Ek-1, φFk are input, and the signal BLIL is output instead of the signal BLIR. When signals φEk−1 and φFk are both at “L” level, signal BLIL is at ground potential G
ND, and signals φEk−1 and φFk are “H” respectively.
Signal BLIL becomes power supply potential VCC in the case of level and "L" level, and signal BLIL in the case of signals .phi.Ek-1 and .phi.Fk being "L" level and "H" level, respectively.
Becomes a negative potential VBB. Both signals φEk−1 and φFk never go to the “H” level.

FIG. 15 shows the local control circuit 70. k-
1,70. k and signal generation circuit 71. k, 72. It is a time chart which shows operation | movement of k. Row address signal RA
A case where the memory array block MAk is selected by 0 to RAi will be described.

In the standby state, the signals φEk−1, φ
Ek, φFk−1, and φFk are both set to the “L” level, and signals BLIR and BLIL are both at ground potential GN.
It is set to D. Active command ACT at a certain time
Is input and the memory array block MAk is selected, the local control circuit 70. signal .phi.Ek is raised to "H" level by k, and signal generation circuit 71.k. The signal BLIR is raised to the power supply potential VCC by k. Then, when precharge command PRE is input, local control circuit 70. The signal φFk is raised to the “H” level by the signal k. The signal BLIL falls to the negative potential VBB by k. When a predetermined time elapses after the precharge command PRE is input, both signals φEk and φFk are lowered to the “L” level, and both signals BLIR and BLIL are ground potential GND.
become.

FIG. 16 is a time chart showing a data writing method of the memory circuit section 3 shown in FIGS.
In FIG. 16, in the standby state, the word line WL is set to the ground potential GND and the N channel M of the memory cell MC.
The OS transistor Q is non-conductive. The storage node SN of the memory cell MC holds the power supply potential VCC or the ground potential GND. Also, the signal BLI
Both R and BLIL are set to the ground potential GND, and the transfer gates 21 and 36 in FIG. 5 are both conductive. Further, the signal BLEQ is set to the “H” level, and the bit line pair BL, / BL is equalized to the bit line precharge potential VBL = VCC / 2 by the equalizer 32 of FIG.

When an active command ACT is input at a certain time and, for example, memory array block MAk is selected, signal BLIR is raised to "H" level, transfer gate 21 in FIG. Amplifier 2
7 is separated from the memory array block MAk-1. Further, the signal BLEQ is set to the “L” level, and equalization of the potentials of the bit lines BL and / BL is stopped.

Next, word line WL in the row corresponding to row address signals RA0-RAi is raised to boosted potential VPP. As a result, the N-channel MOS transistor Q of the memory cell MC connected to the word line WL becomes conductive,
A minute potential difference is generated between the bit line pair BL, / BL according to the data stored in the memory cell MC. At this time, for example, the potential of the bit line BL is set to be slightly higher than the potential of the bit line / BL. Then, the sense amplifier activation signals SE and / SE of FIG. 5 are set to the “H” level and the “L” level, respectively, to activate the sense amplifier 27,
The minute potential difference between the nodes N1 and N2 is amplified to the power supply voltage VCC.

At this time, nodes N1 and N2 are set to power supply potential VCC and ground potential GND, respectively, but bit lines BL and / BL are set to power supply potential VCC and threshold voltage | Vtp | of P channel MOS transistor 38, respectively.
Becomes This is because even if node N1 and signal BLIL are set to ground potential GND, P channel MOS transistor 38 becomes non-conductive when bit line / BL attains | Vtp |.

Therefore, as shown in FIG. 17A, the maximum voltage Vgs applied to the gate insulating film of the N-channel MOS transistor Q of the memory cell MC is Vgs = VPP.
-| Vtp | is suppressed. P of transfer gates 21 and 36
The threshold voltage | Vtp | of the channel MOS transistors 22, 23, 37, 38 is VPP- | Vtp | ≈VC
It is set to be C. Therefore, the memory cell MC
Even if the gate insulating film of the N-channel MOS transistor Q has the same thin film thickness as the insulating film of the capacitor C, there is no problem in reliability.

Then, the column selection line CSL of the column corresponding to the column address signals CA0 to CAi is raised to the selection level "H" level, and the column selection gate 24 of FIG. 5 is rendered conductive. Then, according to the write data signal, the data input / output line pair IO, / I
One data input / output line (for example, / IO) of O is set to "H" level, and the other data input / output line (IO in this case) is set to "L" level. In response, sense amplifier 27 raises node N2 to power supply potential VCC and lowers node N1 to ground voltage GND.
Even at this time, the nodes N1 and N2 are respectively connected to the ground voltage G
ND and power supply potential VCC, but bit lines BL, /
BL becomes the threshold voltage | Vtp | of P channel MOS transistor 37 and power supply potential VCC, respectively. Therefore, the voltage Vgs applied to the gate insulating film of the N-channel MOS transistor Q of the memory cell MC is the maximum Vg.
It is suppressed to s = VPP- | Vtp |.

During this period, when the "H" level is written to the storage node SN of the memory cell MC, the storage node SN can be set to the power supply potential VCC and "H".
Can write enough level data. But,
When data of "L" level is written, storage node SN cannot be set to ground potential GND and data writing becomes insufficient. Therefore, next, "L" level restore is performed.

That is, the precharge command PRE is input to the word line WL from the boosted potential VPP to the power supply potential VPP.
The signal BLIL is lowered to CC and the ground potential GND is applied.
To the negative potential VBB. As a result, the P-channel MOS transistor 37 of the transfer gate 36 of FIG. 5 becomes conductive again, and the bit line BL and the storage node SN fall to the ground potential GND. At this time, as shown in FIG.
As shown in (b), the N channel MO of the memory cell MC
The voltage Vg applied to the gate insulating film of the S transistor Q
Since s is Vgs = VCC, there is no risk of dielectric breakdown of the gate insulating film.

The period for restoring the "L" level can be short. When the "L" level restore is completed, the word line WL is raised to the "L" level, the N-channel MOS transistor Q of the memory cell MC becomes non-conductive, and the level of the storage node SN is maintained. Also the signal BL
Both IR and BLIL are set to the ground potential GND, the transfer gates 21 and 36 are rendered conductive, the signals SE and / SE are both set to the bit line precharge potential level (VCC / 2), and the sense amplifier 27 is deactivated. Signal BLEQ is set to "H" level and bit line pair BL, / BL is equalized to bit line potential VBL.

In the first embodiment, VPP- | Vtp
| ≈VCC, the gate insulating film of the N-channel MOS transistor Q of the memory cell MC is changed to the capacitor C.
The film thickness can be made the same as that of the insulating film, and a small size memory cell MC can be formed. In addition, since "L" level restoration is performed after data writing,
The level of the data signal can be sufficiently written in the storage node SN of the memory cell MC.

In the first embodiment, boosted potential VPP is applied to one word line WL and one bit line BL.
Alternatively, "H" level or "L" level is written in one memory cell MC connected to / BL to store 1-bit data. However, according to the present invention, as shown in FIG. 18, the boosted potential VPP is applied to the two word lines WL,
By writing the “H” level to one of the two memory cells MC connected to the bit lines BL and / BL and writing the “L” level to the other memory cell MC, the 1-bit It goes without saying that it is also applicable to a memory that stores data. Further, as shown in FIG. 19, a boosted potential VPP is applied to one word line WL, and "H" is applied to one of the two memory cells MC connected to the bit lines BL and / BL.
By writing the level, the "L" level is written in the other memory cell MC, which is also applicable to a memory for storing 1-bit data.

[Second Embodiment] FIG. 20 is a circuit diagram showing a main portion of a memory circuit portion of a system LSI according to a second embodiment of the present invention, which is to be compared with FIG. Referring to FIG. 20, the memory circuit portion is different from the memory circuit portion of FIG. 5 in that memory cell MC is replaced with memory cell MC ′, and transfer gates 21 and 36 include transfer gate 90,
It is a point that is replaced with 93.

The memory cell MC ′ is the N-th memory cell MC.
The channel MOS transistor Q is replaced with a P channel MOS transistor Q '. In the standby state, the word line WL is held at the non-selection level "H". When row address signals RA0-RAi are input, word line WL designated thereby is lowered to the selection level "L" level. Word line WL is "L"
When lowered to the level, the P channel MOS transistor Q'of the memory cell MC 'connected to the word line WL becomes conductive, and the storage node SN of the memory cell MC' and the bit line BL or / BL are coupled. It The structure of the memory cell MC 'is the same as that of the memory cell MC shown in FIG.
Is the same as the structure of. However, memory cell MC 'is formed on the surface of the N-type well, and the source region and drain region of P-channel MOS transistor Q'and storage node SN are formed of P-type diffusion layers.

The transfer gate 90 connects the P channel MOS transistors 22 and 23 of the transfer gate 21 to the N channel MO.
It is replaced with S transistors 91 and 92. In the standby state, signal BLIR is held at "H" level. When memory array block MAk is selected, signal BLIR falls to "L" level and transfer gate 9
0 becomes non-conductive to disconnect the memory array block MAk-1 and the sense amplifier band SAk.

The transfer gate 93 connects the P channel MOS transistors 37 and 38 of the transfer gate 36 to the N channel MO.
It is replaced with S transistors 94 and 95. In the standby state, signal BLIL is held at "H" level. When memory array block MAk-1 is selected, signal BLIL falls to "L" level, transfer gate 93 becomes non-conductive, and memory array block MAk-1.
And the sense amplifier band SAk are separated.

FIG. 21 is a time chart showing the data writing method of the memory circuit section described with reference to FIG.
It is a figure contrasted with FIG. 21, in the standby state, word line WL is set to power supply potential VCC, and P channel MOS transistor Q'of memory cell MC 'is non-conductive. The storage node SN of the memory cell MC 'holds the power supply potential VCC or the ground potential GND. Further, the signals BLIR and BLIL are both set to the power supply potential VCC, and the transfer gates 90 and 93 are both conductive. Further, the signal BLEQ is set to the “H” level, and the bit line pair B is set by the equalizer 32.
L and / BL are equalized to the bit line potential VBL = VCC / 2.

When an active command ACT is input at a certain time and, for example, memory array block MAk is selected, signal BLIR is raised to ground potential GND, transfer gate 90 becomes non-conductive, and sense amplifier 27 operates as a memory. It is separated from the array block MAk-1. Further, the signal BLEQ is set to the “L” level, and the bit line B
The equalization of the potentials of L and / BL is stopped.

Next, word line WL of the row corresponding to row address signals RA0-RAi is lowered to negative potential VBB.
As a result, the P-channel MOS transistor Q'of the memory cell MC 'connected to the word line WL becomes conductive,
A minute potential difference is generated between the bit line pair BL, / BL according to the data stored in the memory cell MC '. At this time, for example, the potential of the bit line BL is set to be slightly higher than the potential of the bit line / BL. Then, the sense amplifier activation signals SE and / SE are set to "H" level and "L", respectively.
The level is set to activate the sense amplifier 27, and the minute potential difference between the nodes N1 and N2 is amplified to the power supply potential VCC.

At this time, nodes N1 and N2 are set to power supply potential VCC and ground potential GND, respectively, but bit lines BL and / BL are set to VCC-Vtn and GND, respectively. Vtn is a threshold voltage of N channel MOS transistor 94. This is the node N1 and the signal BL
Even if IL is set to the power supply potential VCC, the bit line BL becomes VCC.
This is because the N-channel MOS transistor 94 becomes non-conductive at −Vtn.

Therefore, the voltage Vgs applied to the gate insulating film of the P channel MOS transistor Q'of the memory cell MC 'is suppressed to the maximum Vgs = | VBB | + VCC-Vtn. N-channel MOS of transfer gates 90 and 93
Threshold voltage V of transistors 91, 92, 94, 95
tn is set so that | VBB | + VCC−Vtn≈VCC. Therefore, even if the gate insulating film of the P channel MOS transistor Q'of the memory cell MC 'is as thin as the insulating film of the capacitor C, there is no problem in reliability.

Next, the column selection line CSL of the column corresponding to the column address signals CA0 to CAi is raised to the selection level "H" level, and the column selection gate 24 is rendered conductive. Then, according to the write data signal, one of the data input / output line pair IO, / IO has a data input / output line (eg / IO) of "H".
Leveled to the other data input / output line (IO in this case)
Is set to the “L” level. In response, sense amplifier 27 raises node N2 to power supply potential VCC and lowers node N1 to ground potential GND. Even at this time, the nodes N1 and N2 are respectively connected to the ground potential GND.
And the power supply potential VCC, but the bit lines BL, / BL
Are VCC-Vtn and GND, respectively. For this reason,
P-channel MOS transistor Q'of memory cell MC '
The maximum voltage Vgs applied to the gate insulating film of Vgs = Vgs =
It is suppressed to | VBB | + VCC-Vtn. During this period, "L" is applied to the storage node SN of the memory cell MC '.
When writing a level, storage node SN can be set to ground potential GND, and "L" level data can be written sufficiently. However, when writing "H" level data, the storage node SN is set to the power supply potential V
CC cannot be set and data writing is insufficient.
Therefore, next, "H" level restore is performed.

That is, the precharge command PRE is input to move the word line WL from the negative potential VBB to the ground potential GN.
At the same time as rising to D, the signal BLIL is raised from the power supply potential VCC to the boosted potential VPP. As a result, N channel MOS transistor 94 of transfer gate 93 becomes conductive again, and bit line BL and storage node SN are raised to power supply potential VCC. At this time, the memory cell M
The voltage Vgs applied to the gate insulating film of C'P channel MOS transistor Q'is Vgs = VCC, and there is no risk of dielectric breakdown of the gate insulating film.

The period for restoring the "H" level can be short. When the "H" level restoration is completed, the word line WL is raised to the power supply potential VCC and the memory cell M
The P-channel MOS transistor Q'of C'is rendered non-conductive, and the level of the storage node SN is maintained. Further, signals BLIR and BLIL are both set to power supply potential VCC, transfer gates 90 and 93 are rendered conductive, signals SE and / SE are both set to bit line precharge potential VCC / 2, sense amplifier 27 is deactivated, and signal BLEQ is "H"
The bit line pair BL, / BL is set to the level and equalized to the bit line potential VBL.

In the second embodiment, | VBB | + VC
Since C-Vtn≈VCC is set, the memory cell MC ′
The gate insulating film of the P-channel MOS transistor Q'can be made as thin as the insulating film of the capacitor C, and a small size memory cell MC 'can be formed. Further, since the "H" level restoration is performed after the data writing, the level of the data signal can be sufficiently written in the storage node SN of the memory cell MC '.

It is needless to say that the second embodiment is also applicable to the method of storing 1-bit data in the two memory cells MC 'as described with reference to FIGS. 18 and 19.

[Third Embodiment] FIG. 22 is a circuit block diagram showing an essential part of a memory circuit portion of a system LSI according to a third embodiment of the present invention, which is to be compared with FIG. Referring to FIG. 22, this memory circuit unit is shown in FIG.
2 is different from the memory circuit section in FIG. 2 in that two memory cells MC are arranged at the intersection of the word line WL and the bit line pair BL, / BL, and the equalizer 32 is removed so that the two equalizers 100 and 104 are provided. Is provided.

N-channel MOS of two memory cells MC
The gates of the transistors Q are both associated with the corresponding word line WL.
N-channel MOS of two memory cells MC connected to
The source of the transistor Q is the corresponding bit line B
It is connected to L and / BL. The "H" level is written in one of the two memory cells MC, and the "L" level is written in the other memory cell MC. 1-bit data is stored in the two memory cells MC.

The equalizer 100 has three P channels M
The OS transistors 101 to 103 are included. P channel M
The OS transistor 101 is a memory array block MA
It is connected between the corresponding bit lines BL and / BL of k-1. The P channel MOS transistors 102 and 103 are
Each of them is connected between corresponding bit line BL, / BL and node N8. P-channel MOS transistor 101
The gates of ˜103 are both connected to node N7. Node N7 receives bit line equalize signal BLEQ, and node N8 receives bit line precharge potential VBL = VCC. When signal BLEQ is set to the activation level of "L", P channel MOS transistors 101 to 10
3 becomes conductive, and the bit line pair BL, / BL becomes the bit line potential V
Equalized to BL.

The equalizer 104 has three P channels M
The OS transistors 105 to 107 are included. P channel M
The OS transistor 105 is the memory array block MA.
It is connected between bit lines BL and / BL corresponding to k. P
Channel MOS transistors 106 and 107 are connected between corresponding bit lines BL and / BL and node N10, respectively. P-channel MOS transistors 105-1
The gates of 07 are both connected to the node N9. Node N9 receives bit line equalize signal BLEQ, and node N10 receives bit line precharge potential VBL = VCC. When signal BLEQ is set to the activation level of "L", P-channel MOS transistors 105-107.
Are turned on, and the bit line pair BL, / BL is equalized to the bit line precharge potential VBL.

FIG. 23 is a time chart showing a data writing method of the memory circuit section described with reference to FIG. FIG. 23
In the standby state, the word line WL is set to the ground potential GND, and the N channel MOS transistors Q of the two memory cells MC of FIG. 22 are both non-conductive. One memory cell M of the two memory cells MC
The power supply potential VCC is written in C, and the other memory cell M
The ground potential GND is held in C. Also, the signal B
Both LIR and BLIL are set to the boosted potential VPP, and both transfer gates 90 and 93 are conductive. Further, the signal BLEQ is set to the “L” level, and the bit line pair BL, / BL is equalized to the bit line precharge potential VBL = VCC by the equalizers 100, 104.

When an active command ACT is input at a certain time and, for example, memory array block MAk is selected, signal BLIR falls to ground potential GND, transfer gate 90 becomes non-conductive, and sense amplifier 27 operates as a memory. It is separated from the array block MAk-1. Further, the signal BLEQ is set to the “H” level, and the bit line B
The equalization of the potentials of L and / BL is stopped.

Next, word line WL of the row corresponding to row address signals RA0-RAi is raised to boosted potential VPP. As a result, the word line WL shown in FIG.
, The N-channel MOS transistor Q of the two memory cells MC becomes conductive, and a minute potential difference corresponding to the data stored in the two memory cells MC is generated between the bit line pair BL, / BL. At this time, for example, the potential of the bit line BL is set to be slightly higher than the potential of the bit line / BL.

Then, signals BLIL and BLIR are both set to ground potential GND, transfer gates 90 and 93 are rendered non-conductive, and sense amplifier 27 and two memory array blocks MAk-1 and MAk are separated. Also, the signal BL
EQ is lowered to “L” level and equalizer 100,
104 is activated and the memory array block MAk−
Each bit line pair BL, / BL of 1 and MAk is equalized to the bit line precharge potential VBL = VCC. At this time, the ground potential GND is applied to the gates of the P channel MOS transistors 101 to 103, 105 to 107 of the equalizers 100 and 104, and the boosted potential VPP is applied to the word line WL of FIG. Sufficient "H" level (power supply potential VCC) is applied to storage node SN of MC.

Sense amplifier activation signals SE and / S
E is set to "H" level and "L" level to activate sense amplifier 27, and the minute potential difference between nodes N1 and N2 is amplified to power supply potential VCC.

At this time, the N channel M of the memory cell MC
The voltage V applied to the gate insulating film of the OS transistor Q
Since gs becomes Vgs = VPP-VCC, even if the gate insulating film of the N-channel MOS transistor Q of the memory cell MC is made as thin as the insulating film of the capacitor C, there is no problem in reliability.

Then, the column selection line CSL of the column corresponding to the column address signals CA0 to CAi 'is raised to the selection level "H" level, and the column selection gate 24 is rendered conductive. Then, according to the write data signal, one data input / output line (for example, / IO) of data input / output line pair IO, / IO is set to the “H” level, and the other data input / output line (IO in this case) is set to “H” level. L "level. In response, sense amplifier 27 raises node N2 to power supply potential VCC and lowers node N1 to ground voltage GND.

Next, when precharge command PRE is input, word line WL is lowered from boosted potential VPP to power supply potential VCC, and signal BLEQ is at "H".
The equalizers 100 and 104 are raised to the level and deactivated. Further, the signal BLIL is raised to the boosted potential VPP, the transfer gate 93 becomes conductive, and the nodes N1 and N2 are turned on.
Potentials GND and VCC of the memory array block MAk are transmitted to the bit lines BL and / BL of the memory array block MAk, respectively, and written to the storage node SN of the two memory cells MC. At this time, since signal BLIL is at boosted potential VPP, a sufficient “L” level is written in storage node SN of memory cell MC. Further, at this time, the voltage Vgs applied to the gate insulating film of the N-channel MOS transistor Q of the memory cell MC becomes Vgs = VCC, and there is no risk of dielectric breakdown of the gate insulating film.

When the writing to the "L" level is completed, word line WL is lowered to ground potential GND and memory cell MC
N-channel MOS transistor Q becomes non-conductive, and the level of storage node SN is maintained. Also signal B
Both LIR and BLIL are set to the boosted potential VPP, the transfer gates 90 and 93 are rendered conductive, and the signals SE and / SE are set to VCC.
The bit line precharge potential level of / 2 is set to inactivate the sense amplifier 27, the signal BLEQ is set to the "L" level, and the bit line pair BL, / BL is equalized to the bit line precharge potential VBL.

In the third embodiment, first the word line WL
Is set to the boosted potential VPP to write "H" level data to one memory cell MC, and then the word line WL is set to the power supply potential VCC to write "L" level data to the other memory cell MC. Therefore, the voltage Vgs applied to the gate insulating film of the N-channel MOS transistor Q of the memory cell MC can be set to VCC or less, and the memory cell M
The gate insulating film of the N-channel MOS transistor Q of C can be made as thin as the insulating film of the capacitor C, and thus the memory cell MC having a small size can be configured. Further, the "H" level or the "L" level can be sufficiently written in the storage node SN of the memory cell MC.

In the third embodiment, the two memory cells MC store a 1-bit data signal and the two memory cells MC are connected to one word line WL. The writing method is one memory cell MC
The present invention is also applicable to a method of storing 1-bit data by using two memory cells MC, as shown in FIG.
Stores a 1-bit data signal and stores two memory cells M
It goes without saying that it is also applicable to the system in which C is connected to each of the two word lines WL.

[Fourth Embodiment] FIG. 24 is a circuit block diagram showing an essential part of a memory circuit portion of a system LSI according to a fourth embodiment of the present invention, which is to be compared with FIG. Referring to FIG. 24, this memory circuit unit is shown in FIG.
Is different from the memory circuit section of FIG. 1 in that the memory cell MC is replaced by the memory cell MC ′.
The point 104 is replaced by the equalizers 110 and 114.

P channel MO of two memory cells MC '
The gates of S transistors Q'are both connected to the corresponding word line WL, and the sources of P channel MOS transistors Q'of the two memory cells MC 'are connected to the corresponding bit lines BL and / BL, respectively. Two memory cells M
The "H" level is written in one memory cell MC 'of C'and the "L" level is written in the other memory cell MC'. 1 bit of data is stored in the two memory cells MC '.

The equalizer 110 has three N channels M
The OS transistors 111 to 113 are included. N channel M
The OS transistor 111 is a memory array block MA.
It is connected between the corresponding bit lines BL and / BL of k-1. The N-channel MOS transistors 112 and 113 are
Each of them is connected between corresponding bit line BL, / BL and node N8. N-channel MOS transistor 111
Gates of ~ 113 are both connected to node N7. Node N7 receives bit line equalize signal BLEQ, and node N8 receives bit line precharge potential VBL = GND. When signal BLEQ is set to the activation level of "H", N channel MOS transistors 111 to 11 are generated.
3 becomes conductive, and the bit line pair BL, / BL becomes the bit line potential V
Equalized to BL.

The equalizer 114 has three N channels M
Includes OS transistors 115-117. N channel M
The OS transistor 115 is the memory array block MA.
It is connected between bit lines BL and / BL corresponding to k. N
Channel MOS transistors 116 and 117 are connected between corresponding bit lines BL and / BL and node N10, respectively. N-channel MOS transistors 115-1
Both gates of 17 are connected to node N9. Node N9 receives bit line equalize signal BLEQ, and node N10 receives bit line precharge potential VBL = GND. When signal BLEQ is set to the activation level of "H", N-channel MOS transistors 115 to 117 are generated.
Are turned on, and the bit line pair BL, / BL is equalized to the bit line precharge potential VBL.

FIG. 25 is a time chart showing a data writing method of the memory circuit section described with reference to FIG. Figure 25
In the standby state, the word line WL is set to the power supply potential VCC, and P of the two memory cells MC ′ of FIG.
Both channel MOS transistors Q'are non-conductive. The power supply potential VCC is written in one of the two memory cells MC ', and the ground potential GND is held in the other memory cell MC'. Further, the signals BLIR and BLIL are both set to the boosted potential VPP, and the transfer gates 90 and 93 are both conductive. In addition, the signal BLEQ is set to the “H” level,
The bit lines BL, /
BL is equalized to the bit line precharge potential VBL = GND.

When an active command ACT is input at a certain time and, for example, memory array block MAk is selected, signal BLIR is lowered to ground potential GND, transfer gate 90 becomes non-conductive, and sense amplifier 27 operates as a memory. It is separated from the array block MAk-1. Further, the signal BLEQ is set to the “L” level, and the bit line B
The equalization of the potentials of L and / BL is stopped.

Then, the word line WL of the row corresponding to the row address signals RA0 to RAi is lowered to the negative potential VBB.
As a result, 2 of FIG. 24 connected to the word line WL
P channel MOS transistor Q'of one memory cell MC 'is rendered conductive, and a minute potential difference according to the stored data of two memory cells MC' is generated between bit line pair BL, / BL. At this time, for example, the potential of the bit line BL is set to be slightly higher than the potential of the bit line / BL.

Then, signals BLIL and BLIR are both set to ground potential GND, transfer gates 90 and 93 are rendered non-conductive, and sense amplifier 27 and two memory array blocks MAk-1 and MAk are separated. Also, the signal BL
The EQ is raised to the “H” level and the equalizer 110,
114 is activated and the memory array block MAk-
Each bit line pair BL, / BL of 1 and MAk is equalized to the bit line precharge potential VBL = GND. At this time, the power supply potential VCC is applied to the gates of the N-channel MOS transistors 111 to 113, 115 to 117 of the equalizers 110 and 114, and the negative potential VBB is applied to the word line WL of FIG. M
Sufficient "L" level (ground potential GND) is applied to storage node SN of C '.

Sense amplifier activation signals SE and / S
E is set to the “H” level and the “L” level to activate the sense amplifier 27, and the minute potential difference between the nodes N1 and N2 is amplified to the power supply voltage VCC.

At this time, the voltage Vgs applied to the gate insulating film of the P-channel MOS transistor Q'of the memory cell MC 'becomes Vgs = VBB-GND, so that the gate of the P-channel MOS transistor Q'of the memory cell MC'. Even if the insulating film is as thin as the insulating film of the capacitor C, there is no problem in reliability.

Next, the column selection line CSL of the column corresponding to the column address signals CA0 to CAi 'is raised to the selection level "H" level, and the column selection gate 24 is rendered conductive. Then, according to the write data signal, one data input / output line (for example, / IO) of data input / output line pair IO, / IO is set to the “H” level, and the other data input / output line (IO in this case) is set to “H” level. L "level. In response, sense amplifier 27 raises node N2 to power supply potential VCC and lowers node N1 to ground potential GND.

Next, when the precharge command PRE is input, the word line WL is changed from the negative potential VBB to the ground potential G.
While being raised to ND, signal BLEQ is lowered to "L" level, and equalizers 110 and 114 are deactivated. Further, the signal BLIL is raised to the boosted potential VPP, the transfer gate 93 is rendered conductive, and the potentials GND and VCC of the nodes N1 and N2 are respectively set in the memory array block M.
It is transmitted to the bit lines BL and / BL of Ak and written in the storage node SN of the two memory cells MC '. At this time, since signal BLIL is at boosted potential VPP, sufficient "H" level is written in storage node SN of memory cell MC '. Further, at this time, the voltage Vgs applied to the gate insulating film of the P-channel MOS transistor Q'of the memory cell MC 'is Vgs = VCC, and there is no risk of dielectric breakdown of the gate insulating film.

When writing to the "H" level is completed, word line WL is raised to power supply potential VCC and memory cell M
The P-channel MOS transistor Q'of C'is rendered non-conductive, and the level of the storage node SN is maintained. Further, the signals BLIR and BLIL are both set to the boosted potential VPP, the transfer gates 90 and 93 are turned on, the signals SE and / SE are set to the bit line precharge potential level of VCC / 2, and the sense amplifier 27 is deactivated. Signal BLEQ is set to "H" level and bit line pair BL, / BL is equalized to bit line precharge potential VBL.

In the fourth embodiment, first, the word line WL
Is set to a negative potential VBB to write "L" level data to one memory cell MC ', and then the word line WL is set to the ground potential GND to write "H" level data to the other memory cell MC'. Therefore, the voltage Vgs applied to the gate insulating film of the P-channel MOS transistor Q'of the memory cell MC 'can be set to VCC or less, and the gate insulating film of the P-channel MOS transistor Q'of the memory cell MC' can be changed to the capacitor C. The thickness of the memory cell MC 'can be as thin as that of the insulating film of
Can be configured. Further, "H" level or "L" level can be sufficiently written in storage node SN of memory cell MC '.

In the fourth embodiment, the two memory cells MC 'store a 1-bit data signal and the two memory cells MC' are connected to one word line WL. This data writing method can also be applied to a method of storing 1-bit data in one memory cell MC ', and, as shown in FIG. 8, a 1-bit data signal in two memory cells MC'. It is needless to say that the present invention is also applicable to a system of storing two memory cells MC ′ and connecting two memory cells MC ′ to two word lines WL.

[Fifth Embodiment] FIG. 26 is a circuit diagram showing a main portion of a memory circuit portion of a system LSI according to a fifth embodiment of the present invention, which is to be compared with FIG. Referring to FIG. 26, the memory circuit unit differs from the memory circuit unit of FIG. 5 in that a memory array block MA ′ adjacent to memory array block MA is added. In FIG. 26, a memory array block MAk 'adjacent to the memory array block MAk is shown.

Memory array block MAk 'has the same number of rows and columns as memory array block MAk, a plurality of memory cells MC' arranged in a matrix, and word lines / WL provided corresponding to each row. And a bit line pair BL, / BL provided corresponding to each column. Memory cell M
C'is the N-channel MOS transistor Q of the memory cell MC replaced by a P-channel MOS transistor Q '. The plurality of word lines / WL of memory array block MAk 'are provided corresponding to the plurality of word lines WL of memory array block MAk, respectively. The word line WL and the corresponding word line / WL form a pair, and when the word line WL is set to the selection level "H" level (power supply voltage VCC), the corresponding word line / WL is set to the selection level "H". L "level (ground potential GND). Bit lines BL, / BL of memory array block MAk and bit lines BL, / BL of memory array block MAk '
Is connected. The activation level of signals BLIR and BLIL is negative potential VBB, and their inactivation level is power supply potential VCC.

Now, memory array blocks MAk, MA
It is assumed that k'is selected and the signal BLIL is set to the activation level negative potential VBB. In the write mode, a pair of word lines WL, / WL designated by row address signals RA0-RAi are set to power supply potential VCC and ground potential GND, respectively, and memory cells corresponding to those word lines WL, / WL are set. N channel MOS transistor Q of MC and P channel MOS transistor Q'of memory cell MC 'are rendered conductive. Then, one of the bit lines BL and / BL is supplied with the power supply potential VCC according to the write data signal.
And the other is set to the ground potential GND.

When bit line BL is set to power supply potential VCC, sufficient "H" level (power supply potential VCC) is written to storage node SN of memory cell MC '.
VCC-V is applied to the storage node SN of the memory cell MC.
tn is written. When bit line BL is set to ground potential GND, sufficient "L" level (ground potential GND) is written in storage node SN of memory cell MC, while | V is stored in storage node SN of memory cell MC '.
tp | is written.

In the read mode, memory cells MC, MC '
If "H" level is written in, the word line W
L and / WL are the power supply potential VCC and the ground potential G, respectively.
When set to ND, the P channel MOS of the memory cell MC '
Transistor Q'is sufficiently conductive and "H" level data is sufficiently read from memory cell MC ', while N-channel MOS transistor Q of memory cell MC is not sufficiently conductive and memory cell MC outputs "H". The level data is not fully read.

When the "L" level is written in memory cells MC and MC ', when word lines WL and / WL are set to power supply potential VCC and ground potential GND, respectively, N of memory cell MC is changed. Channel MOS transistor Q
Is sufficiently conductive and "L" level data is sufficiently read from the memory cell MC, while the P-channel MOS transistor Q'of the memory cell MC 'is not sufficiently conductive and is "L" from the memory cell MC'. Level data is not sufficiently read.

In the fifth embodiment, reading / writing of "L" level data is carried out by memory cell MC and reading / writing of "H" level data is carried out by memory cell MC '. The amplitude voltage of WL, / WL is the power supply voltage VC
Even if C is used, data can be sufficiently read / written. Therefore, the gate insulating films of the N-channel MOS transistor Q and the P-channel MOS transistor Q'of the memory cells MC and MC 'can be made as thin as the insulating film of the capacitor C, and the small-sized memory cells MC and MC'. ′ Can be configured.

It should be considered that the embodiments disclosed this time are illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description but by the claims, and is intended to include meanings equivalent to the claims and all modifications within the scope.

[0148]

As described above, in the semiconductor memory device according to the present invention, the memory cell for storing the data signal having the MOS transistor and the capacitor connected in series is provided, and the MOS transistor is formed on the semiconductor substrate. The capacitor includes a gate insulating film formed on the surface of the gate insulating film, a gate electrode formed on the surface of the gate insulating film, and impurity diffusion regions formed on the surface of the semiconductor substrate on both sides of the gate electrode. A gate electrode of a MOS transistor including an impurity diffusion region formed on the surface of a substrate, an insulating film formed on the surface of the impurity diffusion region, and a flat plate electrode formed on the surface of the insulating film and receiving a reference potential. And the plate electrode of the capacitor are formed in the same wiring layer. Therefore, it is not necessary to separately provide a wiring layer for electrodes of storage nodes and capacitors,
Since it can be manufactured only by the logic process, the chip cost can be reduced. Moreover, since the gate insulating film of the MOS transistor and the insulating film of the capacitor have the same thickness, the distance between the MOS transistor and the capacitor can be shortened, and the chip size can be reduced. Further, since the dynamic type memory cell is adopted, the memory capacity can be increased as compared with the case where the static type memory cell is adopted.

Preferably, the semiconductor memory device is formed on a semiconductor substrate together with a logic circuit including a MOS transistor, and the gate electrode of the MOS transistor of the logic circuit, the gate electrode of the MOS transistor of the memory cell, and the plate electrode of the capacitor are: It is formed of the same wiring layer.
In this case, the system LSI including the semiconductor memory device and the logic circuit can be manufactured only by the CMOS logic process.

Preferably, the MOS transistor of the memory cell is an N-channel MOS transistor, and the semiconductor memory device further includes a word line connected to the gate of the N-channel MOS transistor and one of them is an N-channel. First and second bit lines connected to the source of the MOS transistor, and a first P-channel MO connected between the first bit line and the first node.
An S transistor, a second P channel MOS transistor connected between the second bit line and the second node, and a write circuit for writing a data signal to the memory cell are provided. This write circuit applies a ground potential to the gates of the first and second P-channel MOS transistors to make the first
And a step of making the second P-channel MOS transistor conductive, a step of applying a boosted potential higher than the power supply potential to the word line to make the N-channel MOS transistor of the memory cell conductive, and in accordance with a write data signal externally applied. , A step of setting one of the first and second nodes to the power supply potential and the other node to the ground potential, and setting the gates of the first and second P-channel MOS transistors to be higher than the ground potential. Applying a low negative potential and a power supply potential to the word line. In this case, data can be written in the memory cell without destroying the gate insulating film of the N channel MOS transistor of the memory cell.

Preferably, the absolute value of the threshold voltage of each of the first and second P-channel MOS transistors is set to be approximately equal to the voltage difference between the boosted potential and the power supply potential. In this case, the data signal can be sufficiently written in the memory cell while limiting the voltage applied to the gate insulating film of the N-channel MOS transistor of the memory cell to the power supply voltage or less.

Preferably, two memory cells are provided so that two memory cells store one data signal, two word lines are provided, and the gates of the N-channel MOS transistors of the two memory cells are respectively The N-channel MOS transistors of the two memory cells are connected to the two word lines, and the sources of the N-channel MOS transistors are connected to the first and second bit lines, respectively. In this case, writing / reading of the data signal can be performed more reliably.

Further, preferably, two memory cells are provided and one memory cell stores one data signal.
The gates of the N-channel MOS transistors of two memory cells are both connected to the word line, and the N-channel MOS transistors of the two memory cells are connected to each other.
The sources of the channel MOS transistors are connected to the first and second bit lines, respectively. Also in this case, writing / reading of the data signal can be performed more reliably.

Preferably, the MOS transistor of the memory cell is a P-channel MOS transistor, and the semiconductor memory device further includes a word line connected to the gate of the P-channel MOS transistor and one of them being P-channel. First and second bit lines connected to the source of the channel MOS transistor, and a first N channel M connected between the first bit line and the first node.
An OS transistor, a second N-channel MOS transistor connected between the second bit line and the second node, and a write circuit for writing a data signal in the memory cell are provided. This write circuit applies a power supply potential to the gates of the first and second N-channel MOS transistors to make the first
And a step of turning on the second N-channel MOS transistor, a step of applying a negative potential lower than the ground potential to the word line to turn on the P-channel MOS transistor of the memory cell, and a step of applying a write data signal externally applied. , A step of setting one of the first and second nodes to the power supply potential and the other node to the ground potential, the gates of the first and second N-channel MOS transistors being set to the power supply potential higher than the power supply potential. And a step of applying a ground potential to the word line while applying a high boosted potential. In this case, data can be written in the memory cell without destroying the gate insulating film of the P channel MOS transistor of the memory cell.

Preferably, the threshold voltages of the first and second N-channel MOS transistors are set to be substantially equal to the difference between the ground potential and the negative potential. In this case, the data signal can be sufficiently written in the memory cell while limiting the voltage applied to the gate insulating film of the P-channel MOS transistor of the memory cell to the power supply voltage or less.

Further, preferably, two memory cells are provided, two memory cells store one data signal, two word lines are provided, and the gates of the P-channel MOS transistors of the two memory cells are 2 respectively. Of the two memory cells, and the sources of the P-channel MOS transistors of the two memory cells are connected to the first and second bit lines, respectively. In this case, write the data signal
Reading can be performed more reliably.

Preferably, two memory cells are provided so that one memory cell stores one data signal.
The gates of the P-channel MOS transistors of two memory cells are both connected to the word line,
The sources of the channel MOS transistors are connected to the first and second bit lines, respectively. In this case, writing / reading of the data signal can be performed more reliably.

Preferably, the MOS transistor of the memory cell is a P-channel MOS transistor, and the semiconductor memory device further has a word line connected to the gate of the P-channel MOS transistor and one of them being P-channel. It includes first and second bit lines connected to the sources of channel MOS transistors, and a write circuit for writing a data signal in a memory cell. This writing circuit applies a negative potential lower than a ground potential to a word line to make a P-channel MOS transistor of a memory cell conductive, a step of applying a ground potential to the first and second bit lines, and a word line. To one of the first and second bit lines to the power supply potential and the other bit line to the ground potential according to the step of applying the ground potential to the Perform steps and In this case, data can be written in the memory cell without destroying the gate insulating film of the P channel MOS transistor of the memory cell.

Preferably, two memory cells are provided so that one memory cell stores one data signal, two word lines are provided, and the gates of the P-channel MOS transistors of the two memory cells are 2 respectively. Connected to the first word line, the sources of the P-channel MOS transistors of the two memory cells are connected to the first and second bit lines, respectively. In this case, writing / reading of the data signal can be performed more reliably.

Further, preferably, two memory cells are provided and one memory cell stores one data signal.
The gates of the P-channel MOS transistors of two memory cells are both connected to the word line,
The sources of the channel MOS transistors are connected to the first and second bit lines, respectively. Also in this case, writing / reading of the data signal can be performed more reliably.

Preferably, the MOS transistor of the memory cell is a P-channel MOS transistor, and the semiconductor memory device further includes a word line connected to the gate of the P-channel MOS transistor and one of them being P-channel. It includes first and second bit lines connected to the sources of channel MOS transistors, and a write circuit for writing a data signal in a memory cell. This writing circuit applies a negative potential lower than a ground potential to a word line to make a P-channel MOS transistor of a memory cell conductive, a step of applying a ground potential to the first and second bit lines, and a word line. To one of the first and second bit lines to the power supply potential and the other bit line to the ground potential according to the step of applying the ground potential to the Perform steps and In this case, data can be written in the memory cell without destroying the gate insulating film of the P channel MOS transistor of the memory cell.

Further, preferably, two memory cells are provided so that one memory cell stores one data signal, two word lines are provided, and the gates of the P-channel MOS transistors of the two memory cells are 2 respectively. Connected to the first word line, the sources of the P-channel MOS transistors of the two memory cells are connected to the first and second bit lines, respectively. In this case, writing / reading of the data signal can be performed more reliably.

Preferably, two memory cells are provided and two memory cells store one data signal,
The gates of the P-channel MOS transistors of two memory cells are both connected to the word line,
The sources of the channel MOS transistors are connected to the first and second bit lines, respectively. Also in this case, writing / reading of the data signal can be performed more reliably.

Further, preferably, two memory cells are provided and one memory cell stores one data signal.
The MOS transistor of one of the two memory cells is an N-channel MOS transistor, and the MOS transistor of the other memory cell is a P-channel MOS transistor.
The semiconductor memory device further includes first and second word lines connected to the gates of the N-channel MOS transistor and the P-channel MOS transistor, respectively, and one of them is an N-channel MOS transistor. First and second bit lines connected to the source of the transistor and the source of the P-channel MOS transistor, and a write circuit for writing a data signal into the two memory cells are provided. This writing circuit is
A step of applying a power supply potential and a ground potential to the second word line to make the N-channel MOS transistor and the P-channel MOS transistor conductive, and the first and second bit lines according to a write data signal externally applied. One of the bit lines is set to the power supply potential and the other bit line is set to the ground potential. In this case, data can be written in the memory cell without destroying the gate insulating film of the MOS transistor of the memory cell.

[Brief description of drawings]

FIG. 1 is a system LS according to a first embodiment of the present invention.
It is a block diagram which shows the structure of I.

FIG. 2 is a block diagram showing a configuration of a memory circuit section shown in FIG.

FIG. 3 is a block diagram showing a configuration of a memory array shown in FIG. 2 and a portion related to the memory array.

FIG. 4 is a circuit block diagram showing a configuration of a memory array block shown in FIG.

5 is a circuit diagram showing a main part of the sense amplifier band shown in FIG.

6 is a diagram showing a configuration of a memory cell shown in FIG.

FIG. 7 is a diagram for explaining a problem of the memory cell shown in FIG.

FIG. 8 is another diagram for explaining the problem of the memory cell shown in FIG.

9 is a circuit diagram showing a configuration of a word driver included in the row decoder shown in FIG.

FIG. 10 is a time chart showing the operation of the word driver shown in FIG.

11 is a block diagram showing a signal generation circuit and a local control circuit provided corresponding to the sense amplifier band and the memory array block shown in FIG.

FIG. 12 shows a signal generation circuit 71. shown in FIG. It is a circuit block diagram which shows the structure of k.

13 is a circuit diagram showing a configuration of the level shifter shown in FIG.

FIG. 14 shows a signal generation circuit 72. shown in FIG. It is a circuit block diagram which shows the structure of k.

FIG. 15 is a time chart showing operations of the signal generation circuit and the local control circuit shown in FIGS. 11 to 14.

FIG. 16 is a time chart showing a data writing method of the memory circuit section shown in FIGS. 1 to 15.

17 is a diagram for explaining the effect of the data writing method shown in FIG.

FIG. 18 is a block diagram showing a modified example of the first embodiment.

FIG. 19 is a block diagram showing another modification of the first embodiment.

FIG. 20 is a system L according to a second embodiment of the present invention.
It is a circuit diagram showing the important section of the memory circuit part of SI.

FIG. 21 is a time chart showing a data writing method of the memory circuit section shown in FIG. 20.

FIG. 22 is a system L according to the third embodiment of the present invention.
It is a circuit block diagram showing the important section of the memory circuit part of SI.

FIG. 23 is a time chart showing a data writing method of the memory circuit section shown in FIG. 22.

FIG. 24 is a system L according to the fourth embodiment of the present invention.
It is a circuit block diagram showing the important section of the memory circuit part of SI.

FIG. 25 is a time chart showing a data writing method of the memory circuit section shown in FIG. 24.

FIG. 26 is a system L according to the fifth embodiment of the present invention.
It is a circuit block diagram showing the important section of the memory circuit part of SI.

[Explanation of symbols]

1 system LSI, 2 logic circuit section, 3 memory circuit section, 4 clock buffer, 5 control signal buffer, 6 address buffer, 7 mode register, 8
Control circuit, 9 to 12 memory array, 13 IO buffer, MA memory array block, SA sense amplifier band, 14 memory mat, 15 row decoder, 16 column decoder, MC, MC 'memory cell, WL, / WL
Word line, BL, / BL bit line pair, C capacitor, SN storage node, Q, 25, 26, 30,
31, 33-35, 64-66, 76-78, 82, 8
3 N-channel MOS transistor, 21 column select gate, Q ', 22, 23, 28, 29, 37, 38, 59
~ 63,75,80,81,101-103,105-
107 P-channel MOS transistor, 24, 36,
90, 93 transfer gates, 27 sense amplifiers, 32,
100,104 Equalizer, 40 crystalline silicon substrate, 41 P-type well, 42 gate insulating film, 43 gate electrode, 44 source region, 45 drain region, 4
6 N-type diffusion layer or inversion layer, 47 insulating film, 48 cell plate electrode, 49 insulating layer, 50 contact hole, 51 element isolation film, 55 word driver, 56,
79 level shifter, 57 switching circuit, 58, 67, 6
8, 73, 74, 84 Inverter, 70 Local control circuit, 71, 72 Signal generating circuit.

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 5F083 AD14 LA03 LA05 ZA12                 5M024 AA58 AA91 CC23 CC34 CC63                       CC64 CC74 DD28 FF03 HH03                       KK35 LL01 LL02 PP01 PP03                       PP04 PP05 PP07

Claims (17)

[Claims] 1. A semiconductor memory device formed on a semiconductor substrate, comprising a MOS transistor and a capacitor connected in series, comprising a memory cell for storing a data signal, wherein the MOS transistor is the semiconductor A gate insulating film formed on the surface of the substrate; a gate electrode formed on the surface of the gate insulating film; and an impurity diffusion region formed on the surface of the semiconductor substrate on both sides of the gate electrode. Includes an impurity diffusion region formed on the surface of the semiconductor substrate, an insulating film formed on the surface of the impurity diffusion region, and a flat plate electrode formed on the surface of the insulating film and receiving a reference potential, A semiconductor memory device, wherein a gate electrode of a MOS transistor and a plate electrode of the capacitor are formed in the same wiring layer. 2. The semiconductor memory device is formed on the semiconductor substrate together with a logic circuit including a MOS transistor, and has a gate electrode of the MOS transistor of the logic circuit, a gate electrode of the MOS transistor of the memory cell, and a flat plate of the capacitor. The semiconductor memory device according to claim 1, wherein the electrodes are formed of the same wiring layer. 3. The MOS transistor of the memory cell is an N-channel MOS transistor, and the semiconductor memory device further includes a word line connected to a gate of the N-channel MOS transistor, and one of them. First and second bit lines connected to the source of the N-channel MOS transistor, a first P-channel MOS transistor connected between the first bit line and a first node, the second A second P-channel MOS transistor connected between a bit line and a second node, and a write circuit for writing a data signal in the memory cell are provided, and the write circuit includes the first and second A ground potential is applied to the gate of the second P-channel MOS transistor to make the first and second P-channel MOS transistors conductive. Applying a boosted potential higher than a power supply potential to the word line to make the N-channel MOS transistor of the memory cell conductive, according to a write data signal externally applied, the first and second nodes Setting one of the nodes to the power supply potential and the other node to the ground potential; and the first and second P-channels M
3. The semiconductor memory device according to claim 1, wherein a step of applying a negative potential lower than the ground potential to the gate of the OS transistor and applying the power supply potential to the word line is performed. 4. The first and second P-channel MOSs
4. The semiconductor memory device according to claim 3, wherein the absolute value of the threshold voltage of each transistor is set to be substantially equal to the voltage of the difference between the boosted potential and the power supply potential. 5. The two memory cells are provided so that one memory cell stores one data signal, the two word lines are provided, and the N-channel MOS of the two memory cells is provided.
The gate of the transistor is connected to two word lines respectively, and the sources of the N-channel MOS transistors of the two memory cells are connected to the first and second bit lines, respectively. 4. The semiconductor memory device according to item 4. 6. The two memory cells are provided so that two memory cells store one data signal, and the gates of N-channel MOS transistors of the two memory cells are both connected to the word line and two memory cells are connected. The sources of the N-channel MOS transistors of the memory cell are respectively the first
5. The semiconductor memory device according to claim 3, which is connected to the second bit line. 7. The MOS transistor of the memory cell is a P-channel MOS transistor, and the semiconductor memory device further includes a word line connected to the gate of the P-channel MOS transistor, or one of them. First and second bit lines connected to the source of the P-channel MOS transistor, a first N-channel MOS transistor connected between the first bit line and a first node, and the second A second N-channel MOS transistor connected between a bit line and a second node, and a write circuit for writing a data signal in the memory cell are provided, and the write circuit includes the first and second A power supply potential is applied to the gate of the second N-channel MOS transistor to make the first and second N-channel MOS transistors conductive. The step of applying a negative potential lower than the ground potential to the word line to render the P-channel MOS transistor of the memory cell conductive, and in accordance with a write data signal externally applied, the first and second nodes Setting one of the nodes to the power supply potential and the other node to the ground potential, and the first and second N-channel MOs.
3. The semiconductor memory device according to claim 1, wherein the step of applying a boosted potential higher than the power supply potential to the gate of the S transistor and applying the ground potential to the word line is performed. 8. The first and second N-channel MOSs
The threshold voltage of the transistor is set to be substantially equal to the voltage of the difference between the ground potential and the negative potential,
The semiconductor memory device according to claim 7. 9. The memory cell is provided with two memory cells, two memory cells store one data signal, two word lines are provided, and a P-channel MOS of the two memory cells is provided.
8. The gates of the transistors are respectively connected to two word lines, and the sources of P-channel MOS transistors of the two memory cells are respectively connected to the first and second bit lines. 8. The semiconductor memory device according to item 8. 10. The two memory cells are provided so that two memory cells store one data signal, and the gates of P-channel MOS transistors of the two memory cells are both connected to the word line and two memory cells are connected. 9. The semiconductor memory device according to claim 7, wherein the sources of P-channel MOS transistors of the memory cells are connected to the first and second bit lines, respectively. 11. The MOS transistor of the memory cell is an N-channel MOS transistor, and the semiconductor memory device further includes a word line connected to a gate of the N-channel MOS transistor, or one of them. A first and a second bit line connected to the source of the N-channel MOS transistor, and a write circuit for writing a data signal in the memory cell,
The write circuit applies a boosted potential higher than a power supply potential to the word line to make the N-channel MOS transistor of the memory cell conductive; a step of applying the power supply potential to the first and second bit lines; According to the step of applying the power supply potential to the word line and the write data signal applied from the outside, the first and second
3. The semiconductor memory device according to claim 1, wherein the step of setting one of the bit lines to the power supply potential and the other bit line to the ground potential is performed. 12. The two memory cells are provided, two memory cells store one data signal, the two word lines are provided, and an N channel MO of the two memory cells is provided.
12. The gates of S transistors are connected to two word lines respectively, and the sources of N channel MOS transistors of two memory cells are connected to the first and second bit lines, respectively. Semiconductor memory device. 13. Two memory cells are provided so that two memory cells store one data signal, and the gates of N-channel MOS transistors of the two memory cells are both connected to the word line and two memory cells are connected. The source of the N-channel MOS transistor of the memory cell is connected to the first and second bit lines, respectively.
The semiconductor memory device according to 1. 14. The MOS transistor of the memory cell is a P-channel MOS transistor, and the semiconductor memory device further includes a word line connected to the gate of the P-channel MOS transistor, or one of them. A first and second bit lines connected to the source of the P-channel MOS transistor, and a write circuit for writing a data signal in the memory cell,
The write circuit applies a negative potential lower than a ground potential to the word line to make a P-channel MOS transistor of the memory cell conductive; a step of applying the ground potential to the first and second bit lines; According to the step of applying the ground potential to the word line and the externally applied write data signal, one of the first and second bit lines is set to the power supply potential and the other bit is set to the power supply potential. The semiconductor memory device according to claim 1, wherein the step of bringing a line to said ground potential is executed. 15. The two memory cells are provided so that one memory cell stores one data signal, the two word lines are provided, and the P channel MO of the two memory cells is provided.
15. The gates of S transistors are connected to two word lines respectively, and the sources of P channel MOS transistors of two memory cells are connected to the first and second bit lines, respectively. Semiconductor memory device. 16. The memory cell is provided with two memory cells, two memory cells store one data signal, and the gates of P-channel MOS transistors of the two memory cells are both connected to the word line and two memory cells are connected. The source of the P-channel MOS transistor of the memory cell is connected to the first and second bit lines, respectively.
The semiconductor memory device according to 1. 17. The two memory cells are provided so that one memory cell stores one data signal, and one of the two memory cells has a MOS transistor which is an N-channel MOS transistor and the other has the other. The MOS transistor of the memory cell is a P channel MOS transistor, and the semiconductor memory device further includes first and second word lines connected to the gate of the N channel MOS transistor and the gate of the P channel MOS transistor, respectively. For writing a data signal to the first and second bit lines, one of which is connected to the source of the N-channel MOS transistor and the source of the P-channel MOS transistor, and the two memory cells. And a write circuit, wherein the write circuit is the first A step of applying a power supply potential and a ground potential to the second word line to make the N-channel MOS transistor and the P-channel MOS transistor conductive, and the first and second word lines in accordance with a write data signal externally applied. 3. The semiconductor memory device according to claim 1, wherein the step of setting one of the bit lines to the power supply potential and the other bit line to the ground potential is performed.