JP2003086585A - Method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a film creating device of an layer insulation film having a composition suitable for forming a contact hole. SOLUTION: This manufacturing method of a semiconductor device includes a wiring preparing process for forming a thick wire 3 inserted between an upper surface 3T and a lower surface 3B on the surface of a substrate 1 composed of a semiconductor and am insulation film forming process for making gas containing Si and gas containing O react and deposit an insulation film 4 composed of Si and O to coat the wire 3. The insulation film forming process varies the flow ratio of the gas containing Si into the gas containing in the middle of moving the insulation film 4 from the lower surface 3B of the deposited wire 3 to the upper face 3T, to differentiate the composition of Si and O to at least two steps of a lower layer 4L and an upper layer 4U. By using the difference of etching speed based on the difference of the composition of Si and O, the contact hole can be formed having a depth which does not exceed the lower surface 3B of the wire 3 at the insulation film 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing method. More specifically, the present invention relates to a method for forming an interlayer insulating film formed in a semiconductor device. More specifically, it relates to a method of forming an interlayer insulating film suitable for forming a contact hole.

[0002]

2. Description of the Related Art FIG. 6 is a schematic sectional view showing an example of a conventional semiconductor device. As shown in the figure, a wiring 3 made of metal or the like having a predetermined thickness is formed on the surface of a substrate 1 made of a semiconductor with a first interlayer insulating film 2 interposed therebetween.
Although not shown, transistor elements and wirings are also formed on the surface of the semiconductor substrate 1, and the metal wirings 3 are formed on the transistors and wirings covered with the first interlayer insulating film 2. Further, a second interlayer insulating film 4 is formed so as to cover the metal wiring 3. A contact hole 6 is opened in the second interlayer insulating film 4 so that an electrical contact with the wiring 3 can be made. The resist 5 is used to form the contact hole 6. After applying a resist 5 on the second interlayer insulating film 4, the resist 5 is exposed and developed according to a predetermined pattern to form an opening. The contact hole 6 is formed by etching the second interlayer insulating film 4 through this opening.

[0003]

The pattern is being miniaturized in order to reduce the cost of the semiconductor device (semiconductor chip). As a result, the contact hole 6 for electrically connecting to the wiring 3 made of metal aluminum or the like is also miniaturized. Therefore, in forming the contact hole 6, the opening position and the center position of the wiring 3 may be displaced from each other. In a portion where the bottom surface of the contact hole 6 and the wiring 3 are displaced, overetching of the second interlayer insulating film 4 occurs, and a slit-shaped hole 6E is formed next to the wiring 3. Depending on the etching conditions, the slit hole 6E may become deep and penetrate the first interlayer insulating film 2 to come into contact with a device or wiring formed on the semiconductor substrate 1 made of silicon or the like. This causes short-circuit defects between wires,
This is a cause of reduction in yield of semiconductor chips.

In order to prevent the formation of the slit hole 6E due to overetching of the contact hole 6, various measures have been taken conventionally. For example, the formed interlayer insulating films 2 and 4
The film thickness variation is reduced so that the film thickness is as uniform as possible over the entire substrate. In this way, by suppressing the variation in the film thickness, it is not necessary to give a width to the etching amount required when forming the contact hole 6,
As a result, overetching can be prevented. Thereby, the depth of the slit hole 6E can be suppressed. However, variations in film thickness are strongly affected by wiring density. Therefore, it is very difficult to optimize the manufacturing process by suppressing the film thickness variation for each product. As another measure, a measure for reducing misalignment between the contact hole 6 and the wiring 3 is taken. Essentially, if there is no misalignment between the contact hole 6 and the wiring 3, the above-mentioned problem of the slit hole 6E does not occur. Accurately aligning the contact hole 6 and the wiring 3 is very effective. However, since a misalignment occurs at a certain frequency during mass production, eliminating this completely increases the working time and raises the manufacturing cost.

[0005]

SUMMARY OF THE INVENTION In view of the above-mentioned problems of the conventional technique, an object of the present invention is to provide a film forming means for forming an interlayer insulating film having a composition suitable for forming a contact hole. The following measures have been taken to achieve this purpose. That is, according to the present invention, a wiring forming step of forming a wiring having a thickness sandwiched between an upper surface and a lower surface on a surface of a substrate made of a semiconductor, and a gas containing Si and a gas containing O are reacted to form a composition with Si and O. In the method of manufacturing a semiconductor device, including the step of depositing an insulating film to cover the wiring, the insulating film forming step comprises: It is characterized in that the composition ratio of Si and O is made to differ in at least two stages in the lower layer and the upper layer by changing the flow rate ratio of the gas containing O and the gas containing O.

Specifically, in the insulating film forming step, the flow rate ratio on the lower layer side is set to 0.35 or more in terms of Si / O,
The flow rate ratio on the upper layer side is switched to 0.33 or less to provide a difference in the composition of Si and O between the lower layer and the upper layer of the insulating film.
The method also includes an etching step of forming a contact hole in the insulating film to a depth that does not exceed the lower surface of the wiring by utilizing the difference in etching rate based on the difference in composition between Si and O.
In the insulating film forming step, an insulating film composed of Si and O is formed by bias sputtering using plasma. It also includes a post-process of continuously treating the insulating film from the upper layer to the lower layer.

According to the present invention, while the insulating film made of silicon oxide is being deposited to cover the wiring, the flow rate ratio of the mixed gas used as the film forming raw material is changed during the process from the lower surface to the upper surface of the wiring.
The composition of Si and O is made to differ in two steps in the lower layer and the upper layer. Specifically, the lower layer side of the insulating film made of silicon oxide has a relatively silicon-rich composition, and the upper layer side has a relatively oxygen-rich composition. The etching rate varies depending on the difference in the composition of silicon and oxygen. By utilizing this difference in etching rate, it becomes possible to form a contact hole in which over-etching is unlikely to occur. That is, when the composition is rich in silicon, the etching rate becomes slow and etching becomes difficult. By making the lower layer side of the interlayer insulating film silicon-rich, it is possible to effectively prevent the occurrence of slit holes that cause short-circuit defects.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a schematic sectional view showing an embodiment of a semiconductor device manufactured according to the present invention. The illustrated semiconductor device is manufactured by a manufacturing method including a wiring forming step and an insulating film forming step. In the wiring forming process, on the surface of the substrate 1 made of a semiconductor such as silicon,
The wiring 3 made of metallic aluminum or the like is formed through the first interlayer insulating film 2. A transistor device, a wiring layer, etc. are formed on the surface of the silicon substrate 1, and a first interlayer insulating film 2 is formed so as to cover the transistor device and the wiring layer. The wiring 3 is formed by forming a film of metal aluminum or the like by sputtering and then patterning it into a predetermined shape. The wiring 3 has a predetermined thickness sandwiched between the upper surface 3T and the lower surface 3B. Subsequently, an insulating film forming step is performed to form the second interlayer insulating film 4. Specifically, S
A gas containing i (for example, SiH ₄ gas) is reacted with a gas containing O (for example, O ₂ gas) to deposit an insulating film 4 made of silicon oxide composed of Si and O. The wiring 3 is covered by depositing the insulating film 4.

As a feature of the present invention, in the insulating film forming step, the insulating film 4 is deposited from the lower surface 3B to the upper surface 3 of the wiring 3.
On the way to T, the flow rate ratio of the gas containing Si (for example, SiH ₄ gas) and the gas containing O (for example, O ₂ gas) is changed so that the composition of Si and O is at least two steps in the lower layer 4L and the upper layer 4U. Different from. Specifically, in the insulating film forming step, the flow rate ratio on the lower layer 4L side is set to 0.35 or more in terms of Si / O, and the flow rate ratio on the upper layer 4U side is switched to 0.33 or less. As a result, the lower layer 4L of the second interlayer insulating film 4 is formed.
And the upper layer 4U are different in the composition of Si and O.
Due to such a difference in the composition of Si and O, a difference in etching rate occurs between the lower layer 4L and the upper layer 4U. The silicon-rich lower layer 4L has a relatively low etching rate and has a composition that is difficult to etch. On the other hand, the upper layer 4U having a relatively oxygen-rich composition has a high etching rate and is easy to etch. By utilizing such a difference in etching rate provided between the upper layer 4U and the lower layer 4L, it is possible to accurately form a contact hole in the insulating film 4 at a depth not exceeding the lower surface 3B of the wiring 3. . In the insulating film forming step described above, the insulating film 4 made of silicon oxide composed of Si and O can be formed by bias sputtering using plasma. As shown in FIG. 1, when silicon oxide is deposited by bias sputtering using plasma, the lower layer 4L is formed so as to fill the wiring 3 in the first stage. At the same time, a layer 4L ′ having the same composition as the lower layer 4L is also deposited on the upper surface 3T of the wiring 3. The upper layer 4U is to be deposited so as to cover the lower layers 4L and 4L '.

FIG. 2 is a schematic diagram showing an example of a CVD apparatus used for forming the insulating film 4 shown in FIG. Main CVD
The apparatus deposits silicon oxide on the substrate 1 by bias sputtering using plasma. This apparatus is equipped with source gas sources 11, 12, and 13 and is connected to a chamber 15 via a pipe 14. In the chamber 15, there is an upper electrode 17 and a stage 19 that also serves as a lower electrode.
And are included. The upper RF power supply 16 is connected to the upper electrode 17. Stage 19 that also serves as the lower electrode
A lower RF power source 18 is connected to the. Chamber 15
A vacuum evacuation system 20 is connected to the chamber so that the inside can be vacuum evacuated.

Silane gas SiH _{4 as} a material of the insulating film, oxygen gas O ₂ and carrier Ar gas are sent into the vacuum chamber 15 through the pipe 14. Vacuum chamber 15
Inside, plasma is generated by the RF power source 16 connected to the upper electrode 17. Silane SiH ₄ decomposed in this plasma and oxygen O ₂ are combined to form an insulating film made of SiO ₂ on the silicon substrate 1. At that time, the lower side R
The bias electric field supplied from the F power source 18 generates a sputter component. In this example, the plasma source is an IC
P is used. Typical CVD conditions using this apparatus are as follows: chamber pressure is 0.67 Pa, ICP power is 1300 W on the upper electrode side and 3000 W on the side surface.
The bias power on the lower electrode side is 3300W. SiH
The composition of the insulating film made of silicon oxide deposited on the substrate 1 is adjusted by appropriately adjusting the flow rate ratio of the ₄ gas and the O ₂ gas. In this specification, the flow rate ratio of the raw material gas is calculated in terms of Si / O. For example, SiH ₄ gas at 50 cm ³ / m
When introduced at a flow rate of in and O ₂ gas at a flow rate of 100 cm ³ / min, the flow rate ratio of both gases is 50/100 =
0.5, but 50 / when converted to Si / O
(100 × 2) = 0.25. However, the gas flow rate is
It is measured at 25 ° C. under a pressure of 101325 Pa.

The insulating film 4 of the semiconductor device shown in FIG. 1 is formed by using the CVD device shown in FIG. First, the lower layer 4L of the insulating film 4 is formed, but the film thickness thereof is smaller than that of the wiring 3. In other words, the boundary between the lower layer 4L and the upper layer 4U is below the upper surface 3T of the wiring 3 and above the lower surface 3B. By setting the flow rate ratio (element ratio) of Si and O to be 0.35 or more as the gas condition used for forming the lower layer 4L of the insulating film 4, the etching rate can be relatively reduced. After forming the lower layer 4L, the flow rate ratio in terms of Si / O is changed in the same chamber to form the upper layer 4U. The upper layer 4U has a role of completely covering the wiring 3 and ensuring electrical insulation from the wiring formed on the insulating film 4. The gas conditions used for forming the upper layer 4U are SiH in terms of Si / O.
The flow rate ratio of ₄ gas and O ₂ gas is set to 0.33 or less. As a result, the etching rate can be made sufficiently higher than that of the lower layer 4L. In particular, in order to form a good contact hole in the subsequent step, the flow rate ratio of the source gas of the lower layer 4L is set to 0.37 to 0.43 in terms of Si / O, while the flow rate ratio of the source gas of the upper layer 4U is set. In Si / O conversion.
It is preferably in the range of 25 to 0.28.

FIG. 3 schematically shows a state in which a contact hole is opened in the semiconductor device shown in FIG. To form a contact hole, a photoresist 5 serving as a mask is applied on the second interlayer insulating film 4, and a predetermined pattern opening is formed by using a lithography technique. The insulating film 4 is etched through the photoresist 5 having the opening formed therein to form the contact hole 6. The formation of the contact hole 6 is to successively process the insulating film 4 from the upper layer 4U to the lower layer 4L. In this case, the contact hole 6 is formed in the insulating film 4 to a depth not exceeding the lower surface 3B of the wiring 3 by utilizing the difference in etching rate provided between the upper layer 4U and the lower layer 4L. That is, when a positional deviation occurs between the opening formed in the photoresist 5 and the wiring 3, the contact hole 6 does not stop at the upper surface 3T of the wiring 3 and etching progresses toward the lower surface 3B of the wiring. . At this time, since the lower layer 4L is less likely to be etched than the upper layer 4U, the slit hole 6E formed at the tip of the contact hole 6 does not advance deeply and stops before reaching the lower surface 3B of the wiring 3.

FIG. 4 is a graph showing the relationship between the Si / O conversion flow rate ratio and the etching rate. When the Si / O conversion flow rate ratio is up to 0.33, a constant etching rate can be obtained. It can be seen that as the Si / O conversion flow rate is further increased, the etching rate is rapidly reduced. The present invention utilizes this phenomenon, and the flow rate ratio is 0.3.
The upper layer 4U of the insulating film is formed in the region of 3 or less, and the lower layer 4L is formed in the region of 0.33 or more.

Finally, FIG. 5 shows an example of an etching apparatus used for forming the contact hole shown in FIG. This etching apparatus is a parallel plate type with a narrow gap. An upper electrode 27 and a lower electrode 29 are attached to the chamber 25. The upper electrode 27 has an upper RF power source 26.
Are connected. A lower RF power source 28 is connected to the lower electrode 29. The substrate 1 to be processed is placed on the stage integrated with the lower electrode 29. A shower plate 28 made of silicon is attached to the upper electrode 27 so that the working gas introduced from the pipe 24 is ejected. Working gas is supplied from the shower plate 23 of the upper electrode 27 to the upper electrode 27 at 60 MHz.
RF is applied to the lower electrode 29 while plasma of 2 MHz is applied to the lower electrode 29 to etch the insulating film made of silicon dioxide formed on the substrate 1. The gas mainly used is C ₄ F ₈ / Ar
/ O ₂ , and the flow rate ratio is 11/400/8 (cm ³ /
min). The pressure in the chamber 25 is 4.0P.
RF power applied to the upper electrode 27 is 27 MH
z is 2000 W, RF power applied to the lower electrode 29 is 8
It is 1200 W at 00 kHz.

[0016]

As described above, according to the present invention, the slit depth of the contact hole is suppressed by changing the formation condition (Si / O composition ratio) of the interlayer insulating film between the upper layer and the lower layer. There is. As a result, it is possible to allow a larger variation in film thickness of the interlayer insulating film than in the conventional case. or,
It is possible to allow a larger misalignment between the contact hole and the wiring. As a result, it is possible to use a lower cost manufacturing apparatus as compared with the conventional one. Further, the throughput of the manufacturing process can be increased as compared with the conventional case. As described above, the manufacturing cost of the semiconductor device can be reduced. Also, good electrical characteristics of the contact hole can be obtained.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view of a semiconductor device manufactured according to the present invention.

FIG. 2 is a schematic view showing an example of a CVD apparatus used in the semiconductor device manufacturing method of the present invention.

3 is a cross-sectional view showing a state in which a contact hole is formed in the semiconductor device shown in FIG.

FIG. 4 is a graph showing the relationship between the Si / O conversion flow rate ratio and the etching rate.

5 is a schematic cross-sectional view showing an example of an etching apparatus used to form the contact holes shown in FIG.

FIG. 6 is a schematic view showing a problem of a conventional semiconductor device.

[Explanation of symbols]

1 ... Substrate, 2 ... First interlayer insulating film, 3 ... Wiring, 4 ... Insulating film, 4L ... Lower layer, 4U ... Upper layer, 5 ... Photoresist, 6 ... Contact holes

Claims (5)

[Claims] 1. A wiring forming step of forming a wiring having a thickness sandwiched between an upper surface and a lower surface on a surface of a substrate made of a semiconductor, and a gas containing Si and a gas containing O are reacted to form a composition of Si and O. In the method of manufacturing a semiconductor device, which includes a step of depositing an insulating film to cover the wiring, the insulating film forming step is performed to remove the Si during the deposition of the insulating film from a lower surface to an upper surface of the wiring. A method of manufacturing a semiconductor device, characterized in that the composition ratio of Si and O is made to differ in at least two stages in the lower layer and the upper layer by changing the flow rate ratio of the gas containing and the gas containing O. 2. In the insulating film forming step, the flow rate ratio on the lower layer side is set to 0.35 or more in terms of Si / O, and the flow rate ratio on the upper layer side is switched to 0.33 or less to change the insulation rate. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the composition of Si and O is different between the lower layer and the upper layer of the film. 3. An etching step of forming a contact hole in the insulating film to a depth not exceeding the lower surface of the wiring by utilizing the difference in etching rate based on the difference in composition of Si and O. The method for manufacturing a semiconductor device according to claim 2. 4. The method of manufacturing a semiconductor device according to claim 1, wherein in the insulating film forming step, an insulating film composed of Si and O is formed by bias sputtering using plasma. 5. The method of manufacturing a semiconductor device according to claim 1, further comprising a post-step of continuously treating the insulating film from an upper layer to a lower layer.