JP2003007060A - Semiconductor memory and its control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory in which late-write operation by which masking of write data can be performed appropriately is performed and its control method. SOLUTION: A semiconductor memory has data registers 103-1, 103-2 latching write-in data, DQ write-driver 101-1, 101-2 driving a data line in accordance with write data, DM registers 117-1, 117-2 latching a control signal deciding whether write data is masked or not. In a cycle of a first write command, a first write data is latched in a data register, while a first control signal deciding whether the first write data is masked or not is latched to the DM register conforming to a first data mask signal. In a successive cycle of a second write command, a DQ write-driver is driven conforming to the first control signal latched in the DM register.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a control method thereof, and more particularly to a write data masking technique in a semiconductor memory device performing a late write operation. The present invention is, for example, a high-speed cycle (Fast Cycle) synchronous DRAM (SDR-FCRAM) having a function of reading and writing random data from a memory cell array at a high speed, and further, a double data transfer rate that doubles the data transfer rate. It is applied to a data rate synchronous DRAM (DDR-FCRAM).

[0002]

2. Description of the Related Art (Recent SDR → DDR conversion situation) As a trend of semiconductor memories in recent years, general-purpose semiconductors that have been conventionally used to fill a gap in data transfer rate between a controller side such as a CPU or MPU and a memory. DRA
Instead of M, a DRAM having a special function for burst data transfer is generally used.
Examples of these DRAMs are a Rambus specification DRAM (hereinafter, RDRAM) and a synchronous (Syn).
CRONUS) DRAM (hereinafter referred to as SDRAM). Particularly, in SDRAM, not only is the frequency of a basic clock (hereinafter referred to as CLK) increased, but also Double Data R that inputs and outputs data at a high speed.
The specifications of ate (hereinafter referred to as DDR) have been established and have been commercialized. In the DDR specifications, Si that performs data input / output in synchronization with the conventional rising edge of CLK is used.
For single data rate (SDR),
CLK, as is done in Rambus DRAM
Data is input / output at twice the speed in synchronization with both the rising and falling edges of.

(Recent Background of DDR → FCRAM Development) While architectures for increasing the data transfer rate are being actively developed, the run switch (L
In the so-called network field such as AN switch) and routers, Static RAM has been conventionally used.
(SRAM) is used. This is because in the network field, random access of cell data in the memory core, that is, speeding up of access when the row (row) address changes is important. Considering the application of DRAM to the network field, DRAM
A certain amount of time (referred to as core latency) required for destructive reading, amplification operation, and precharge operation for accessing the memory core, which is peculiar to the memory cell, becomes a bottleneck.
Due to this core latency, the random cycle time (hereinafter referred to as tRC) of the memory core cannot be shortened, so that it is difficult for the conventional DRAM product to enter the network field.

In order to solve this problem, tRC has been suppressed to less than half that of the conventional DRAM by pipelining the access to the memory core and the precharge operation.
A so-called high-speed cycle RAM (FCRAM) has been proposed, and its commercialization is about to begin, mainly in the network field.

Regarding the basic system for reading data in the FCRAM, for example, International Publication No. WO98
/ 56004 (Fujioka et al.). Also, F
Regarding the data writing system of the CRAM, for example, Japanese Patent Laid-Open No. 2000-137983 (Tsuchida et al.) Describes a delayed write operation (Delayed Write Operation).
method) has been proposed. This method
In the present application, a late write operation (Late Write p
eration).

(Late write operation) SDRAM and DDR
In the case of the write operation in the SDRAM, after receiving the write command and the address to be written, the write data for the burst length is received in the subsequent clock cycle, and basically the write operation to the memory cell is performed during the command cycle. Complete. Here, for convenience, this operation is referred to as a conventional light operation (conventio).
nal write operation).

On the other hand, the late write operation proceeds in the following manner. FIG. 13 is a timing chart showing the late write operation of the FCRAM. FCR
Write command WRT for late write operation of AM
At the same time, after receiving the address AD0 to be written,
The write data D0 to D1 corresponding to the burst length (here, burst length = 2) are received in consecutive clock cycles, and the information is temporarily stored in the newly provided address register and data register. Further, immediately after the next write command is given, the data D0 to D are stored in the address of the memory cell corresponding to the address AD0 received earlier.
While writing "1", the address AD1 and the data D2 to D3 received in the write cycle are overwritten in the two registers.

That is, in the conventional write operation,
Write to the memory cell after receiving the last data,
The flow of precharging the memory core is adopted. On the other hand, in the late write operation, as soon as the write command is received, the operation of writing the data held in the previous cycle to the memory cell is started. Therefore, the time from the write command to the completion of precharge of the memory core is shortened, and as a result, the random cycle tRC can be shortened.

FIG. 14 is a block diagram showing a conventional semiconductor memory device performing a late write operation. This device includes a memory core unit 100, a data input buffer 108, a data output buffer 110, and a serial / parallel conversion circuit 1.
09, a parallel-serial conversion circuit 111, and a write timing control circuit 112.

The data input buffer 108 receives write data at the DQ input / output terminal 107. The data output buffer 110 outputs read data to the outside of the chip.
The serial-parallel conversion circuit 109 converts the serial data output from the data input buffer into parallel data and outputs the parallel data to the write data lines WDe and WDo. The parallel-serial conversion circuit 111 uses the read data line RD.
The parallel data of e and RDo are transferred to the data output buffer as serial data. The write timing control circuit 112 receives the write command and generates a data register transfer signal WXFR for determining the timing of writing the data in the data register, while determining the timing of writing the data held in the data register in the memory cell MC. DQ write driver drive signal WE
To generate.

The memory core section 100 includes a DQ buffer section, a row decoder 106, and a bit line sense amplifier SA.
And column switches 105-1 and 105-2, and column decoders 104-1 and 104-2. The DQ buffer unit includes DQ read amplifiers 102-1 and 102-2,
It is composed of DQ write drivers 101-1 and 101-2 and data registers 103-1 and 103-2. The row decoder 106 includes a memory cell MC and a bit line pair B.
The word line WL for connecting L and bBL is controlled. The bit line sense amplifier SA amplifies the data on the bit line pair. The column switches 105-1 and 105-2 are
The bit line pair and the I / O data line pair MDQ and bMDQ are connected. The column decoders 104-1 and 104-2 control column switches by the column selection line CSL.

FIG. 15 is a circuit diagram showing details of the DQ write driver and the data register in the DQ buffer section of the device shown in FIG. The DQ write driver 101 is
P-channel type MOS transistors 201 to 203 and N
Channel type MOS transistors 204 to 205 and NO
R gates 206 to 209 and AND gates 210 to 21
1 and inverters 212 to 213. The inverter 212 receives the write driver drive signal WE at its input terminal and outputs the inverted signal bWE. The signal MDQEQ for precharging the MDQ line pair is input to the input terminal of the inverter 213,
The inverted signal bMDQEQ is output.

Among the elements constituting the driver section on the bMDQ line side, the inverted signal of the data held in the WE and the data register is input to the AND gate 210 at the input terminal b.
WDIN is connected. The output terminal of the AND gate 210 is connected to one input terminal of the NOR gate 206,
MDQEQ is input to the other input terminal of the NOR gate 206. The output terminal of the NOR gate 206 is connected to the gate terminal of the P-channel MOS transistor 201, the source terminal is connected to the power supply, and the drain terminal is bM.
Connected to DQ line. The bWE and bWDIN are connected to the input terminal of the NOR gate 207. The output terminal of the NOR gate 207 is connected to the gate terminal of the N-channel MOS transistor 204, the source terminal is connected to the ground point, and the drain terminal is connected to the bMDQ line.

Among the elements forming the driver section on the MDQ line side, the WE and WDIN which is the data held in the data register are connected to the input terminal of the AND gate 211. The output terminal of the AND gate 211 is connected to one input terminal of the NOR gate 208, and the NOR gate 2
MDQEQ is input to the other input terminal of 08. P
The output terminal of the NOR gate 208 is connected to the gate terminal of the channel MOS transistor 203, the source terminal is connected to the power supply, and the drain terminal is connected to the MDQ line. The input terminals of the NOR gate 209 are bWE and W.
It is connected to DIN. The output terminal of the NOR gate 209 is connected to the gate terminal of the N-channel MOS transistor 205, the source terminal is connected to the ground point, and the drain terminal is connected to the MDQ line.

The data register 103 includes an inverter 21.
4 to 215 and clocked inverters 216 to 217 that are clocked by WXFR that controls the fetch of the write data WD. The internal data bus WD is connected to the input terminal of the clocked inverter 216, and the output terminal is connected to the input terminal of the inverter 214 and the output terminal of the clocked inverter 217. The output terminal of the inverter 214 is the clocked inverter 21.
7 and the input terminal of the inverter 215, and becomes WDIN which is the latched data. The output of the inverter 215 becomes bWDIN which is its inverted signal.

FIG. 16 is a timing chart showing the operation of the device shown in FIG. Here, the cycle of the first write command WRT is "i-1" cycle, and the second write cycle is "i" cycle. Write data D0 to D given from the DQ terminal in the "i-1" cycle
1 is taken into the inside of the chip by the data input buffer 108, and the serial-parallel conversion circuit 109 respectively makes internal data buses WDe and WD for Even and Odd.
sent to o. At this time, the column selection line CS of the previous cycle
When the operation of L is completed, WXFR which is a data latch take-in signal becomes "H" and WDe and WDo are taken into the latch unit via the clocked inverter 216, respectively, and when WXFR becomes "L". At the same time, the latched data WDINe and WDINo are fixed.

Next, after the word line WL is selected in response to the WRT command of the "i" cycle, the MDQ line pair equalize signal MDQEQ becomes "L" and the precharge of the MDQ line pair is released. At the same time, the write driver drive signal WE becomes “H” and the latched data WDI
MDQ of Ne and WDINo of Even and Odd respectively
These are written to the bit line by being transferred to the bMDQ line and the subsequent CSL becoming “H”. As a result, the write data D0 to D1 follow the thick arrows,
In the next write cycle, data is written in the memory cells MC of Even and Odd.

(Register read operation) On the other hand, as a problem in performing such a late write operation, the write data is latched in the data register and written to the memory cell before the next write command is input, that is, still in the memory cell. It is conceivable that a read command may be input to the same address in the state where the read command is not read. In such a case, it is necessary to read the data from the data register, not from the memory cell, to maintain the coherency of the data. With respect to such a method, the above-mentioned Japanese Patent Laid-Open No. 2000-1
No. 37983. In the present application, this operation will be referred to as a register read operation. A configuration for realizing this register read will be described below with reference to the drawings.

FIG. 17 is a block diagram showing a conventional semiconductor memory device which performs a late write operation and a register read operation. In FIG. 17, the same components as those shown in FIG. 14 are designated by the same reference numerals, and the description thereof will be omitted. Other components will be described. In the device shown in FIG. 17, an address input terminal 113, an address input buffer 114, and an address register 115 are arranged.
The address register 115 is the address input buffer 11
The output AIN of 4, the write command WRT, and the read command RDE are input, and the core address bus ALTC for selecting a row and a column is output. The address input terminal 113, the address input buffer 114, and the address register 115 are not shown in FIG.
It is safe to assume that the device shown in FIG. As a new element in the present device, a consistency determiner 116 is provided which inputs the address given in the previous write cycle and the address given in the subsequent read cycle and compares them. Consistency determiner 1
16 outputs a signal WDRD for performing a register read operation if both addresses match.

FIG. 18 is a circuit diagram showing details of the address register 115 and the consistency determiner 116 of the device shown in FIG. The address signal input from the address input terminal 113 is supplied to the inside of the chip as the internal address signal AIN by the address input buffer 114. The address register 115 includes the clocked inverters 300 to.
It comprises 303 and inverters 305 to 306.
The internal address signal AIN is the clocked inverter 300.
Connected to the input terminal of the
5 and the output terminal of the clocked inverter 301. The output terminal of the inverter 305 is connected to the input terminal of the clocked inverter 301 and the input terminal of the clocked inverter 302. The output terminal of the clocked inverter 302 is connected to the input terminal of the inverter 306 and the output terminal of the clocked inverter 303. The output of the inverter 306 becomes a signal AREG which holds the address at the time of the write cycle.

In consideration of the fact that this circuit configuration is actually used, the clocked inverter 30 for switching the address transfer path between the write cycle and the read cycle.
7-308 and inverters 309-310 for holding address information when both of these two clocked inverters are off. AREG is input to the input terminal of the clocked inverter 307, and when the write command WRT is “H”, the output is the inverter 30.
9 is transmitted to the input terminal. Clocked inverter 30
AIN, which is the output of the address input buffer 114, is input to the input terminal 8 and the read command RDE is "H".
At that time, the output is transmitted to the input terminal of the inverter 309. The inverters 309 and 310 form a latch circuit connected in cascade, and the output thereof is a core address bus ALTC for selecting a row or a column.

The consistency determiner 116 comprises an exclusive logic NOR gate (Ex-NOR) 311. AREG and ALTC are connected to the input terminal of the consistency determiner 116, and the output is W which is a signal for controlling the register read.
It becomes DRD.

FIG. 19 is a circuit diagram showing details of the DQ buffer section of the device shown in FIG. DQ write driver 10
Since 1 and the data register 103 are the same as those shown in FIG. 15, the description thereof is omitted here. In the circuit configuration shown in FIG. 19, the DQ read amplifier 102, the first and second switches SW1 and SW2, the multiplexer 218, the NAND gate 219, and the NOR gate 2
20, P-channel MOS transistor 221, N
A channel type MOS transistor 222 is provided.
The DQ read amplifier 102 amplifies the read data from the bit line pair via the MDQ line pair. The first switch SW1 is controlled by the WDRD signal,
It conducts when RD is "H". Second switch SW2
Is controlled by the WDRD signal and conducts when WDRD is "L". The multiplexer 218 is the first
And the signal from the second switch, whichever is conductive, is selected and output.

The output terminal of the DQ read amplifier 102 is connected to the first input terminal of the multiplexer 218 via the second switch SW2. The output terminal WDIN of the data register 103 is connected to the second input terminal of the multiplexer 218 via the first switch SW1. The output terminal of the multiplexer 218 is connected to the first input terminals of the NAND gate 219 and the NOR gate 220, respectively. A timing control signal RDP for outputting read data to RD is connected to the second input terminal of the NAND gate 219. A NAND gate 219 is provided at the gate terminal of the P-channel MOS transistor 221.
Output terminal is connected, the source terminal is connected to the power supply,
The drain terminal is connected to the read data bus RD.
The second input terminal of the NOR gate 220 is connected to bRDP which is an inverted signal of the RDP. N channel type M
The output terminal of the NOR gate 220 is connected to the gate terminal of the OS transistor 222, the source terminal is connected to the ground point, and the drain terminal is connected to RD.

FIG. 20 is a timing chart showing the register read operation of the device shown in FIG. In this timing chart, a read command corresponding to the same address A0 is input after a write command corresponding to the address A0. First, the address signal A0 input from the ADD terminal by the write command is taken into the address register by the clocked inverter 300 in FIG. 18 during the “H” period of the signal WRT indicating the write command, and the WRT becomes “L”. When it becomes, it will be held as AREG. On the other hand, the write data D0 to D1 given by the write command receive WDe / WDe / in response to the change signal WXFR of the data register 103 becoming “H”.
It is transferred from WDo to WDIN and held when it goes to "L".

Next, a read command is given to the same address as the address A0 input by the write command. In this case, the address A0 receives the read command RDE signal at "H"
It is output as ALTC from the output of 9. This information is compared with the AREG held by the write command by the consistency determiner 116, and when a match is detected, the signal WDRD controlling register read becomes "H".

The WDRD signal controls the changeover switches SW1 and SW2 in FIG. 19, and when WDRD is "H", SW1 is closed while SW2 is opened.
As a result, the multiplexer 218 outputs WDIN, which is the output of the data register, and the data of WDIN is transferred to the internal read data bus RD when the read timing control signal RDP becomes "H".

According to the above-mentioned configuration, the case where the read command is input to the same address with respect to the data written in the data register by the write command and not actually written in the memory cell is dealt with. can do. That is, in this case, the data can be read from the data register instead of the memory cell, and the data coherency can be maintained.

[0029]

(Data mask function of DM system) Conventional SDR-SDRAM and DDR-SDR
The AM performs so-called burst data transfer in which a series of continuous data is serially transferred according to a preset burst length. For this reason, a data mask function is employed to prevent particular data in the burst direction from being written to or read from the memory core. Among these, according to the current specifications of DDR-SDRAM,
Only the so-called write data mask function is adopted.
The write data mask function is a series of burst write data input in synchronization with CLK and a data mask signal (D
It is a function to input M) and not write data. In the present application, this function will be referred to as a DM system.

(VW system data mask function) Further, recently, a new data mask system has been devised in place of the DM system which has been conventionally used. One of them is Va
A method called a liable write method (hereinafter referred to as a VW method), which is being studied for adoption in the next-generation DDR standard DDR2. In this method, the mask information is not input at the same time as the burst write data, but when the write command is issued, burst length information coded using an unused address terminal or the like is input. Here, in addition to the burst length set by a mode register set command (hereinafter referred to as MRS) in advance, a burst length that is valid only during writing can be set. As a result, burst writing after the designated bit is not performed, and the same effect as masking the subsequent bits can be realized. With this method, it is not possible to perform a masking operation on any bit of the burst data (it is specified that a certain bit is masked after the bit). However, it is only necessary to input the mask information at the same timing as that of the address signal (synchronized with the rising edge of CLK), and there is an advantage that it is easy to deal with a high CLK frequency.

As described above, some proposals have been made regarding the method for speeding up the random cycle such as the late write operation and the register read operation. However, sufficient proposals have not been made regarding the technology for realizing the data mask function that is actually required for commercializing FCRAM.

The present invention has been made in view of the above problems of the prior art, and provides a semiconductor memory device performing a late write operation and a control method thereof, which can appropriately mask write data. The purpose is to

[0033]

The first aspect of the present invention is as follows.
A semiconductor memory device comprising: a data register for latching data to be written in a memory cell; a DQ write driver for driving a data line according to the write data latched in the data register; and the write data according to a data mask signal. And a DM register for latching a control signal for masking whether to mask the first write data according to the first data mask signal in the cycle of the first write command. Latching a first control signal in the DM register,
In the following second write command cycle,
The DQ write driver is driven according to the first control signal latched in the DM register to control writing of data to the memory cell.

A second aspect of the present invention is a semiconductor memory device, comprising a data register for latching data to be written in a memory cell, and a DQ for driving a data line according to the write data latched in the data register. A DM for latching a control signal for masking the write data according to a write driver and a data mask signal
A register for latching first write data in the data register in accordance with a first data mask signal in the cycle of the first write command, and in accordance with the first data mask signal for the first write data. A first control signal for whether or not to mask write data is latched in the DM register, and the DQ write is performed in accordance with the first control signal latched in the DM register in the next cycle of the second write command. It is characterized in that the driver is driven to selectively write the first write data latched in the data register to the memory cell.

A third aspect of the present invention is a semiconductor memory device, comprising a data register for latching data to be written in a memory cell, and a DQ for driving a data line according to the write data latched in the data register. A DM for latching a control signal for masking the write data according to a write driver and a data mask signal
A register for latching the first write data in the data register without following the first data mask signal in the cycle of the first write command, and according to the first data mask signal, First
A first control signal as to whether or not to mask the write data of the DQ is latched in the DM register, and the DQ is latched in the DM register according to the first control signal latched in the subsequent second write command cycle. It is characterized in that a write driver is driven to selectively write the first write data latched in the data register to the memory cell.

In the case of the semiconductor memory device according to the first to third aspects, the first data mask is set so as to latch the first control signal in the DM register in the cycle of the first write command. D by signal
The M register can be set. Instead, in the cycle of the first write command, the DM is used as the first control signal with the first data mask signal.
Can be latched in a register.

The semiconductor memory devices of the first to third aspects are provided corresponding to the address register for latching the address corresponding to the memory cell in which data is written and the DQ write driver, and are provided on the data line. A DQ read amplifier that amplifies the read data that has been read,
The DQ is output according to the consistency determiner that determines whether the address associated with the read command and the address associated with the write command immediately before that match, and the output of the DM register and the output of the consistency determiner. A switching circuit for switching between read data amplified by a read amplifier and data latched in the data register and supplying the read data line with the switching circuit, further comprising a first address signal in the cycle of the first write command. In the address register, and in the cycle of the read command performed between the first and second write commands, the address associated with the read command and the first address match the address determined by the consistency determiner. And the first control latched in the DM register. If the number does not mask a portion of the first write data corresponding to the matching address, the switching circuit shuts off the output of the DQ read amplifier and latches the first write data in the data register. Can be designed to supply the portion corresponding to the matching address to the read data line.

According to a fourth aspect of the present invention, the first write data is latched in the cycle of the first write command, and the first write data is transferred to the memory cell in the cycle of the next second write command. A method of controlling a semiconductor memory device for performing a late write operation for writing to a first write command cycle according to a first data mask signal in a cycle of the first write command.
Latching a first control signal for whether to mask the write data of No. 2 in a state independent of the first write data, and in a cycle of the second write command,
The writing of data to the memory cell is controlled according to the latched first control signal.

Further, in the semiconductor memory device control method according to the fourth aspect, further, in the cycle of the first write command, the first address signal is latched, and the first and second write commands are delayed. In the cycle of the read command performed in step 1, when the address accompanying the read command and the first address match and the latched first control signal does not mask the first write data, it is latched. It can be set to read the first write data.

Furthermore, the embodiments of the present invention include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, when the invention is extracted by omitting some of the constituent elements shown in the embodiment, when omitting the extracted invention, the omitted part is appropriately supplemented by a well-known conventional technique. It is something that will be done.

[0041]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. In the following description, constituent elements having substantially the same functions and configurations are designated by the same reference numerals, and redundant description will be given only when necessary.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
3 is a block diagram showing a semiconductor memory device having a DM-type data mask function according to the embodiment of FIG. This device
A memory core unit 100, a data input buffer 108,
The data output buffer 110, the serial / parallel conversion circuit 109, the parallel / serial conversion circuit 111, the write timing control circuit 112 ′, and the DM input terminal 118.
And a DM parallel-to-serial conversion circuit 120.
The device also includes an address input terminal 113, an address input buffer 114, and an address register 115. The address register 115 inputs the output AIN of the address input buffer 114, the write command WRT, and the read command RDE, and outputs the core address bus ALTC for selecting a row and a column.

The data input buffer 108 receives write data at the DQ input / output terminal 107. The data output buffer 110 outputs read data to the outside of the chip.
The serial-parallel conversion circuit 109 converts the serial data output from the data input buffer into parallel data and outputs the parallel data to the write data lines WDe and WDo. The parallel-serial conversion circuit 111 uses the read data line RD.
The parallel data of e and RDo are transferred to the data output buffer as serial data. The write timing control circuit 112 ′ receives the write command and determines the timing of writing the data to the even and odd data registers, respectively, and a data register transfer signal WX.
While generating FRe and WXFRo, a write driver drive signal WE that determines the timing of writing the data held in the data register to the memory cell MC is generated.

A data mask signal is input to the DM input terminal 118 in synchronization with the write data from the DQ terminal. The DM input buffer 119 takes in the data mask signal inside the chip. DM parallel-serial conversion circuit 12
0 indicates the DMI of the serial output of the DM input buffer 119.
Converted to Ne, DMINo parallel data and input to the write timing control circuit to WXFRe, WXFR
Controls ON / OFF of o.

The memory core section 100 includes a DQ buffer section, switches SW3 and SW4, and a row decoder 106.
, Bit line sense amplifier SA, and column switch 10
5-1, 105-2 and column decoders 104-1, 1
04-2 and. The DQ buffer section includes DQ read amplifiers 102-1 and 102-2 and a DQ write driver 10.
1-1, 101-2 and data registers 103-1, 1
03-2 and DM registers 117-1, 117-2. In the switches SW3 and SW4, the write driver drive signal WE output from the write timing control circuit 112 ′ receives the DQ write drivers 101-1 and 101-.
Existing on the path up to 2, and DM registers 117-1, 1
ON / OFF is controlled according to the state of the output of 17-2. The row decoder 106 controls the word line WL for connecting the memory cell MC and the bit line pair BL, bBL. The bit line sense amplifier SA amplifies the data on the bit line pair. The column switches 105-1 and 105-2 are
The bit line pair and the I / O data line pair MDQ and bMDQ are connected. The column decoders 104-1 and 104-2 connect the column switches 105-1 and 105-2 to the column selection line C.
Controlled by SL.

FIG. 2 shows a DQ write driver, a data register, and a DM in the DQ buffer section of the device shown in FIG.
It is a circuit diagram which shows the detail of a register. The DQ write driver 101 includes P-channel type MOS transistors 201 to 201.
203 and N-channel MOS transistors 204-2
05, NOR gates 206 to 209, AND gates 210 to 211, and an inverter 213. The signal MDQEQ for precharging the MDQ line pair is input to the input terminal of the inverter 213, and the inverter 213 outputs the inverted signal bMDQEQ.

Of the elements forming the driver section on the bMDQ line side, one input terminal of the AND gate 210 has a WGT corresponding to the terminal on the opposite side of the write driver drive signal WE of the switches SW3 and SW4 in FIG. Are connected. The other input terminal of the AND gate 210 has a signal bWD which is an inverted signal of the data held in the data register.
IN is connected. The output terminal of the AND gate 210 is N
NOR gate 206 connected to one input terminal of NOR gate
MDQEQ is input to the other input terminal of the gate 206. The output terminal of the NOR gate 206 is connected to the gate terminal of the P-channel MOS transistor 201, the source terminal is connected to the power supply, and the drain terminal is connected to the bMDQ line. To the input terminal of the NOR gate 207, bWGT and bWDIN which are the inverted signals of the WGT are connected. The output terminal of the NOR gate 207 is connected to the gate terminal of the N-channel type MOS transistor 204,
The source terminal is connected to the ground point and the drain terminal is bMD
Connected to the Q line.

Among the elements constituting the driver section on the MDQ line side, the W is connected to one input terminal of the AND gate 211.
WDI which is data held in GT and data register
N is connected. The output terminal of the AND gate 211 is N
Is connected to one input terminal of the OR gate 208, and NOR
MDQEQ is input to the other input terminal of the gate 208. The output terminal of the NOR gate 208 is connected to the gate terminal of the P-channel MOS transistor 203, the source terminal is connected to the power supply, and the drain terminal is connected to the MDQ line. The input terminal of the NOR gate 209 has the b
WGT and WDIN are connected. N-channel type MOS
The NOR gate 20 is provided at the gate terminal of the transistor 205.
9 output terminals are connected, the source terminal is connected to the ground point, and the drain terminal is connected to the MDQ line.

The data register 103 includes an inverter 21.
4 to 215 and clocked inverters 216 to 217 that are clocked by WXFR that controls the fetch of the write data WD. The internal data bus WD is connected to the input terminal of the clocked inverter 216, and the output terminal is connected to the input terminal of the inverter 214 and the output terminal of the clocked inverter 217. The output terminal of the inverter 214 is the clocked inverter 21.
7 and the input terminal of the inverter 215, and becomes WDIN which is the latched data. The output of the inverter 215 becomes bWDIN which is its inverted signal.

The DM register 117 is a P channel type MO.
The S transistor 223, the N-channel type MOS transistor 224, the inverters 225 to 226, the clocked inverter 227, and the NAND gate 228 are included. The signal bDMPR, which is a signal for precharging the DM register, is input to the gate terminal of the P-channel MOS transistor 223, and the source terminal is connected to the power supply. The drain terminal of the P-channel MOS transistor 223 is connected to the drain terminal of the N-channel MOS transistor 224, the input terminal of the inverter 225, and the output terminal of the clocked inverter 227. The same WXFR as the fetch signal of the data register is connected to the gate terminal of the N-channel MOS transistor 224, and the source terminal is connected to the ground point. Inverter 22
The output terminal of 5 is connected to the input terminal of the clocked inverter 227 and one input terminal of the NAND gate 228. The write driver drive signal WE is connected to the other input terminal of the NAND gate 228. NAND gate 2
The output terminal of 28 serves as the bWGT and is connected to the input terminal of the inverter 226. The output of the inverter 226 becomes WGT.

FIG. 3 is a timing chart showing the operation of the device shown in FIG. The data mask operation during late write in this device will be described below with reference to FIG.

In the cycle of the first write command WT (a), D0 and D1 input to the DQ terminal 107 are input.
Are taken in via the data input buffer 108 in synchronization with the rising edge and the falling edge of CLK, respectively. D0 and D1 are converted into parallel data by the serial / parallel conversion circuit 109 and transferred to the respective write data buses WDe and WDo. Here, the subscript e is C
E indicating an even bit corresponding to the rising edge of LK
Similarly, the subscript o also indicates Odd indicating an odd bit corresponding to the falling edge of CLK.

These data WDe and WDo are respectively E
It is input to the data register provided in the ven memory core and the Odd memory core. These data are WX
When FR becomes "H", it is taken into the data register, and when it becomes "L", it is latched and held until the next write command WT (b) arrives. on the other hand,
DM given from the DM input terminal 118 in synchronization with DQ
The signal is converted into parallel data by the DM serial / parallel conversion circuit 116 via the DM input buffer 119, and is input to the write timing control circuit as DMINe and DMINo.

Here, the first write command WT (a)
At, the data mask is applied to the data D0. Therefore, the DMI is synchronized with the rising edge of CLK.
It is prevented that Ne becomes “H” and WXFRe becomes “H”. As a result, the data D0 on WDe is not taken into the data register, and the value of WDINe does not change. However, since the DMINo on the Odd side remains "L", WXFRo becomes "H", and only the data D1 on WDo is taken into the data register, and WDINo
Changes. The fetched data is latched at the same time when WXFRo becomes “L” and held until the next write command WT (b) is given.

In the DM register, in the cycle of the first write command WT (a), bDMP is performed at the timing when the writing of the data of the previous cycle to the memory cell is completed.
R becomes "L" and bDMLT of each Even / Odd
C is reset to "L" once. In the cycle of the first write command WT (a), WX is performed by DMINe.
Since FRe is masked, even side bDML
TC is not set, while bDML on Odd side
TC is set to "H".

When the next write command WT (b) is given, at the timing when the write driver drive signal WE becomes "H", the WG on the Odd side whose bDMLTC is "H".
Only To becomes "H". As a result, only the data D1 held at the output WDINo of the data register is transferred to the IO data line MDQ / bMDQ, and the column selection line CS
As L becomes “H”, the bit line pair BL / bBL is written.

As described above, the write data input in a certain write command cycle and the data mask signal DM input in synchronism with the write command cycle are respectively stored in the data register and the DM register provided inside the memory core. Independently maintained. Then, when the next write command is given, only the data of the bit that has not been masked is written to the memory cell, and the masked data is not written. Therefore, by using this configuration, it is possible to realize the write data mask function by the DM method even when performing the late write operation.

(Second Embodiment) FIG. 4 shows a second embodiment of the present invention.
3 is a block diagram showing a semiconductor memory device having a DM-type data mask function according to the embodiment of FIG. In this embodiment, the DM system data mask function is added to the late write system corresponding to the register read shown in FIG. That is, in the present device, the consistency determiner 116 that receives the address given in the previous write cycle and the address given in the subsequent read cycle and compares them is provided in addition to the configuration shown in FIG. To be done. The consistency determiner 116 outputs a signal WDR for performing a register read operation if the two addresses match.
D is output, and this output is input to the DQ buffer unit in the memory core.

FIG. 5 shows a data register 103, a DM register 117, and a DQ buffer 117 in the DQ buffer section of the apparatus shown in FIG.
FIG. 3 is a circuit diagram showing details of a portion that controls data at the time of reading. WDIN which is the output of the data register 103
Is connected to one input terminal of the multiplexer 218 via the switch SW1. The output terminal of the read amplifier 102 is connected to the other input terminal of the multiplexer via the switch SW2. The output terminal of the multiplexer 218 is a NAND gate 219 and a NOR gate 220.
Is connected to one of the input terminals.

RDP is connected to the other input terminal of the NAND gate 219. The output terminal of the NAND gate 219 is connected to the gate terminal of the P-channel MOS transistor 221. BRDP is connected to the other input terminal of the NOR gate 220. The output terminal of the NOR gate 220 is connected to the gate terminal of the N-channel type MOS transistor 222. P-channel MOS transistor 2
The drain terminals of the N-type MOS transistor 21 and the N-channel type MOS transistor 222 are connected to the read data line RD, and the source terminals thereof are connected to the power source and the ground point.

BD which is a node in the DM register 117
The MLTC is connected to the first input terminal of the NAND gate 230. The second input terminal of the NAND gate 230 is connected to the output of the consistency determiner 116, WDRD. The output terminal of the NAND gate 230 is the inverter 22.
9 is connected to the input terminal, and its output controls the switches SW1 and SW2 as REGRD. When REGRD is "H", SW1 is closed and SW2 is opened, so that the data register WDIN is output to the output terminal of the multiplexer 218. When REGRD is “L”, SW1 is opened and SW2 is closed, so that D is output to the output terminal of the multiplexer 218.
The output of the Q read amplifier 102 appears.

FIG. 6 is a timing chart showing the operation of the device shown in FIG. The late write operation and the register read operation in this device will be described below with reference to FIG.

In FIG. 6, address A0 and write data D
First write command WT (a) corresponding to 0 to D1
Then, the second write command WT (b) corresponding to the address A1 and the write data D2 to D3 and the read command (RD) corresponding to the address A1 are sequentially input.

In the first write command WT (a) cycle, the address A0 input from the ADD terminal 113 is output from the address register 115 in response to the fall of the write command signal WRT. In this cycle, since the data mask is not applied to the data D0 and D1, both DMINe and DMINo are “L”, and WX
Both FRe and WXFRo transit to “H”. The write data transferred onto WDe and WDo in response to this timing is taken into the data latch, so WDI
D0 and D1 appear in Ne and WDINo. Also, WX
Eve due to FRe and WXFRo becoming "H"
Node bDML in the DM register on both the n side and the Odd side
TC is set to "H".

Next, in the cycle of the second write command WT (b), the address A0 latched in the first write cycle responds to the rising of the write command signal WRT, and the core address for selecting the row or the column. Bus A
It is output as LTC. Then, the outputs WDINe, W of the data register latched in the first write cycle
The DINo is the write driver 101 at the timing of WE controlled by the write timing control circuit 112 ′.
Is written to the memory cell MC through. When the data writing to the memory cell is completed, bDMPR becomes “L”, and DM registers 1 of both Even and Odd
The node bDMLTC of 17 is reset to “L”.

On the other hand, at the fall of WRT, the address A1 input from the ADD terminal is taken into the address register and AREG transits to A1. Of the write data D2 and D3, the data mask is applied to D2, and the DM information taken in is parallel data DMINe and DM by the DM serial / parallel conversion circuit.
It is decomposed into INo. Since D2 is masked here, DMINe is set to "H", and the data latch take-in signal XWFRe on the Even side is prevented from being set to "H". As a result, of the data on WDe and WDo, only D3 on the WDo side is fetched by the data latch, and the data D2 on the Even side is not fetched. On the other hand, when WXFRRo becomes “H”, O
Only bDMLTCo of the DM register on the dd side is set to “H”.

Next, in the cycle of the read command RD, the rising edge of the read command signal RDE is received and A
The address A1 input from the DD terminal 113 is directly transferred to the core address bus ALTC. Then, the consistency determiner 116 and the address ARE latched in the address register in the second write cycle with ALTC.
G is compared. Here, WDRD becomes "H" because both match in A1. In the configuration shown in FIG. 17 showing the conventional technique, the register read operation is performed in the read cycle when WDRD becomes “H”. On the other hand, in the device of the present embodiment, this WDRD is “H”.
The register read operation is performed only when both the condition "and the condition not masked by the second write cycle" are satisfied. The data of the bits that do not match this condition are read from the memory cell as usual.

In the present embodiment, whether or not both of these conditions are met is determined by a signal called REGRD. Odd not masked in the second write cycle
WDRD and bDMLTC are both "H" only on the side
Since the conditions (not masked) are met, REGRD becomes “H” and the register read operation is performed. Specifically, REGRD becomes "H", and the switch SW1 in FIG. 5 is closed, while the switch SW2 is opened. As a result, WDIN latched by the data register is output from the multiplexer 218, and when the read timing control signal RDP becomes "H", this data is transferred to the internal read data bus RDo.

On the other hand, in the DQ buffer section on the Even side, W
DRD is commonly used for Even / Odd, so "H"
However, since bDMLTC is "L" (masked), REGRD remains "L", and data is transferred from the memory cell to RDe through the read amplifier as usual. The data transferred here is the data previously stored in the memory cell at the address corresponding to the address A1 and the Even side, and is represented by Dx here. The data transferred to the read data lines RDe and RDo are converted into serial data by the parallel-serial conversion circuit 111, and then read out from the DQ terminal 107 to the outside of the chip via the data output buffer 110.

According to the above configuration, even in the late write system capable of register read operation, DM
A data mask function according to the method can be realized.
Here, the register read operation is selectively performed only on the data of the bits for which the write mask has not been performed among the data that have not been written to the memory cells by the late write operation. Therefore, data integrity (Cohe
The read operation can be performed while maintaining the (rency).

(Third Embodiment) FIG. 7 shows a third embodiment of the present invention.
3 is a block diagram showing a semiconductor memory device having a VW data mask function according to the embodiment of the present invention. FIG. In this method, the mask information is not input at the same time as the burst write data, but when the write command is issued, that is, in synchronization with this command, the burst length information coded using, for example, an unused address terminal is used. input. Here, in addition to the burst length previously set by the MRS command, a burst length that is valid only during writing can be set. In the present embodiment, Even
The burst length at the time of writing (hereinafter referred to as write burst) is 2 for the burst length = 2 corresponding to / Odd.
A case will be described in which (nothing is masked), 1 (write only one bit on the even side), and 0 (write nothing).

In this embodiment, in contrast to FIG. 1 showing the first embodiment, instead of the DM input buffer 116 and the DM serial / parallel conversion circuit 120, signals WBL0 and WBL1 representing the write burst length are input. A write burst length encoder 121 that performs encoding is provided. Outputs of the write burst length encoder 121, VWENCe and VWENCo, are DMIN in FIG.
e, the same WX as DMINo and corresponding WX
Controls ON / OFF of FRe or WXFRo.

FIGS. 8 (a) and 8 (b) are diagrams showing a concrete circuit configuration and a truth table of the write burst length encoder in the apparatus shown in FIG. 7, respectively. Input signal WBL
The write burst length is determined by the combination of 0 and WBL1. Normally, if no bits are masked, WBL
0 and WBL1 both become “L” and VWENCe, VWE
NCo is also “L”. Therefore, WXFRe, WX
FRo operates normally and both Even / Odd data is written to the data register. When the write burst length 1 is designated, WBL0 becomes "L", WBL1 becomes "H", and only VWENCo becomes "H". Therefore, WXFRo is masked, and as a result, only the data on the Even side is taken into the data register. When write burst length 0 is specified, WBL0 is "H", WBL
1 becomes "L", and both VWENCe and VWENCo become "H". Therefore, WXFR is odd on the Even side as well.
Since neither side operates, no bits are taken into the data register.

With the above structure, the write data mask operation by the VW method can be realized even in the memory which performs the late write operation. In this embodiment,
The same can be applied to the system for performing register read as shown in the second embodiment.

(Fourth Embodiment) FIG. 9 is generated when the clock cycle time (hereinafter referred to as tCK) is shortened in the first and second embodiments shown in FIGS. 5 is a timing chart for explaining a problem to be solved. FIG. 9 shows a state in which the write command WT is input every two clocks. The write data DQ is
This is an operation waveform when the so-called write latency = 1, which starts to be input one clock after the write command.

Internal write data buses WDe, WDo
Is determined from the rising edge and the falling edge of the clock to which the data D0 and D1 are input, respectively. WXFR, which is a capture signal of the data register, is created at a certain timing from the falling edge of the clock to which the data on the Odd side (D1 in this case) is applied.

At this time, WXFR is the next write command W.
The operation must be completed before the write driver drive signal WE generated from T (b) rises. It can be said that the time from the fall of WXFR to the rise of WE is the margin of tCK (clock cycle time). Therefore, in order to increase the tCK margin, it is desirable to set the WXFR timing as early as possible. At this time, the write data WD is WXFR.
If it is confirmed during the period when is "H", the correct data will be finally fetched into the data register.

On the other hand, turning to DM for masking the write data, for example, when the data D1 is masked as shown in FIG. 9, the data mask signal DMINo converted into parallel data is WXFR depending on the circuit configuration.
There is a risk that the mask will not be applied due to a glitch on WXFR later than the rising timing of. From this point of view, the DMINe / DMINo generated by the serial-parallel conversion circuit needs to be determined at least before the WXFR is generated. Therefore, in the above-described first and second embodiments, WXFR cannot be generated from the time when the DM signal is captured until the time when DMIN is generated,
There is a limit to shortening tCK.

FIG. 10 is a block diagram showing a semiconductor memory device having a DM data mask function according to the fourth embodiment of the present invention. The present embodiment aims to improve the problems that occur in the first and second embodiments in reducing tCK.

One of the differences from the device shown in FIG. 1 is a write timing control circuit 112, which has the same circuit configuration as that of the prior art shown in FIG. Therefore, the signal WX for fetching the data into the data register
FR is not even / odd independent and is commonly used by both. In addition, the DM serial-parallel conversion circuit 120
The output DMINe / DMINo of is not transferred to the write timing control circuit 112 but transferred to the DM register 117 'via the internal bus. The structure of the DM register 117 'is the same as that of the device shown in FIG.
Is different from.

FIG. 11 is a circuit diagram showing details of the DM register 117 'of the apparatus shown in FIG. DM register 11
7'is a clocked inverter 231 and an inverter 2
32-235, a clocked NOR gate 236, N
It is composed of an AND gate 237. DMIN is connected to the input terminal of the clocked inverter 231 and its output is connected to the input terminal of the inverter 232 and the clocked NOR.
It is connected to the output terminal of the gate 236. Inverter 2
The output terminal of 32 is connected to the input terminal of the inverter 233 and one input terminal of the clocked NOR gate 236. The output terminal of the inverter 233 is the NAND gate 2
37 is connected to one input terminal of 37 and is a bDMLTC in which a DM signal is latched. The write driver drive signal WE is connected to the other input terminal of the NAND gate 237, and its output is input to the write driver as bWGT and is also connected to the input terminal of the inverter 234. The output terminal of the inverter 235 is connected to the other input terminal of the clocked NOR gate 236. BDMPR is input to the input terminal of the inverter 235, and has a function of clearing the DM information latched at the end of the late write operation.

FIG. 12 is a timing chart showing the operation of the device shown in FIG. The output DMINe / DMINo of the DM serial / parallel conversion circuit 120 is the ON state of the data register fetch signal WXFRe / WXFRo.
Do not directly control / OFF. Instead, DMINe / D
The MINos are input to the Even / Odd DM registers, respectively, and bDMLTCe, b are input by the signal WXFR.
Each is latched in DMLTCo.

Here, the first write command WT (a)
Of the write data D0 to D1 input by
A write mask is performed on D0, and therefore DM
INe becomes "H" in response to the rising edge of the clock.
However, since the signal WXFR is common to Even / Odd, both write data WDe and WDo are taken into the data register. At this time, even if the confirmation of DMINe is delayed with respect to WXFR, bDMLTCe is latched without any problem if it is confirmed during the period when WXFR is "H". Therefore, the second write command WT
When (b) is input, the generation of WGTe is suppressed,
WDINe taken into the data register is not written to the MDQ line pair. Therefore, only the unmasked data D1 on WDINo is written to the memory cell.

According to the above configuration, it is not necessary to determine DMIN in advance even when the fetch signal WXFR of the data register is placed as early as possible. Similar to the write data WD, WXFR need only be settled during the period of “H”, which makes it possible to prevent the write mask from failing, which is effective in shortening tCK.
Further, since the propagation paths of the write data WD and the mask data DMIN are the same, the data input buffer 1
08 and DM input buffer 119 can be designed with the same circuit configuration, and serial-parallel conversion circuit 109 and D
There is also an advantage that the M serial / parallel conversion circuit 120 can be designed with the same circuit configuration.

The present embodiment can also be applied to the late write system corresponding to the register read in the second embodiment and the late write system corresponding to the VW data mask in the third embodiment. Is.

In addition, within the scope of the idea of the present invention, those skilled in the art can come up with various modifications and modifications, and those modifications and modifications are also within the scope of the present invention. Understood.

[0087]

According to the present invention, it is possible to provide a semiconductor memory device which performs a late write operation and which can appropriately mask write data, and a control method thereof.

[Brief description of drawings]

FIG. 1 is a block diagram showing a semiconductor memory device having a DM data mask function according to a first embodiment of the present invention.

2 is a block diagram of a DQ buffer unit of the device shown in FIG.
FIG. 6 is a circuit diagram showing details of a write driver, a data register, and a DM register.

FIG. 3 is a timing chart showing the operation of the apparatus shown in FIG.

FIG. 4 is a block diagram showing a semiconductor memory device having a DM data mask function according to a second embodiment of the present invention.

5 is a circuit diagram showing details of a data register, a DM register, and a part that controls data at the time of reading, in the DQ buffer unit of the device shown in FIG.

6 is a timing chart showing the operation of the device shown in FIG.

FIG. 7 is a block diagram showing a semiconductor memory device having a VW data mask function according to a third embodiment of the present invention.

8A and 8B are diagrams respectively showing a specific circuit configuration and a truth table of a write burst length encoder in the device shown in FIG. 7.

FIG. 9 is a diagram showing the first and second embodiments of the present invention.
Timing chart for explaining the problems that occur when trying to reduce the clock cycle time.

FIG. 10 is a block diagram showing a semiconductor memory device having a DM data mask function according to a fourth embodiment of the present invention.

11 is a circuit diagram showing details of a DM register of the device shown in FIG.

12 is a timing chart showing the operation of the device shown in FIG.

FIG. 13 is a timing chart showing the late write operation of the FCRAM.

FIG. 14 is a block diagram showing a conventional semiconductor memory device that performs a late write operation.

15 is a diagram showing a DQ buffer unit of the device shown in FIG.
FIG. 6 is a circuit diagram showing details of a DQ write driver and a data register.

16 is a timing chart showing the operation of the device shown in FIG.

FIG. 17 is a block diagram showing a conventional semiconductor memory device that performs a late write operation and a register read operation.

FIG. 18 is a circuit diagram showing details of an address register and a consistency determiner of the device shown in FIG.

19 is a circuit diagram showing details of a DQ buffer section of the device shown in FIG.

20 is a timing chart showing a register read operation of the device shown in FIG.

[Explanation of symbols]

100 ... Memory core unit 101 ... DQ write driver 102 (102-1, 102-2) ... DQ read amplifier 103 (103-1, 103-2) ... Data register 104 (104-1, 104-2) ... Column decoder 105 (105-1, 105-2) ... Column switch 106 ... Row decoder 107 ... DQ terminal 108 ... Data input buffer 109 ... Serial / parallel conversion circuit 110 ... Data output buffer 111 ... Parallel / serial conversion circuit 112 ... Write timing control circuit 112 '... Write timing control circuit 113 ... ADD terminal 114 ... Address input buffer 115 ... Address register 116 ... Consistency determiner 117 (107-1, 107-2) ... DM register 117'(107'-1,107'-2) ) ... DM register 118 ... DM terminal 119 ... D M input buffer 120 ... DM serial / parallel conversion circuit 121 ... Write burst length encoder

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Hiroyuki Otake             1st Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa             Ceremony Company Toshiba Microelectronics Sen             Inside (72) Inventor Susumu Ozawa             1st Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa             Ceremony Company Toshiba Microelectronics Sen             Inside F term (reference) 5M024 AA49 BB05 BB17 BB18 BB20                       BB27 BB30 BB35 BB36 DD17                       DD28 DD39 DD83 GG20 HH01                       JJ02 JJ03 JJ50 JJ54 KK28                       PP01 PP02 PP03 PP07 PP10

Claims (20)

[Claims] 1. A data register for latching data to be written in a memory cell, a DQ write driver for driving a data line according to the write data latched in the data register, and a mask for the write data according to a data mask signal. A DM register for latching a control signal indicating whether or not to
In a cycle of the first write command, according to a first data mask signal, a first control signal as to whether or not to mask the first write data is latched in the DM register, and continues. In a cycle of a second write command, the DQ write driver is driven according to the first control signal latched in the DM register to control writing of data to the memory cell. 2. A data register for latching data to be written in a memory cell, a DQ write driver for driving a data line according to the write data latched in the data register, and a mask for the write data according to a data mask signal. A DM register for latching a control signal indicating whether or not to
In a cycle of the first write command, the first write data is latched in the data register according to a first data mask signal, and the first write data is stored in the data register according to the first data mask signal. A first control signal for masking or non-masking is latched in the DM register, and the DQ write driver is driven according to the first control signal latched in the DM register in the subsequent second write command cycle. Then, the semiconductor memory device is characterized in that the first write data latched in the data register is selectively written to the memory cell. 3. A data register for latching data to be written in a memory cell, a DQ write driver for driving a data line according to the write data latched in the data register, and a mask for the write data according to a data mask signal. A DM register for latching a control signal indicating whether or not to
In the cycle of the first write command, the first write data is latched in the data register without depending on the first data mask signal, and the first write data is latched according to the first data mask signal. A first control signal for whether or not to mask write data is latched in the DM register, and the DQ write is performed in accordance with the first control signal latched in the DM register in the next cycle of the second write command. A semiconductor memory device characterized by driving a driver to selectively write the first write data latched in the data register to the memory cell. 4. The DM register is set by the first data mask signal so as to latch the first control signal in the DM register in the cycle of the first write command. The semiconductor memory device according to claim 1. 5. The cycle according to claim 1, wherein the first data mask signal is latched in the DM register as the first control signal in the cycle of the first write command. Semiconductor memory device. 6. A write timing control circuit for driving and controlling the DQ write driver according to a write command, and a switch for selectively connecting the write timing control circuit and the DQ write driver. In the cycle of the write command, the first write data latched in the data register is selected for the memory cell by turning on or off the switch according to the first control signal latched in the DM register. 6. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is programmed. 7. An address register for latching an address corresponding to a memory cell into which data is written, a DQ read amplifier provided corresponding to the DQ write driver, for amplifying read data read onto the data line, According to a consistency determiner that determines whether the address associated with the read command and the address associated with the write command immediately before the match, and the DQ output according to the output of the DM register and the output of the consistency determiner. A switching circuit for switching between the read data amplified by the read amplifier and the data latched in the data register and supplying the read data line, and a first address signal in the cycle of the first write command. Is latched in the address register, and the first and second write commands are In the cycle of the read command performed between the first control and the address associated with the read command, the first control is determined to include the matching address by the consistency determiner and latched in the DM register. When the signal does not mask a portion of the first write data corresponding to the matching address, the switching circuit shuts off the output of the DQ read amplifier and latches the first write data in the data register. 7. The semiconductor memory device according to claim 1, wherein the read data line is supplied with a portion corresponding to the coincident address of. 8. In the cycle of the first write command, when a capture signal for determining the timing of capturing the first write data in the data register is in the first state, the first write data and the The first control signal is taken into the data register and the DM register respectively, and when the take-in signal is in the second state, the input to the data register and the DM register is cut off to make the first write data. 8. The semiconductor memory device according to claim 1, further comprising: latching the first control signal. 9. In the cycle of the second write command, after controlling writing of data to the memory cell according to the latched first control signal,
9. The semiconductor memory device according to claim 1, wherein the DM register is reset. 10. A signal generation circuit for forming the first data mask signal is further provided, wherein the signal generation circuit selects the first burst from among the total burst lengths representing the total bit length of the first write data. 10. The first data mask signal is formed on the basis of a first burst length signal in which a valid burst length is set in bit units in one write command cycle. The semiconductor memory device according to 1. 11. The semiconductor memory device according to claim 10, wherein said DM register is arranged corresponding to each bit of said total burst length. 12. The first burst length signal is the first burst length signal.
12. The semiconductor memory device according to claim 10, wherein the semiconductor memory device is input in synchronization with the write command of. 13. The semiconductor memory device according to claim 1, wherein the first data mask signal is input in synchronization with the first write data. 14. A late write operation in which first write data is latched in a first write command cycle, and the first write data is written to a memory cell in a subsequent second write command cycle. A method of controlling a semiconductor memory device, comprising:
Latching a first control signal for masking the first write data independently of the first write data in accordance with the data mask signal of the second write command, and latching in a cycle of the second write command. A method of controlling a semiconductor memory device, comprising: controlling writing of data to the memory cell according to the first control signal. 15. The method of controlling a semiconductor memory device according to claim 14, wherein in the cycle of the first write command, the first write data is latched according to the first data mask signal. 16. The semiconductor memory device according to claim 14, wherein in the cycle of the first write command, the first write data is latched without following the first data mask signal. Control method. 17. The method according to claim 14, wherein in the cycle of the first write command, the first control signal is generated and latched by the first data mask signal. Method for controlling semiconductor memory device of. 18. The semiconductor memory according to claim 14, wherein in the cycle of the first write command, the first data mask signal is latched as the first control signal. Device control method. 19. In a cycle of the first write command, a first address signal is latched, and in a cycle of a read command performed between the first and second write commands, an address associated with the read command is generated. If the latched first control signal includes an address matching the first address and does not mask a portion of the first write data corresponding to the matching address, the latched first control signal 19. The method of controlling a semiconductor memory device according to claim 13, wherein a portion of write data corresponding to the matching address is read. 20. A first burst length signal in which a valid burst length in a cycle of the first write command among the total burst lengths representing the total bit length of the first write data is set in a bit unit. Based on the first
20. The method of controlling a semiconductor memory device according to claim 13, wherein the data mask signal is formed.