JP2002334890A - High-frequency power amplifier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a structure for achieving high-breakdown voltage characteristics by restraining kinking phenomenon, in a field effect transistor having a short gate length of 0.2 μm or smaller. SOLUTION: In the field effect transistor, a buffer layer 2, a channel layer 3, a Schottky layer 4, and an ohmic contact layer 5 are formed successively on a compound semiconductor substrate 1, an ohmic electrode 7 is formed on the ohmic contact layer 5, and a gate electrode 6 is formed on the Schottky layer; and at least up to the uppermost layer in the channel layer 3 from the uppermost layer in the ohmic contact layer 5 for forming a source electrode is removed by etching, and with the source electrode and a channel being connected electrically. Holes accumulated in the channel layer 3 are discharged by an electrode 8 for discharging the holes, and generation of kinks is inhibited, thus achieving high breakdown voltage characteristics.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LMDS (Local
Multipoint Distribution System) or FWA (Fi
The present invention relates to a technology for improving the withstand voltage of an ultra-high-speed field-effect transistor used in millimeter-wave communication represented by xed Wireless Access).

[0002]

2. Description of the Related Art Recent electronic devices for millimeter waves include 26
There is a demand for a characteristic capable of amplifying, modulating and demodulating a signal having an extremely high frequency of GHz or 60 GHz. Therefore, a field effect transistor using a compound semiconductor having a high carrier mobility is used for a device for millimeter waves, and its gate length is extremely fine, not more than 0.25 μm. For example, an MMIC (Monolithic Microwave Integrated Circuit) for millimeter waves using a pHEMT having a gate length of 0.2 μm.
s) has been reported (1999 IEEE GaAs IC Symposium
Technical Digests), and its maximum oscillation frequency (fmax) has reached 100 GHz. However, in order to miniaturize the gate length, Ids-V which normally shows a saturation characteristic is used.
In the ds characteristic, a phenomenon (kink) in which the drain current sharply rises above a certain drain voltage is observed (FIG. 4).
reference). This is because, around the gate electrode, the speed of electrons traveling through the channel becomes extremely high, and holes generated by impact ionization accumulate, resulting in an equivalently positive gate bias.

A conventional technique for solving the above problem will be described with reference to FIG. 1 is a compound semiconductor substrate, 2 is a buffer layer, 3 is a channel layer, 4 is a Schottky layer, 5 is an ohmic contact layer, 6 is a gate electrode, and 7 is an ohmic electrode. By lowering the impurity concentration of the Schottky layer 4, the electric field intensity near the gate electrode 6 is reduced,
It suppresses ionization collision.

[0004]

However, the prior art is not a fundamental technique for suppressing kink, and its effect is not so great.

According to the present invention, in a field effect transistor having a short gate length using a compound semiconductor, the generation of kink is suppressed by a method considered from its generation principle, and as a result, a short gate length electric field capable of realizing high breakdown voltage characteristics is realized. An object of the present invention is to provide a structure of an effect transistor.

[0006]

In order to solve the above-mentioned conventional problems, a high-frequency power amplifier according to the present invention comprises a channel layer formed on a semiconductor substrate, a Schottky layer formed on the channel layer. An ohmic contact layer formed in a partial region on the Schottky layer; a drain electrode and a source electrode formed on the ohmic contact layer; and the contact layer formed on the Schottky layer. A gate electrode formed in a region other than the region having the hole, a hole penetrating at least the contact layer and the Schottky layer, and a conductive material formed in the hole, wherein the conductive material and the source electrode are And the conductive material and the channel layer are in contact with each other, whereby holes accumulated near the channel layer are formed through the conductive material. It can be released.

[0007]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a sectional structural view of a power amplifier according to a first embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a compound semiconductor substrate, which is a high-speed device substrate such as GaAs or InP. Reference numeral 2 denotes a buffer layer, and reference numeral 3 denotes a channel layer in which carriers travel, which is usually made of InGaAs. Reference numeral 4 denotes a Schottky layer, which is formed of AlGaAs, InGaP, or InAlP.
As or the like is used. Generally, a part of the Schottky layer 4 is doped with impurities for supplying carriers. Reference numeral 5 denotes an ohmic contact layer, which is made of GaAs or InGaAs heavily doped. 6
Is a gate electrode, Ti / Al or Ti / Pt / A
u or WSi is used. Reference numeral 7 denotes an ohmic electrode, and an AuGe-based and InGaAs-based GaAs layer
For the layer, WSi or Ti / Pt / Au is used. Reference numeral 8 denotes a hole discharging electrode, which is a conductor formed inside a hole penetrating at least the ohmic contact layer 5 and the Schottky layer 4, and has a function of discharging holes accumulated in the channel layer 3. For this reason, channel accumulation of holes is suppressed, and the occurrence of kink can be reduced. As a result, a high withstand voltage characteristic can be realized even with a short gate length.

(Embodiment 2) FIG. 2 is a sectional structural view of a power amplifier according to Embodiment 2 of the present invention. In FIG. 2, reference numeral 1 denotes a compound semiconductor substrate, which is a high-speed device substrate such as GaAs or InP. Reference numeral 2 denotes a buffer layer, and reference numeral 3 denotes a channel layer in which carriers travel, which is usually made of InGaAs. Reference numeral 4 denotes a Schottky layer, which is formed of AlGaAs, InGaP, or InAlP.
As or the like is used. Generally, a part of the Schottky layer 4 is doped with impurities for supplying carriers. Reference numeral 5 denotes an ohmic contact layer, which is made of GaAs or InGaAs heavily doped. 6
Is a gate electrode and is Ti / Al or Ti / Pt / A
u or WSi is used. Numeral 7 denotes an ohmic electrode, which is AuGe-based and InGaAs for the GaAs layer.
For the layer, WSi or Ti / Pt / Au is used. 9 is a hole discharging electrode formed on the back surface,
A conductive material formed at least inside a hole penetrating the compound semiconductor substrate 1 and having a function of discharging holes accumulated in the channel layer 3. It is desirable that the hole discharging electrode 9 penetrates the buffer layer 2. Reference numeral 10 denotes a back electrode, which is electrically connected to the hole discharging electrode 9.
For this reason, channel accumulation of holes is suppressed, and the occurrence of kink can be reduced. As a result, a high withstand voltage characteristic can be realized even with a short gate length.

(Embodiment 3) FIG. 3A is a sectional structural view of a power amplifier according to Embodiment 3 of the present invention.
FIG. 3B shows a plan view of the power amplifier. FIG.
In (a), reference numeral 1 denotes a compound semiconductor substrate, which is GaAs.
Alternatively, it is a substrate for a high-speed device such as InP. Reference numeral 2 denotes a buffer layer, and reference numeral 3 denotes a channel layer in which carriers travel, which is usually made of InGaAs. Reference numeral 4 denotes a Schottky layer, which is composed of AlGaAs, InGaP, or IGaAs.
nAlAs or the like is used. Generally, a part of the Schottky layer 4 is doped with impurities for supplying carriers. Reference numeral 5 denotes an ohmic contact layer, which is made of GaAs or InGaAs heavily doped. 6 is a gate electrode which is Ti / Al or Ti / P
t / Au or WSi is used. Reference numeral 7 denotes an ohmic electrode, and an AuGe-based and InG
For the aAs layer, WSi or Ti / Pt / Au is used. Reference numeral 9 denotes a hole discharging electrode formed on the back surface, and has a function of discharging holes accumulated in the channel layer 3. Reference numeral 10 denotes a back electrode, which is electrically connected to the hole discharging electrode 9. For this reason, channel accumulation of holes is suppressed, and the occurrence of kink can be reduced. As a result, a high withstand voltage characteristic can be realized even with a short gate length.
Further, since a plurality of hole discharging electrodes 9 are formed for one ohmic electrode, a parasitic capacitance component between the gate electrode and the source electrode is suppressed, and deterioration of high frequency characteristics can be suppressed. .

[0011]

As described above, according to the present invention, even when the gate length is designed to be 0.2 μm or less, an advantageous effect that kink can be suppressed, that is, a high withstand voltage characteristic can be realized.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a power amplifier according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of a power amplifier according to a second embodiment of the present invention.

3A is a sectional view of a power amplifier according to a third embodiment of the present invention. FIG. 3B is a plan view of the power amplifier.

FIG. 4 is a diagram showing current characteristics of a conventional power amplifier.

FIG. 5 is a cross-sectional view of a conventional power amplifier.

[Explanation of symbols]

 Reference Signs List 1 compound semiconductor substrate 2 buffer layer 3 channel layer 4 Schottky layer 5 ohmic contact layer 6 gate electrode 7 ohmic electrode 8, 9 hole discharging electrode 10 back electrode

Continued on the front page F term (reference) 4M104 AA04 AA05 BB10 BB14 BB15 BB28 FF01 FF02 FF13 GG12 5F102 FA01 GB01 GB02 GC01 GD01 GJ05 GJ06 GL05 GM04 GM06 GQ01 GS02 GT03 GT05 GV00

Claims (7)

[Claims] A channel layer formed on a semiconductor substrate; a Schottky layer formed on the channel layer;
An ohmic contact layer formed in a partial region on the Schottky layer; a drain electrode and a source electrode formed on the ohmic contact layer; and the ohmic contact layer formed on the Schottky layer. A gate electrode formed in a region other than the region, a hole penetrating at least the ohmic contact layer and the Schottky layer, and a conductive material formed in the hole, the conductive material and the source electrode And the conductive material is in contact with the channel layer. 2. A buffer layer is formed between the semiconductor substrate and the Schottky layer, wherein the hole penetrates the channel layer, and the conductive material and the buffer layer are in contact with each other. 2. The semiconductor device according to claim 1, wherein 3. The semiconductor device according to claim 2, wherein said hole penetrates through said buffer layer, and said conductor and said semiconductor substrate are in contact with each other. 4. The semiconductor device according to claim 1, wherein a plurality of said holes are formed. 5. A channel layer formed on a first main surface of a semiconductor substrate, a Schottky layer formed on the channel layer, and an ohmic contact formed in a partial region on the Schottky layer A layer, a drain electrode and a source electrode formed on the ohmic contact layer,
A gate electrode formed on a region other than the region where the ohmic contact layer is formed on the Schottky layer; and a metal formed on a second main surface of the semiconductor substrate opposite to the first main surface. A layer, at least a hole penetrating the semiconductor substrate, and a conductive material formed in the hole, wherein the conductive material and the channel layer are in contact, and the conductive material and the metal layer are in contact with each other. A semiconductor device. 6. The semiconductor device according to claim 5, wherein a buffer layer is formed between said semiconductor substrate and said Schottky layer, and said hole penetrates through said buffer layer. 7. The semiconductor device according to claim 5, wherein a plurality of said holes are formed.