JP2002314406A - Clock recovery circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a clock recovery circuit that reduces jitter in a recovered clock even when a received data signal includes man noises. SOLUTION: The clock recovery circuit comprises a clock component extraction section 1, a band-pass filter 2, a phase comparator 3, a low-pass filter 4, a voltage controlled oscillator(VCO) 5, and a 1/N frequency divider 6. The band-pass filter reduces the noise component included in a reference clock extracted from a received data signal by the clock component extraction section, the phase comparator compares the reference clock whose noise component is reduced with an output of the VCO to control the VCO via the low-pass filter thereby reducing the jitter of the clock signal in the VCO output caused by the noise component included in the extracted reference clock. Thus, the clock recovery circuit can recover the clock signal with less jitter that follows the frequency of the received data signal and phase fluctuations.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention extracts a clock component from a received data signal, compares the reference clock with the output of a voltage-controlled oscillator by a phase comparator, and passes a low-pass filter through a low-pass filter so that the two match. The present invention relates to a clock recovery circuit for recovering a clock signal by a PLL circuit that controls the voltage of a voltage controlled oscillator based on the output of a phase comparator.

[0002]

2. Description of the Related Art As a conventional clock recovery circuit, for example, a circuit described in Japanese Patent Application Laid-Open No. 08-149414 is known.

FIG. 11 is a block diagram showing a configuration of a conventional PLL circuit. The PLL circuit shown has a clock component extraction unit 1, a phase comparator 3, a low-pass filter (LP
F) A voltage controlled oscillator (VCO) 5 and a 1 / N divider 6 are provided. The clock component extraction unit 1 extracts the reference clock extracted from the received data signal and the output of the voltage controlled oscillator 5 by one.
The output divided by the / N frequency divider 6 is compared with the output of the phase comparator 3, and the voltage-controlled oscillator 5 is controlled by the output of the phase comparator 3 via the low-pass filter 4 so that the two match. The voltage-controlled oscillator 5 outputs a signal in which the frequency and phase of the reference clock are synchronized, and reproduces the clock signal. However, the parts that are not involved in the present invention are omitted.

[0004]

However, in the configuration of the conventional clock recovery circuit, when the received data signal contains noise, that is, when the extracted reference clock contains a noise component, the noise amount is particularly low. Is large, there is a problem that a phase fluctuation (jitter) occurs in the clock signal output from the voltage controlled oscillator 5 due to noise. Further, when the received data signal has frequency and phase fluctuations, if the bandwidth of the low-pass filter 4 in the PLL loop is reduced in order to reduce the jitter, the frequency and phase fluctuations of the received data signal will be reduced. Has a problem that the follow-up performance is deteriorated.

An object of the present invention is to solve the above-mentioned problems, and an object of the present invention is to provide a clock recovery circuit capable of reducing a noise component included in a reference clock of a PLL loop input.

[0006]

In order to achieve the above object, a clock recovery circuit according to the present invention extracts a reference clock from a received data signal, and compares the reference clock with the output of a voltage controlled oscillator by a phase comparator. A clock recovery circuit configured to reproduce a clock signal by a PLL circuit that controls the voltage of the voltage-controlled oscillator based on an output of the phase comparator through a low-pass filter so that the two coincide with each other. It is provided with a band-pass filter at the preceding stage. With this configuration, it is possible to reduce noise components included in the reference clock input to the PLL loop.

The band-pass filter is a variable-bandwidth band-pass filter, the low-pass filter is a variable-bandwidth low-pass filter, and includes a control unit for controlling these bandwidths. Has a configuration for controlling the bandwidths of the bandwidth variable band-pass filter and the bandwidth variable low-pass filter in accordance with the amount of noise included in the reference clock. With this configuration, it is possible to reduce noise components included in the reference clock input to the PLL loop.

A clock recovery circuit according to another invention extracts a reference clock from a received data signal, compares the reference clock with the output of a voltage controlled oscillator by a phase comparator,
In a clock recovery circuit in which a clock signal is recovered by a PLL circuit that controls the voltage of the voltage controlled oscillator by an output of a phase comparator through a low-pass filter so that the two match, the voltage controlled oscillator has a voltage −
A plurality of voltage-controlled oscillators having different frequency sensitivities, a selection control unit for selecting an output of these voltage-controlled oscillators, wherein the selection control unit includes a plurality of voltage-controlled oscillators according to a noise amount included in a reference clock. Select the output of
It has a configuration for changing the PLL loop gain. With this configuration, the PLL loop gain can be controlled by switching between various voltage-controlled oscillators having different voltage-frequency sensitivities.

[0009] Further, a configuration is provided in which a band-pass filter is provided in a stage preceding the phase comparator. With this configuration, the noise component included in the reference clock input to the PLL loop can be reduced by the band-pass filter, and the PLL loop gain can be controlled by switching between various voltage-controlled oscillators having different voltage-frequency sensitivities. it can.

The band-pass filter is a variable-bandwidth band-pass filter, the low-pass filter is a variable-bandwidth low-pass filter, and the selection control unit is configured to control a noise in accordance with a noise amount included in a reference clock. The variable bandwidth band-pass filter and the variable bandwidth low-pass filter. With this configuration,
The noise component included in the reference clock input to the PLL loop can be reduced, and the frequency and phase fluctuation band of the received data signal that can be followed can be expanded while maintaining the jitter generated due to the noise at an allowable constant value. it can.

A clock recovery circuit according to still another invention extracts a reference clock from a received data signal, compares the reference clock with the output of a voltage controlled oscillator by a phase comparator, and compares the reference clock with the output of the voltage controlled oscillator so that the two match. In a clock recovery circuit configured to recover a clock signal by a PLL circuit that controls the voltage of the voltage controlled oscillator by an output of the phase comparator via a band-pass filter, a variable gain amplifier is provided at a subsequent stage of the phase comparator. And a control unit for controlling the gain of the variable gain amplifier, wherein the control unit controls the gain of the variable gain amplifier in accordance with the amount of noise included in the reference clock to change the PLL loop gain. . With this configuration, the PLL loop gain can be controlled by changing the amplification of the variable gain amplifier.

[0012] Further, a configuration is provided in which a band-pass filter is provided before the phase comparator. With this configuration, P
Noise components included in the reference clock input to the LL loop can be reduced.

Further, the band-pass filter is a variable-bandwidth band-pass filter, the low-pass filter is a variable-bandwidth low-pass filter, and further includes a control unit for controlling these bandwidths. Has a configuration for controlling the bandwidths of the bandwidth variable band-pass filter and the bandwidth variable low-pass filter in accordance with the amount of noise included in the reference clock. With this configuration, the noise component included in the reference clock input to the PLL loop can be reduced, and the frequency and phase of the received data signal that can be followed while maintaining the jitter generated due to the noise at an allowable constant value can be maintained. The fluctuation band can be expanded.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. It is to be noted that the same reference numerals are used for the portions that exhibit the same or common functions as the above-described conventional ones, and the description thereof is omitted.

(First Embodiment) FIG. 1 is a block diagram showing a configuration of a clock recovery circuit according to a first embodiment of the present invention. The difference between the clock recovery circuit according to the first embodiment shown in FIG. 1 and the conventional example shown in FIG. 11 is that the band is provided between the clock component extraction unit 1 and the phase comparator 3 before the phase comparator 3. It has a pass filter 2.

Next, the operation will be described. The noise component of the reference clock including noise extracted by the clock component extraction unit 1 from the received data signal including noise is removed by the band-pass filter 2.

FIG. 2 shows the characteristics of the band-pass filter 2. The characteristics of the filter are such that the frequency component of the received data signal to be followed, the phase fluctuation, in other words, the frequency of the reference clock, the bandwidth enough to capture the phase fluctuation, while removing noise components of higher frequencies than that It has steep frequency characteristics.

The frequency of the reference clock to be followed by the band-pass filter 2, and the reference clock from which high-frequency noise components exceeding the phase variation have been removed are converted into a VC by the phase comparator 3.
The phase with the signal from O5 is compared, and a voltage proportional to the difference signal is output from the phase comparator 3. This voltage passes through the low-pass filter 4 and is applied to the VCO 5 to become a drive voltage.

As described above, by removing the noise component included in the reference clock input to the PLL loop by the steep band-pass filter 2, high-frequency noise that cannot be sufficiently removed only by the low-pass filter 4 in the PLL loop is used. The component can be removed, and the jitter of the clock signal of the VCO output generated due to the noise component included in the reference clock can be reduced.

As described above, according to the first embodiment,
By the band-pass filter 2 at the previous stage of the phase comparator 3, PL
The output from the voltage-controlled oscillator 5 is removed by removing the frequency component and phase variation of the received data signal to be followed, which is included in the reference signal of the L-loop input, that is, the noise components in unnecessary bands equal to or higher than the frequency and phase variation of the reference clock. Therefore, even when the reference clock extracted from the received data signal contains much noise, a clock recovery circuit with less generated jitter can be realized.

(Embodiment 2) FIG. 3 is a block diagram showing a configuration of a clock recovery circuit according to Embodiment 2 of the present invention. In the second embodiment, the band-pass filter 2 of the first embodiment is configured by a variable-bandwidth band-pass filter 7, and the low-pass filter 4 is configured by a variable-bandwidth low-pass filter 9, and further controls these. The control unit 8 is provided.

Next, the operation will be described. The noise-containing reference clock extracted by the clock component extraction unit 1 from the received data signal containing noise is subjected to noise removal by the bandwidth variable bandpass filter 7.

FIG. 4 shows the characteristics of the variable bandwidth bandpass filter. The pass band of the filter is controlled by the noise power density included in the received data signal, that is, the noise power density included in the reference clock.

That is, when the noise power density included in the reference clock is small, the jitter of the VCO output clock signal generated due to the noise component included in the reference clock is not large, so that the pass band width is increased. The frequency and phase fluctuation band of the reference clock that can be followed, that is, the frequency and phase fluctuation band of the received data signal are expanded.

On the other hand, when the noise power density included in the reference clock is large, the jitter of the clock signal of the VCO output generated due to the noise component included in the reference clock increases, so that the pass bandwidth is reduced. The jitter of the clock signal of the VCO output caused by the noise component included in the reference clock is reduced.

The phase of the reference clock from which the noise component has been removed by the variable bandwidth band-pass filter 7 is compared with the signal from the VCO 5 by the phase comparator 3, and a voltage proportional to the difference signal is output from the phase comparator 3. You. This voltage passes through the bandwidth variable low-pass filter 9 and further removes noise components.

Here, the pass band of the variable bandwidth low-pass filter 9 is the same as that of the variable bandwidth band-pass filter 7,
If the noise power density contained in the reference clock is small,
V generated due to noise components included in the reference clock
Since the jitter of the clock signal of the CO output is not large, the pass bandwidth is increased, and the frequency of the reference clock that can be followed, the phase fluctuation band, that is, the frequency of the received data signal,
Expand the phase fluctuation band.

On the other hand, when the noise power density included in the reference clock is large, the jitter of the clock signal of the VCO output generated due to the noise component included in the reference clock increases, so that the pass bandwidth is reduced. The jitter of the clock signal of the VCO output caused by the noise component included in the reference clock is reduced. The voltage from which this noise component has been removed is applied to the VCO 5 and becomes the drive voltage.

As described above, the noise component included in the reference clock input to the PLL loop is removed by the band-pass filter, so that the high-frequency noise component that cannot be sufficiently removed only by the low-pass filter in the PLL loop is removed. Therefore, the jitter of the clock signal of the VCO output generated due to the noise component included in the reference clock can be reduced. Also, by controlling the pass band of the variable bandwidth band-pass filter 7 or the variable bandwidth low-pass filter 9 in accordance with the noise power density included in the reference clock, the jitter generated due to noise is controlled. Can be maintained at a permissible constant value, and the frequency and phase fluctuation band of the received data signal that can be followed can be expanded.

As described above, according to the second embodiment,
By the band-pass filter at the preceding stage of the phase comparator 3, the PLL
Output from the voltage controlled oscillator 5 by removing the frequency component and phase variation of the received data signal to be followed, which is included in the reference clock of the loop input, in other words, by removing noise components in unnecessary bands exceeding the frequency and phase variation of the reference clock. The jitter of the clock signal can be reduced, and a clock recovery circuit with less generated jitter can be realized even when the reference clock extracted from the received data signal contains much noise.

Further, by controlling the pass band of the band-pass filter or the low-pass filter in accordance with the noise power density included in the reference clock, it is possible to reduce the jitter generated due to the noise and follow the received data. With the frequency and phase fluctuation band of the signal expanded, the jitter generated due to noise is kept at a certain allowable level,
According to the present invention, it is possible to realize a clock recovery circuit capable of maximizing the frequency and phase fluctuation band of a reception data signal that can be followed according to the amount of noise included in the reception data signal.

(Embodiment 3) FIG. 5 is a block diagram showing a configuration of a clock recovery circuit according to Embodiment 3 of the present invention. The third embodiment has a configuration including a plurality of VCOs 11, 12, and 13 and a selection unit 10 for selecting their outputs.

Next, the operation will be described. The reference clock including the noise extracted by the clock component extraction unit 1 from the received data signal including the noise is supplied to the phase comparator 3.
Is compared in phase with the signal from the VCO, and a voltage proportional to the difference signal is output from the phase comparator 3. This voltage passes through the low-pass filter 4 to remove noise components. The voltage from which this noise component has been removed is applied to the VCO and becomes the drive voltage.

Here, as shown in FIG. 5, a plurality of VCOs are provided, and the gain of the PLL loop can be changed by making the voltage-frequency sensitivity of each VCO different. When increasing the loop gain, the output of the VCO having a high voltage-frequency sensitivity is selected by the selection section, and when decreasing the loop gain, the output of the VCO having a low voltage-frequency sensitivity is selected by the selection section.

Next, a method of changing the loop gain, that is, a method of selecting which VCO output will be described. The loop gain changes the ability to follow the frequency and phase variations of the received data signal, and it is necessary to increase the loop gain in order to improve the ability to follow. On the other hand, when the loop gain is increased, the jitter of the clock signal of the VCO output generated due to the noise component included in the reference clock increases.

Therefore, when the noise power density included in the reference clock is small, the jitter of the clock signal of the VCO output generated due to the noise component included in the reference clock is not large, so that the VCO having high voltage-frequency sensitivity By selecting the output of and increasing the loop gain,
The ability to follow the frequency and phase fluctuations of the reference clock can be increased.

On the other hand, when the noise power density included in the reference clock is large, the jitter of the clock signal of the VCO output generated due to the noise component included in the reference clock increases, so that the VCO with low voltage-frequency sensitivity is used. Of the VCO generated by the noise component included in the reference clock by selecting the output of
The jitter of the output clock signal can be reduced.

That is, the control unit 8 gives a command to the selection unit 10 to select the outputs of the plurality of voltage controlled oscillators according to the amount of noise included in the reference clock, and the selection unit 10 has different voltage-frequency sensitivities. By selecting the output of the VCO and controlling the PLL loop gain, while reducing the jitter generated due to the noise included in the reference clock, the frequency and phase fluctuation of the reference clock, in other words, the frequency of the received data signal, The ability to follow the phase fluctuation can be increased. Note that the control unit 8 and the selection unit 10 can be integrated to form a selection control unit.

As described above, according to the third embodiment,
Select the output of VCO with different voltage-frequency sensitivity,
By controlling the L loop gain, while reducing the jitter generated due to the noise included in the reference clock,
The ability to follow the frequency and phase fluctuations of the reference clock can be increased, and the amount of noise contained in the reference clock, in other words, the received data signal, is kept in a state where the jitter generated due to noise is kept at a certain allowable level. , It is possible to realize a clock recovery circuit that can maximize the frequency and phase fluctuation band of the received data signal that can be followed according to the amount of noise included in the clock recovery circuit.

(Embodiment 4) FIG. 6 is a block diagram showing a configuration of a clock recovery circuit according to Embodiment 4 of the present invention. Embodiment 3 is a configuration in which the configuration of Embodiment 1 and the configuration of Embodiment 3 are combined.

Next, the operation will be described. The noise component of the reference clock including noise extracted by the clock component extraction unit 1 from the received data signal including noise is removed by the band-pass filter 2.

FIG. 2 shows the characteristics of the band-pass filter 2. The characteristics of the filter are such that the frequency component of the received data signal to be followed, the phase fluctuation, in other words, the frequency of the reference clock, the bandwidth enough to capture the phase fluctuation, while removing noise components of higher frequencies than that It has steep frequency characteristics. The frequency of the received data signal to be followed by the band-pass filter 2 and the reference clock from which high-frequency noise components equal to or more than phase fluctuation have been removed are compared in phase with the signal from the VCO by the phase comparator 3 and are proportional to the difference signal. Is output from the phase comparator 3.

This voltage passes through the low-pass filter 4 to remove noise components. The voltage from which this noise component has been removed is applied to the VCO and becomes the drive voltage.

Here, as shown in FIG. 6, a plurality of VCOs are provided, and the gain of the PLL loop can be changed by making the voltage-frequency sensitivity of each VCO different. When increasing the loop gain, the output of the VCO having a high voltage-frequency sensitivity is selected by the selection section 10, and when decreasing the loop gain, the output of the VCO having a low voltage-frequency sensitivity is selected by the selection section 10.

Next, a method of changing the loop gain, that is, a method of selecting which VCO output will be described. The loop gain changes the ability to follow the frequency and phase variations of the received data signal, and it is necessary to increase the loop gain in order to improve the ability to follow. On the other hand, when the loop gain is increased, the jitter of the clock signal of the VCO output generated due to the noise component included in the reference clock increases.

Therefore, when the noise power density included in the reference clock is small, the jitter of the clock signal of the VCO output generated due to the noise component included in the reference clock is not large, so that the VCO having a large voltage-frequency sensitivity is used. By selecting the output of and increasing the loop gain,
The ability to follow the frequency and phase fluctuations of the reference clock can be increased.

On the other hand, when the noise power density included in the reference clock is large, the jitter of the clock signal of the VCO output generated due to the noise component included in the reference clock increases, so that the VCO with low voltage-frequency sensitivity Of the VCO generated by the noise component included in the reference clock by selecting the output of
The jitter of the output clock signal can be reduced.

As described above, by removing the noise component included in the reference clock of the PLL loop input by the band-pass filter 2, the high-frequency noise component that cannot be sufficiently removed only by the low-pass filter 4 in the PLL loop is removed. Thus, the jitter of the VCO output clock signal generated due to the noise component included in the reference clock can be reduced.

Further, by selecting the outputs of VCOs having different voltage-frequency sensitivities and controlling the PLL loop gain, the jitter generated due to the noise included in the reference clock can be reduced, and the frequency and frequency of the reference clock can be reduced. Phase variation,
In other words, the ability to follow the frequency and phase fluctuations of the received data signal can be increased.

As described above, according to the fourth embodiment,
By the band-pass filter 2 at the previous stage of the phase comparator 3, PL
The output from the voltage-controlled oscillator is obtained by removing a frequency component and a phase variation of the received data signal to be tracked included in the reference clock of the L loop input, that is, a noise component in an unnecessary band equal to or higher than the frequency and the phase variation of the reference clock. The jitter of the clock signal can be reduced, and a clock recovery circuit with less jitter can be realized even when the reference clock contains much noise.

Further, by selecting the outputs of VCOs having different voltage-frequency sensitivities and controlling the PLL loop gain, controlling the PLL loop gain reduces jitter generated due to noise included in the reference clock. The amount of noise included in the reference clock can be reduced while maintaining the jitter generated due to noise at a certain allowable level while reducing the frequency and phase fluctuation of the reference clock. For example, according to the amount of noise included in the received data signal, the frequency of the received data signal that can be tracked,
A clock recovery circuit capable of maximizing the phase fluctuation band can be realized.

(Fifth Embodiment) FIG. 5 is a block diagram showing a configuration of a clock recovery circuit according to a fifth embodiment of the present invention. The fifth embodiment is a combination of the second embodiment and the third embodiment.

Next, the operation will be described. The noise-containing reference clock extracted by the clock component extraction unit 1 from the received data signal containing noise is subjected to noise removal by the bandwidth variable bandpass filter 7.

FIG. 4 shows the characteristics of the variable bandwidth band-pass filter. The pass band of the filter is controlled by the noise power density included in the received data signal, that is, the noise power density included in the reference clock. That is, when the noise power density included in the reference clock is small, the jitter of the VCO output clock signal generated due to the noise component included in the reference clock is not large, so that the pass band width can be increased and The frequency and phase fluctuation band of the clock, that is, the frequency and phase fluctuation band of the received data signal are expanded.

On the other hand, when the noise power density included in the reference clock is large, the jitter of the VCO output clock signal generated due to the noise component included in the reference clock increases, so that the pass bandwidth is reduced. The jitter of the clock signal of the VCO output caused by the noise component included in the reference clock is reduced.

The reference clock from which the noise component has been removed by the bandwidth variable band-pass filter 7 is compared in phase with the signal from the VCO by the phase comparator 3, and a voltage proportional to the difference signal is output from the phase comparator 3. Is done. This voltage passes through the variable bandwidth low-pass filter 9 to remove noise components.

Here, the pass band of the variable bandwidth low-pass filter 9 is the same as that of the variable bandwidth band-pass filter 7,
If the noise power density contained in the reference clock is small,
V generated due to noise components included in the reference clock
Since the jitter of the clock signal output from the CO is not large, the pass band width is increased, and the frequency and phase fluctuation band of the received data signal that can be followed is expanded.

On the other hand, when the noise power density included in the reference clock is large, the jitter of the VCO output clock signal generated due to the noise component included in the reference clock increases, so that the pass band width is reduced. The jitter of the clock signal of the VCO output caused by the noise component included in the reference clock is reduced. The voltage from which this noise component has been removed is applied to the VCO and becomes the drive voltage.

Here, as shown in FIG. 7, a plurality of VCOs are provided, and the gain of the PLL loop can be changed by making the voltage-frequency sensitivity of each VCO different. When increasing the loop gain, the output of the VCO having a high voltage-frequency sensitivity is selected by the selection section, and when decreasing the loop gain, the output of the VCO having a low voltage-frequency sensitivity is selected by the selection section.

Next, a method of changing the loop gain, that is, a method of selecting which VCO output will be described. The loop gain changes the ability to follow the frequency and phase variations of the received data signal, and it is necessary to increase the loop gain in order to improve the ability to follow. On the other hand, when the loop gain is increased, the jitter of the clock signal of the VCO output generated due to the noise component included in the reference clock increases.

Therefore, when the noise power density included in the reference clock is small, the jitter of the clock signal of the VCO output generated due to the noise component included in the reference clock is not large, so that the VCO having a large voltage-frequency sensitivity is used. By selecting the output of and increasing the loop gain,
The ability to follow the frequency and phase fluctuations of the reference clock can be increased. On the other hand, when the noise power density included in the reference clock is large, the jitter of the clock signal of the VCO output generated due to the noise component included in the reference clock increases, so that the output of the VCO with low voltage-frequency sensitivity is reduced. By selecting and lowering the loop gain,
V generated due to noise components included in the reference clock
The jitter of the clock signal of the CO output can be reduced.

As described above, the noise component included in the reference clock input to the PLL loop is removed by the variable bandwidth band-pass filter 7, so that the variable bandwidth low-pass filter 9 in the PLL loop alone cannot sufficiently remove the noise component. High-frequency noise components can be removed, and jitter of the VCO output clock signal generated due to noise components included in the reference clock can be reduced.

Further, by controlling the pass bands of the bandwidth variable band-pass filter 7 and the bandwidth variable low-pass filter 9 in accordance with the noise power density included in the reference clock,
The frequency and phase fluctuation band of the received data signal that can be followed can be expanded while reducing the jitter generated due to noise.

Further, VCOs having different voltage-frequency sensitivities
By controlling the PLL loop gain by selecting the output of (1), it is possible to reduce the jitter caused by the noise included in the reference clock and increase the followability to the frequency and phase fluctuation of the received data signal. it can.

As described above, according to the fifth embodiment, the frequency of the follow-up reception data signal contained in the reference clock of the PLL loop input is controlled by the bandwidth variable band-pass filter 7 at the preceding stage of the phase comparator 3. By removing noise components in unnecessary bands exceeding the phase fluctuation, the voltage-controlled oscillator 1
It is possible to reduce the jitter of the clock signals output from 1, 12, and 13, and to realize a PLL circuit with less jitter even when the reference clock contains much noise.

Further, by controlling the pass bands of the variable bandwidth band-pass filter 7 and the variable bandwidth low-pass filter 9 in accordance with the noise power density included in the reference clock,
The frequency and phase fluctuation band of the received data signal that can be followed can be expanded while reducing the jitter generated due to noise.

Further, VCOs having different voltage-frequency sensitivities
By controlling the PLL loop gain by selecting the output of the reference clock, the jitter generated due to the noise included in the reference clock can be reduced, and the ability to follow the frequency and phase fluctuation of the reference clock can be increased. With the jitter generated due to noise kept at a certain allowable level, the amount of noise included in the reference clock, in other words, according to the amount of noise included in the received data signal, the frequency of the received data signal that can be tracked, A clock recovery circuit capable of maximizing the phase fluctuation band can be realized.

(Embodiment 6) FIG. 8 is a block diagram showing a configuration of a clock recovery circuit according to Embodiment 6 of the present invention. The sixth embodiment has a configuration in which a variable gain amplifier 14 is added to the subsequent stage of the phase comparator 2.

Next, the operation will be described. The reference clock signal including noise extracted by the clock component extraction unit 1 from the received data signal including noise is compared in phase with the signal from the VCO by the phase comparator 3, and a voltage proportional to the difference signal is obtained. Output from the phase comparator 3. This voltage is amplified by the variable gain amplifier 14.

Here, a method of varying the gain of the variable gain amplifier 14 will be described. The loop gain changes the responsiveness to the frequency and phase fluctuations of the reference clock, and it is necessary to increase the gel loop gain to improve the responsiveness. On the other hand, when the loop gain is increased, the jitter of the clock signal of the VCO output generated due to the noise component included in the reference clock increases.

Therefore, when the noise power density included in the reference clock is small, the jitter of the clock signal of the VCO output generated due to the noise component included in the reference clock is not large. By increasing the loop gain and the loop gain, it is possible to increase the ability to follow the frequency and phase fluctuations of the reference clock.

On the other hand, when the noise power density included in the reference clock is large, the jitter of the clock signal of the VCO output generated due to the noise component included in the reference clock increases. By lowering the loop gain, the jitter of the VCO output clock signal generated due to the noise component included in the reference clock can be reduced.

The voltage proportional to the difference signal that has passed through the variable gain amplifier 14 passes through the low-pass filter 4 to remove noise components. The voltage from which this noise component has been removed is V
The driving voltage is given to CO.

As described above, the variable gain amplifier 14
By controlling the L loop gain, while reducing the jitter generated due to the noise included in the reference clock,
The ability to follow the frequency and phase fluctuations of the reference clock, in other words, the frequency and phase fluctuations of the received data signal can be increased.

As described above, according to the sixth embodiment,
By controlling the PLL loop gain by the variable gain amplifier 14, it is possible to increase the followability to the frequency and phase fluctuations of the reference clock while reducing the jitter generated due to the noise included in the reference clock. With the jitter generated due to noise kept at a certain allowable level, the frequency and phase of the received data signal that can be tracked according to the amount of noise contained in the reference clock, in other words, the amount of noise contained in the received data signal A clock recovery circuit capable of maximizing the fluctuation band can be realized.

(Embodiment 7) FIG. 9 is a block diagram showing a configuration of a clock recovery circuit according to Embodiment 7 of the present invention. Embodiment 6 is a configuration in which the configuration of Embodiment 1 and the configuration of Embodiment 6 are combined.

Next, the operation will be described. The noise component of the reference clock signal containing noise extracted by the clock component extraction unit 1 from the received data signal containing noise is removed by the band-pass filter 2.

FIG. 2 shows the characteristics of the band-pass filter 2. The characteristics of the filter are such that the frequency component of the received data signal to be followed, the phase fluctuation, in other words, the frequency of the reference clock, the bandwidth enough to capture the phase fluctuation, while removing noise components of higher frequencies than that It has steep frequency characteristics.

The reference clock from which the high-frequency noise component exceeding the frequency and phase variation of the received data signal to be followed by the band-pass filter 2 is removed is supplied to the phase comparator 3 by V
The phase is compared with the signal from the CO, and a voltage proportional to the difference signal is output from the phase comparator 3. This voltage is amplified by the variable gain amplifier 14.

Here, a method of varying the gain of the variable gain amplifier 14 will be described. The loop gain changes the responsiveness to the frequency and phase fluctuations of the reference clock, and it is necessary to increase the gel loop gain to improve the responsiveness. On the other hand, when the loop gain is increased, the jitter of the clock signal of the VCO output generated due to the noise component included in the reference clock increases.

Accordingly, when the noise power density included in the reference clock is small, the jitter of the VCO output clock signal generated due to the noise component included in the reference clock is not large, so that the gain of the variable gain amplifier 14 is reduced. By increasing the loop gain and the loop gain, it is possible to increase the ability to follow the frequency and phase fluctuations of the reference clock.

On the other hand, when the noise power density included in the reference clock is large, the jitter of the VCO output clock signal generated due to the noise component included in the reference clock increases. By lowering the loop gain, the jitter of the VCO output clock signal generated due to the noise component included in the reference clock can be reduced.

The voltage proportional to the difference signal that has passed through the variable gain amplifier 14 passes through the low-pass filter 4 to remove noise components. The voltage from which this noise component has been removed is V
The driving voltage is given to CO.

As described above, the noise component contained in the reference clock input to the PLL loop is removed by the band-pass filter 2, thereby removing the high-frequency noise component that cannot be sufficiently removed only by the low-pass filter in the PLL loop. Therefore, the jitter of the clock signal of the VCO output generated due to the noise component included in the reference clock can be reduced.

Further, by controlling the PLL loop gain by the variable gain amplifier 14, the jitter generated due to the noise included in the reference clock can be reduced, and the frequency and phase fluctuation of the reference clock, in other words, the received data signal can be reduced. Can follow up the frequency and phase fluctuations.

As described above, according to the seventh embodiment,
By the band-pass filter 2 at the previous stage of the phase comparator 3, PL
The output from the voltage-controlled oscillator is obtained by removing a frequency component and a phase variation of the received data signal to be tracked included in the reference clock of the L loop input, that is, a noise component in an unnecessary band equal to or higher than the frequency and the phase variation of the reference clock. The jitter of the clock signal can be reduced, and a clock recovery circuit with less jitter can be realized even when the reference clock contains much noise.

Further, by controlling the PLL loop gain by the variable gain amplifier 14, jitter generated due to noise included in the reference clock is reduced, and the ability to follow the frequency and phase fluctuations of the reference clock is increased. The amount of noise contained in the reference clock, while maintaining the jitter generated due to noise at a certain allowable level,
In other words, it is possible to realize a clock recovery circuit that can maximize the frequency and phase fluctuation band of the received data signal that can be followed in accordance with the amount of noise included in the received data signal.

(Eighth Embodiment) FIG. 10 is a block diagram showing a configuration of a clock recovery circuit according to an eighth embodiment of the present invention. Embodiment 8 is a configuration in which the configuration of Embodiment 2 and the configuration of Embodiment 6 are combined.

Next, the operation will be described. The noise component of the reference clock signal including the noise extracted by the clock component extraction unit 1 from the received data signal including the noise is removed by the bandwidth variable bandpass filter 7.

Here, as shown in FIG. 4, the pass band of the bandwidth variable filter 7 is controlled by the noise power density included in the received data signal, that is, the noise power density included in the reference clock. That is, when the noise power density included in the reference clock is small, the jitter of the VCO output clock signal generated due to the noise component included in the reference clock is not large, so that the pass band width can be increased and The frequency and phase fluctuation band of the clock, that is, the frequency and phase fluctuation band of the received data signal are expanded.

On the other hand, when the noise power density included in the reference clock is large, the jitter of the VCO output clock signal generated due to the noise component included in the reference clock increases, so that the pass bandwidth is reduced. The jitter of the clock signal of the VCO output caused by the noise component included in the reference clock is reduced.

The reference clock from which the noise component has been removed by the variable bandwidth band-pass filter 7 is compared in phase with the signal from the VCO by the phase comparator 3, and a voltage proportional to the difference signal is output from the phase comparator 3. Is done. This voltage is amplified by the variable gain amplifier 14.

Here, a method of varying the gain of the variable gain amplifier 14 will be described. The loop gain changes the responsiveness to the frequency and phase fluctuations of the reference clock, and it is necessary to increase the gel loop gain to improve the responsiveness. On the other hand, when the loop gain is increased, the jitter of the clock signal of the VCO output generated due to the noise component included in the reference clock increases.

Therefore, when the noise power density included in the reference clock is small, the jitter of the VCO output clock signal generated due to the noise component included in the reference clock is not large. By increasing the loop gain and the loop gain, it is possible to increase the ability to follow the frequency and phase fluctuations of the reference clock.

On the other hand, when the noise power density included in the reference clock is large, the jitter of the VCO output clock signal generated due to the noise component included in the reference clock increases. By lowering the loop gain, the jitter of the VCO output clock signal generated due to the noise component included in the reference clock can be reduced.

The voltage proportional to the difference signal that has passed through the variable gain amplifier 14 passes through the variable bandwidth low-pass filter 9 to remove noise components. Here, the pass band of the bandwidth variable low-pass filter 9 is caused by the noise component included in the reference clock when the noise power density included in the reference clock is low, similarly to the bandwidth variable band-pass filter 7. Since the jitter of the clock signal output from the VCO is not large, the pass band width is increased, and the frequency and phase fluctuation band of the reference clock that can be followed, that is, the frequency and phase fluctuation band of the received data signal are expanded.

On the other hand, when the noise power density included in the reference clock is large, the jitter of the clock signal of the VCO output generated due to the noise component included in the reference clock increases, so that the pass bandwidth is reduced. The jitter of the clock signal of the VCO output caused by the noise component included in the reference clock is reduced. The voltage from which this noise component has been removed is applied to the VCO and becomes the drive voltage.

As described above, the noise component included in the reference clock input to the PLL loop is removed by the variable bandwidth band-pass filter 7, so that it cannot be sufficiently removed only by the variable bandwidth low-pass filter 9 in the PLL loop. High-frequency noise components can be removed, and jitter of the VCO output clock signal generated due to noise components included in the reference clock can be reduced.

Also, by controlling the passbands of the variable bandwidth bandpass filter 7 and the variable bandwidth lowpass filter 9 according to the noise power density included in the reference clock,
The frequency and phase fluctuation band of the reference clock that can be followed, that is, the frequency and phase fluctuation band of the received data signal, can be expanded while reducing the jitter generated due to noise.

Further, by controlling the PLL loop gain by the variable gain amplifier 14, the jitter generated due to the noise included in the reference clock can be reduced, and the frequency and phase fluctuation of the reference clock, in other words, the received data signal can be reduced. Can follow up the frequency and phase fluctuations.

As described above, according to the eighth embodiment,
The frequency variable and band-pass filter 7 at the preceding stage of the phase comparator 3 controls the frequency and phase fluctuation of the reception data signal to be followed, which is included in the reference clock of the PLL loop input, in other words, the unnecessary frequency band exceeding the frequency and phase fluctuation of the reference clock. By removing the noise component, the jitter of the clock signal output from the voltage controlled oscillator 5 can be reduced,
Even when the reference clock contains much noise, a clock recovery circuit with less jitter can be realized.

Further, by controlling the passbands of the variable bandwidth bandpass filter 7 and the variable bandwidth lowpass filter 9 according to the noise power density included in the reference clock,
The frequency and phase fluctuation band of the reference clock that can be followed, that is, the frequency and phase fluctuation band of the received data signal, can be expanded while reducing the jitter generated due to noise.

Further, by controlling the PLL loop gain by the variable gain amplifier 14, the jitter generated due to the noise included in the reference clock is reduced, and the followability to the frequency and phase fluctuation of the reference clock is increased. The received data can be tracked in accordance with the amount of noise included in the reference clock, in other words, the amount of noise included in the received data signal, while maintaining the jitter generated due to noise at a certain allowable level. A clock recovery circuit capable of maximizing the frequency and phase fluctuation band of a signal can be realized.

[0104]

As described above, the clock recovery circuit of the present invention extracts the reference clock from the received data signal, compares the reference clock with the output of the voltage controlled oscillator by the phase comparator, and the two match. In a clock recovery circuit that reproduces a clock signal by a PLL circuit that controls the voltage of the voltage-controlled oscillator based on the output of the phase comparator through a low-pass filter, By providing a filter, P
The noise component included in the reference clock input to the LL loop can be reduced, and the generated jitter can be reduced.

A clock recovery circuit according to another invention extracts a reference clock from a received data signal, compares the reference clock with the output of a voltage controlled oscillator by a phase comparator,
In a clock recovery circuit in which a clock signal is recovered by a PLL circuit that controls the voltage of the voltage controlled oscillator by an output of a phase comparator through a low-pass filter so that the two match, the voltage controlled oscillator has a voltage −
A frequency control oscillator having a plurality of voltage-controlled oscillators having different frequency sensitivities, comprising a selection control unit for selecting an output of the voltage-controlled oscillator, wherein the selection control unit controls the plurality of voltage-controlled oscillators in accordance with an amount of noise included in a reference clock. , And switching between various voltage-controlled oscillators having different voltage-frequency sensitivities, the PLL loop gain can be controlled, and the generated jitter can be reduced.

A clock recovery circuit according to still another aspect of the present invention extracts a reference clock from a received data signal, compares the reference clock with the output of a voltage controlled oscillator by a phase comparator, and compares the reference clock with the output of the voltage controlled oscillator so that the two match. In a clock recovery circuit configured to recover a clock signal by a PLL circuit that controls the voltage of the voltage controlled oscillator by an output of the phase comparator via a band-pass filter, a variable gain amplifier is provided at a subsequent stage of the phase comparator. A control unit that controls the gain of the variable gain amplifier, and the control unit controls the PLL loop gain by changing the amplification degree of the variable gain amplifier according to the amount of noise included in the reference clock. And the generated jitter can be reduced.

Further, by providing a variable bandwidth band-pass filter as a band-pass filter at the preceding stage of the phase comparator and a variable bandwidth low-pass filter as a low-pass filter, jitter generated due to noise is reduced. Can be maintained at a permissible constant value, and the frequency and phase fluctuation band of the received data signal that can be followed can be expanded.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a clock recovery circuit according to a first embodiment of the present invention;

FIG. 2 is a diagram illustrating an example of characteristics of a band-pass filter used in the present invention.

FIG. 3 is a diagram showing a configuration of a clock recovery circuit according to a second embodiment of the present invention;

FIG. 4 is a diagram showing an example of characteristics of a bandwidth variable bandpass filter used in the present invention, and a method of reducing noise using the filter.

FIG. 5 is a diagram showing a configuration of a clock recovery circuit according to a third embodiment of the present invention;

FIG. 6 is a diagram showing a configuration of a clock recovery circuit according to a fourth embodiment of the present invention;

FIG. 7 is a diagram showing a configuration of a clock recovery circuit according to a fifth embodiment of the present invention;

FIG. 8 is a diagram showing a configuration of a clock recovery circuit according to a sixth embodiment of the present invention;

FIG. 9 is a diagram showing a configuration of a clock recovery circuit according to a fifth embodiment of the present invention;

FIG. 10 is a diagram showing a configuration of a clock recovery circuit according to a sixth embodiment of the present invention;

FIG. 11 is a diagram showing a configuration of a conventional clock recovery circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Clock component extraction part 2 Band pass filter (BPF) 3 Phase comparator 4 Low pass filter (LPF) 5, 11, 12, 13 Voltage controlled oscillator (VCO) 6 1 / N divider 7 Bandwidth variable band pass Filter 8 control unit 9 variable bandwidth low-pass filter 10 selection unit 14 variable gain amplifier

Claims (8)

[Claims] 1. A reference clock is extracted from a received data signal, and this reference clock is compared with an output of a voltage controlled oscillator by a phase comparator. A clock recovery circuit for recovering a clock signal by a PLL circuit that controls a voltage of the voltage controlled oscillator by an output, comprising a band-pass filter at a stage preceding the phase comparator. 2. The apparatus according to claim 1, wherein said band-pass filter is a variable-bandwidth band-pass filter, said low-pass filter is a variable-bandwidth low-pass filter, and further comprises a control unit for controlling these bandwidths. 2. The clock recovery circuit according to claim 1, wherein the controller controls the bandwidths of the variable bandwidth band-pass filter and the variable bandwidth low-pass filter according to an amount of noise included in a reference clock. 3. A reference clock is extracted from a received data signal, and the reference clock is compared with an output of a voltage controlled oscillator by a phase comparator. In a clock recovery circuit configured to reproduce a clock signal by a PLL circuit that controls a voltage of the voltage controlled oscillator by an output, the voltage controlled oscillator is constituted by a plurality of voltage controlled oscillators having different voltage-frequency sensitivities. A selection control unit that selects an output of the controlled oscillator, wherein the selection control unit selects outputs of the plurality of voltage controlled oscillators according to an amount of noise included in the reference clock and changes a PLL loop gain. Clock recovery circuit. 4. The clock recovery circuit according to claim 3, wherein a band-pass filter is provided before the phase comparator. 5. The band-pass filter is a variable-bandwidth band-pass filter, the low-pass filter is a variable-bandwidth low-pass filter, and the selection control unit is responsive to a noise amount included in a reference clock. 5. The clock recovery circuit according to claim 4, wherein the bandwidth of the variable bandwidth bandpass filter and the variable bandwidth lowpass filter is controlled. 6. A reference clock is extracted from a received data signal, and the reference clock is compared with an output of a voltage controlled oscillator by a phase comparator. In a clock recovery circuit for recovering a clock signal by a PLL circuit that controls the voltage of the voltage controlled oscillator by an output, a variable gain amplifier is provided at a subsequent stage of the phase comparator, and a gain of the variable gain amplifier is controlled. A clock recovery circuit comprising a control unit, wherein the control unit controls a gain of a variable gain amplifier according to an amount of noise included in a reference clock to change a PLL loop gain. 7. The clock recovery circuit according to claim 6, wherein a band-pass filter is provided in a stage preceding the phase comparator. 8. The band-pass filter is a variable-bandwidth band-pass filter, the low-pass filter is a variable-bandwidth low-pass filter, and includes a control unit for controlling these bandwidths. 8. The clock recovery circuit according to claim 7, wherein the controller controls the bandwidths of the bandwidth variable band-pass filter and the bandwidth variable low-pass filter according to a noise amount included in a reference clock.