JP2002289749A - Wiring board for mounting semiconductor device and semiconductor device mounting package using the same - Google Patents

Wiring board for mounting semiconductor device and semiconductor device mounting package using the same

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Publication number
JP2002289749A
JP2002289749A JP2001093719A JP2001093719A JP2002289749A JP 2002289749 A JP2002289749 A JP 2002289749A JP 2001093719 A JP2001093719 A JP 2001093719A JP 2001093719 A JP2001093719 A JP 2001093719A JP 2002289749 A JP2002289749 A JP 2002289749A
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Japan
Prior art keywords
portion
wiring board
part
semiconductor device
post
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
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JP2001093719A
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Japanese (ja)
Inventor
Yoji Mine
Susumu Okikawa
Koji Sato
Hiroshi Takashima
Kentaro Yano
光司 佐藤
洋二 峯
進 沖川
健太郎 矢野
洋 高島
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Hitachi Metals Ltd
日立金属株式会社
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Priority to JP2001093719A priority Critical patent/JP2002289749A/en
Publication of JP2002289749A publication Critical patent/JP2002289749A/en
Application status is Abandoned legal-status Critical

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Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Abstract

PROBLEM TO BE SOLVED: To inexpensively provide a semiconductor device mounting package capable of coping with high density by using a laminated foil sandwiching a conductor intermediate layer being an etching barrier in intermediation to form a wiring board. SOLUTION: In a wiring board for mounting a semiconductor device having a lead part leading a signal from the semiconductor device, a land part provided on a part of the lead part, a post part formed to penetrate an insulation layer from the land part, and a terminal part on the edge of the post part, a conductor layer different in etching characteristic from one of both or any one of the lead part and the land part, and the post part is formed between the land part and the post part.

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【発明の属する技術分野】本発明は半導体素子搭載用配線板及びそれを用いた半導体素子搭載パッケージに関するものである。 The present invention relates to relates to a semiconductor element mounting package using the wiring board and its semiconductor element mounting.

【0002】 [0002]

【従来の技術】近年携帯電話、ノート型パソコンなどといった携帯情報機器の急速な普及に伴い、機器の軽量・ In recent years mobile phone, such as a notebook computer with the rapid spread of portable information devices, lightweight equipment
小型化ならびに高性能化は急激な進展を遂げており、これを構成する電子部品に対しても高密度化が要求されている。 Compact and high performance has undergone a rapid development, high density is required even for electronic components constituting it. これに対応して半導体素子を搭載する配線板では、配線の微細パターン化、狭ピッチ化が推進されている。 In the wiring board for mounting a semiconductor device in response to this, the fine patterning of the wiring, narrow pitch has been promoted.

【0003】従来の半導体素子搭載用配線板においては、例えば図5に模式的に示すように、両面銅張樹脂を用いて、絶縁層(3)を貫通する穴をあけた後、穴の内部をめっきし、層間の導通を得て、所望の配線パターンを形成する方法が使用されている。 [0003] In the conventional semiconductor element mounting wiring board, as shown schematically in FIG. 5, for example, using a double-sided copper-clad resin, after a hole passing through the insulating layer (3), within the bore plated, to obtain continuity between the layers, a method of forming a desired wiring pattern is used. この技術ではドリルまたはレーザを用いて所謂スルーホール(17)を形成し、スルーホールめっきを行う。 This technique forms a so-called through-hole (17) using a drill or laser, performing through-hole plating. また、図6ならびに図7に模式的に示すように、穴あけ及びめっきの形態が異なる方法で製造された半導体素子搭載用配線板もある。 Further, as schematically shown in FIG. 6 and FIG. 7, there is also drilling and plating element mounting wiring board form is manufactured by different methods. ここに使用される技術は、レーザにより所謂IVH(18)(Interst Technique used herein, the laser by a so-called IVH (18) (Interst
itial Via Hole)を形成し、露出した穴表面をめっきするか、あるいは穴をめっきで完全に埋めてしまうものである。 itial Via Hole) is formed, or plating the exposed hole surfaces, or those which would completely fill the hole with the plating.

【0004】 [0004]

【発明が解決しようとする課題】しかしながら、スルーホールを有する半導体素子搭載用配線板においては、高密度化に対応するにはレーザ穴あけが必須となり、穴数の増加に伴いレーザ穴あけのコストが増大すること、スルーホール直下に端子部を配置できず、引き回し配線が必要であること、レーザ穴あけし、めっきした後にリード部や端子部(引き回し配線も含む)をエッチングで形成するため、配線厚さが増加し、配線の微細化が困難であることなど、高密度化に関して多くの問題がある。 However [0005] In the semiconductor element mounting wiring board having a through-hole, the laser drilling is required to correspond to the higher density, the cost of laser drilling is increased with increasing number of holes to it, can not place the terminal portion directly below the through-hole, it is necessary lead wiring, since the laser drilling to form the lead portion and the terminal portion after plating (lead wiring including) by etching, the wiring thickness there was an increase, such that the miniaturization of the wiring is difficult, there are a number of problems with respect to densification.

【0005】また、IVHを有する半導体素子搭載用配線板においては、IVH直下に端子部を形成できるが、レーザスルーホールめっきと同様に、レーザを使用するためコストがかかることやめっきにより配線厚さが増加するため、微細配線が得られ難いという問題がある。 [0005] In the semiconductor element mounting wiring board having IVH, may form a terminal portion directly below IVH, similarly to the laser through-hole plating, the wiring by costly it or plating for using laser thickness order but increasing, there is a problem that is difficult to obtain fine line. 本発明の目的は、中間にエッチングバリアとなる導体中間層を挟んだ積層箔を用いて、配線板を形成することで、高密度化に対応できる半導体素子搭載パッケージをより安価に提供することである。 An object of the present invention, a stacked foil sandwiching the conductive intermediate layer which serves as an intermediate in the etching barrier, by forming the wiring board, to provide a semiconductor element mounting package that can correspond to high density at lower cost is there.

【0006】 [0006]

【課題を解決するための手段】本発明者らは、中間にエッチングバリアとなる導体層を挟んだ積層箔を用いて製造したポスト付きリード材を使用することで、レーザ工程及びめっき工程が不要となり、配線板の配線高密度化ならびにコスト削減が実現できることを知見し、本発明に到達した。 The present inventors have SUMMARY OF THE INVENTION, by the use of post-leaded material manufactured by using the laminated foil sandwiching a conductive layer serving as the intermediate etch barrier, unnecessary laser process and the plating process is next, and it found that the wiring density as well as cost reduction of the wiring board can be achieved, thereby achieving the present invention.

【0007】すなわち本発明は、半導体素子から信号を導くリード部と、該リード部の一部に設けたランド部と、該ランド部から絶縁層を貫通して形成されたポスト部と、該ポスト部の先端に端子部を有する半導体素子搭載用配線板において、ランド部とポスト部の間に、リード部及びランド部とポスト部の両方または何れか一方とはエッチング特性が異なる導体層が形成されている半導体素子搭載用配線板である。 That is, the present invention provides a lead portion for guiding a signal from the semiconductor element, and the land portion provided on a portion of the lead portion, and a post portion which is formed through the insulating layer from the land portion, said post in the semiconductor element mounting wiring board having a terminal part on the tip parts, between the land portion and the post portion, the etching characteristics are different conductive layer forming the both or either of the lead portion and the land portion and the post portion and it has a semiconductor element mounting wiring board. 好ましくは、半導体素子搭載用配線板の厚さが0.2mm以下である半導体素子搭載用配線板である。 Preferably, the thickness of the semiconductor element mounting wiring board is a semiconductor element mounting wiring board is 0.2mm or less. また、更に好ましくは、リード部及びランド部とポスト部がCuまたはCu合金からなり、且つ導体層がAgまたはAg合金からなる半導体素子搭載用配線板であり、上述の導体層は乾式成膜された乾式成膜層である半導体素子搭載用配線板である。 Further, more preferably, the lead portion and the land portion and the post portion is made of Cu or Cu alloy, a and element mounting wiring board conductor layer is made of Ag or an Ag alloy, the conductor layers described above are dry-deposited and a semiconductor element mounting wiring board a dry deposition layer. また、本発明は上述の半導体素子搭載用配線板を用いてなる半導体素子搭載パッケージである。 Further, the present invention is a semiconductor element mounting package obtained by using the above-described semiconductor device mounting wiring board.

【0008】 [0008]

【発明の実施の形態】以下に詳しく本発明について説明する。 DETAILED DESCRIPTION OF THE INVENTION be described in detail the present invention below. 本発明は、中間にエッチングバリアとなる導体層を挟んだ積層箔を用いてポスト付きのリード材を形成し、これを用いることによって、既存の設備や技術で安価に配線板の配線高密度化が実現できることに特長がある。 The present invention forms a lead material with post a stacked foil sandwiching a conductive layer serving as the intermediate etch barrier, by using this, the wiring density of the low cost wiring board in the existing equipment and technology there is a feature that but can be realized. 具体的には、本発明の重要な特長は図1、図2に示すように、半導体素子から信号を導くリード部(1)の一部に設けたランド部(2)と、ランド部から絶縁層(3)を貫通して形成されたポスト部(4)との間に、リード部及びランド部とポスト部の両方または何れか一方とはエッチング特性が異なる導体層(6)が形成されていることにある。 Specifically, an important feature of the present invention 1, as shown in FIG. 2, the land portion formed in a portion of the lead portion (1) for guiding the signal from the semiconductor element (2), isolated from the land portion during the post portion formed through the layer (3) and (4), the lead portions and the land portions and the both post portions, or either the conductor layer is etching characteristic different from (6) is formed It lies in the fact you are.

【0009】この半導体素子搭載用配線板の製造方法としては、例えば、図3に示すように、先ず、(a)リード材(7)/中間材(8)/ポスト材(9)の構造を有する三層積層箔(10)を準備し、(b)選択エッチングにより、片面にポスト部(4)を形成、更に(c)中間材を選択エッチングする。 [0009] As a method for producing the semiconductor element mounting wiring board, for example, as shown in FIG. 3, first, the structure of (a) the lead material (7) / the intermediate member (8) / post member (9) prepare three layer laminate foil (10) having, by (b) selective etching, forming a post portion (4) on one side, selective etching further (c) an intermediate member. 次に(d)ポスト部及び導体層(6)を絶縁層(3)に埋める。 Then (d) is the post portion and the conductor layer (6) filled in the insulating layer (3). ここで端子部(5)は露出している必要があるため、 Here, since the terminal portion (5) needs exposed,
場合によっては平面研削等を行う。 When performing surface grinding or the like by. そして、次に(e)リード部(1)及びランド部(2)を選択エッチングにより形成すれば良い。 And then (e) the lead portion (1) and the land portions (2) may be formed by selective etching.

【0010】この技術を用いれば、穴数増加によりコストが増大するレーザ穴あけの代わりに選択エッチングにより一括してポスト部の形成が可能となり、価格的にも有利であり、しかも高密度化に対応できる。 [0010] With this technique, collectively by selective etching in place of the laser drilling cost is increased by increasing the number of holes allows the formation of the post portion is advantageous in price, the addition corresponds to the density it can. また、ランド部の直下に端子部を形成することができ、電気特性的に優れており、無駄な引き回し配線も不必要である。 Further, it is possible to form the terminal portion immediately below the land portion, and electrical properties to better, useless lead wiring is also unnecessary. 更にめっき工程がなく、リード部の配線厚さを小さくできるため、配線の微細化に対応可能である。 No further plating process, it is possible to reduce the wiring thickness of the lead portion, it is possible to cope with miniaturization of the wiring.

【0011】ここで、リード部及びランド部とポスト部の形成においては選択エッチングを用いるため、厚さは薄いほうが好ましく、配線板の厚さは0.2mm以下が望ましい。 [0011] Here, since the use of selective etching in the formation of the lead portion and the land portion and the post portion, the thinner is preferable thickness, the thickness of the circuit board below is preferable 0.2 mm. また、ポスト部及びリード部及びランド部はそれぞれ150μm、50μm以下が良い。 Further, each of the post portion and the lead portion and the land portion 150 [mu] m, or less good 50 [mu] m. 更に好ましくはそれぞれ115μm、35μm以下である。 More preferably each 115 .mu.m, is 35μm or less. 一方、導体層の厚さはエッチングバリアとして機能する程度の厚さが必要で、且つ選択エッチングで迅速に除去できるようにできるかぎり薄いほうが良い。 On the other hand, the thickness of the conductive layer requires a thickness sufficient to function as an etch barrier and thinner is better as possible to allow rapid removal by selective etching. 導体層の厚さは材質により異なるが、0.05μm〜5μmが好ましく、より好ましくは0.1μm The thickness of the conductive layer varies depending on the material, 0.05 [mu] m to, more preferably 0.1μm
〜1μmの範囲である。 It is in the range of ~1μm.

【0012】次にリード部及びランド部とポスト部となる材料は配線材であるため、金属または合金が好ましく、Cu、Al、Au、Ag等の金属または合金の他、Fe‐Ni系合金などから選ぶと良い。 [0012] Then for material for the lead portion and the land portion and the post portion is a wiring material, a metal or alloy is preferred, Cu, Al, Au, other metals or alloys such as Ag, Fe-Ni based alloy such as You may choose from. ここで合金とはその金属を主成分とするものを指す。 Here, the alloy refer to those based on the metal. リード部及びランド部とポスト部は同一の材料でも、異種材料であっても構わない。 Lead portion and the land portion and the post portion is also of the same material, it may be a different material. 電気抵抗や入手のし易さを考慮すると、CuまたはCu合金が好適であり、特にCuが望ましい。 In view of the electric resistance and easy availability, Cu or Cu alloy are preferable, especially Cu is preferable.

【0013】導体層としては、上記リード部及びランド部とポスト部に対して選択エッチングが可能である必要があるため、両方または何れか一方の材料に対してエッチングバリア性を有する導体である必要がある。 [0013] As the conductive layer, it is necessary it is possible to selectively etched with respect to the lead portion and the land portion and the post portion, it must be a conductor having an etch barrier to both or either of the material there is. 従って、導体層は金属が好適であり、Ti、Ni、Al、Sn、Ag、 Therefore, the conductive layer is a metal are preferred, Ti, Ni, Al, Sn, Ag,
Au、Ptの金属または合金が好ましい。 Au, Pt metals or alloys are preferred. また、導体層は配線としても機能するため、電気抵抗が低いものが好ましく、Ag、Au、Alなどが特に望ましい。 Further, since the conductive layer which also functions as a wiring, is preferably a low electrical resistance, Ag, Au, Al, etc. are particularly preferable. 更に好ましくは電気抵抗が最も低いAgが導体層として好適であり、Ag合金でも同様の効果が得ることが可能である。 More preferably is suitable lowest Ag electric resistance as a conductor layer, it is possible to obtain the same effect in Ag alloy. 従って、最も好ましいリード部及びランド部/導体層/ポスト部の材料の組合せとしてはCuまたはCu合金/AgまたはAg合金/CuまたはCu合金である。 Accordingly, the most preferred lead portion and the land portion / conductor layer / a combination of the post portion of the material Cu or Cu alloy / Ag or an Ag alloy / Cu or Cu alloy.

【0014】上述した導体層の形成は乾式成膜法を用いると良い。 [0014] Formation of the conductive layer described above is preferably used for the dry film formation method. なお、乾式成膜法は、物理蒸着や化学蒸着法など、気相やプラズマを利用した乾式の成膜方法全般のことであり、この中には真空蒸着法は勿論、イオンプレーティングのように真空で加熱し蒸発させたものをイオン化、加速して成膜する方法や、スパッタのように気体イオンをぶつけて所望の原子をたたき出し成膜する方法や、特殊なるつぼを用い、ある特定の材料を分子線状に引き出して蒸発させる分子線蒸着法も含まれるし(以上、物理蒸着法)、化学蒸着法のようにある種の気体を加熱反応させる成膜法も含まれる。 Incidentally, the dry film forming method, such as physical vapor deposition or chemical vapor deposition is that the deposition process in general dry using vapor or plasma, vacuum deposition method in this course, as ion plating ionizing the one obtained by heating in a vacuum evaporation, accelerated to a method for forming, and a method of forming Tatakidashi the desired atomic bumping gas ions as sputtering, using a special crucible, certain materials the it also includes molecular linear molecular beam evaporation method in which evaporation is pulled out (or, physical vapor deposition), deposition method for heating the reaction of certain gaseous also included as chemical vapor deposition.

【0015】中でも、近年の成膜技術の高速化が著しい、真空蒸着法、スパッタリング法、イオンプレーティング法などの物理蒸着法が好適である。 [0015] Among them, significant speed of recent deposition techniques, vacuum deposition, sputtering, is suitable physical vapor deposition method such as an ion plating method. 真空蒸着法は蒸着速度が速く、生産性が良い。 Vacuum deposition method has a high deposition rate, good productivity. スパッタリング法は、導体層となる金属が高融点金属の場合も対応可能であり、 Sputtering method, even if the metal comprising the conductive layer is of a refractory metal are adaptable,
導体層となる金属の選択範囲が広く、何れの方法を用いて形成される乾式成膜層でも均一で均質な成膜が可能である。 Wide selection of metal serving as the conductor layer, it is possible to uniform and homogeneous deposited in a dry film formation layer formed by using any method. 更に、この乾式成膜法は真空槽内で行うため、乾式成膜層(導体層)に活性な金属を用いても、表面酸化の恐れも少ないため、リード部及びランド部とポスト部との電気伝導度性も確保される。 In addition, the dry deposition method is for performing in a vacuum chamber, even with the active metal in dry film forming layer (conductor layer), since less risk of surface oxidation, the lead portion and the land portion and the post portion electric conductivity property is ensured.

【0016】本発明の半導体素子搭載用配線板は例えば図4に示す如く、はんだレジスト(11)塗布し、半導体素子(12)を搭載し、リード部(1)にAuワイヤ(13)でワイヤーボンディングし、モールド樹脂(15)で埋めこんで、端子部(5)には接続用のはんだボール(14)を配して使用すれば良い。 The element mounting wiring board of the present invention as shown in FIG. 4, for example, a solder resist (11) was applied, by mounting a semiconductor element (12), a wire of Au wire (13) to the lead section (1) bonding, elaborate filled with mold resin (15), the terminal portion (5) may be used by arranging a solder ball for connection (14). また、配線板のリード部及びランド部とポスト部、並びに導体層を形成する際に、半導体素子の下部に導体が残るようにしておけば、ヒートシンク(16)として使用でき、好ましい。 The lead portion and the land portion and the post portion of the wiring board, and when forming the conductive layer, if as the conductor remains in the lower portion of the semiconductor element, can be used as a heat sink (16), preferably. そして、半導体素子の搭載はリード部にパッド部を形成し、フリップチップ実装を行っても良い。 The mounting of the semiconductor device forms a pad portion to the lead unit may perform flip-chip mounting. 更に端子部の接続ははんだペーストを塗布しても良い。 Further connection terminal portions may be coated with solder paste. なお、リード部の接続部や端子部に関しては必要に応じてAuめっきなどの処理を行うと良い。 Incidentally, it may perform processing such as Au plating as necessary with respect to the connection portion and the terminal portion of the lead portion.

【0017】以上、説明する本発明の配線板の構造をとることで、高密度化に対応できる半導体素子搭載パッケージをより安価に提供することができる。 [0017] above, by taking a structure of a wiring board of the present invention to be described, it is possible to provide a semiconductor element mounting package that can correspond to high density at lower cost.

【0018】 [0018]

【発明の効果】本発明によれば、中間にエッチングバリアとなる導体中間層を挟んだ積層箔を用いて、配線板を形成することで、高密度化に対応できる半導体素子搭載パッケージをより安価に提供することが可能となる。 According to the present invention, a stacked foil sandwiching the conductive intermediate layer which serves as an intermediate in the etching barrier, by forming a wiring board, more expensive semiconductor element mounting package that can correspond to high density it is possible to provide in.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】本発明の半導体素子搭載用配線板の一例を示す断面模式図である。 1 is a schematic sectional view showing an example of a semiconductor element mounting wiring board of the present invention.

【図2】本発明の半導体素子搭載用配線板の一例を示す平面模式図である。 2 is a schematic plan view showing an example of a semiconductor element mounting wiring board of the present invention.

【図3】本発明の半導体素子搭載用配線板の製造工程の一例を示す概略図である。 Figure 3 is a schematic diagram showing an example of a semiconductor element mounting wiring board manufacturing process of the present invention.

【図4】本発明の半導体素子搭載パッケージの一例を示す断面模式図である。 It is a cross-sectional view schematically showing an example of a semiconductor element mounting package of the present invention; FIG.

【図5】従来の半導体素子を搭載した配線板の一例を示す断面模式図である。 5 is a schematic sectional view showing an example of a wiring board equipped with the conventional semiconductor device.

【図6】従来の半導体素子を搭載した配線板の一例を示す断面模式図である。 6 is a schematic sectional view showing an example of a wiring board equipped with the conventional semiconductor device.

【図7】従来の半導体素子を搭載した配線板の一例を示す断面模式図である。 7 is a schematic sectional view showing an example of a wiring board equipped with the conventional semiconductor device.

【符号の説明】 DESCRIPTION OF SYMBOLS

1. 1. リード部、2. Lead part, 2. ランド部、3. The land portion, 3. 絶縁層、4. Insulating layer, 4. ポスト部、5. Post portion, 5. 端子部、6. The terminal portions, 6. 導体層、7. Conductor layer, 7. リード材、8. Lead material, 8. 中間材、9. Intermediate material, 9. ポスト材、10. Post material, 10. 三層積層箔、11. Three-layer laminated foil, 11. はんだレジスト、12. Solder resist, 12. 半導体素子、13. Semiconductor element, 13. Auワイヤ、14. Au wire, 14. はんだボール、15. Solder balls, 15. モールド樹脂、16. Molding resin 16. ヒートシンク、17. Heat sink, 17. スルーホール、18. Through-hole, 18. IVH IVH

───────────────────────────────────────────────────── フロントページの続き (72)発明者 佐藤 光司 島根県安来市安来町2107番地2 日立金属 株式会社冶金研究所内 (72)発明者 沖川 進 東京都港区芝浦一丁目2番1号 日立金属 株式会社内 ────────────────────────────────────────────────── ─── of the front page continued (72) inventor Koji Sato Shimane Prefecture Yasugi Yasugi-cho, 2107 address 2 Hitachi Metals Co., Ltd. metallurgy the laboratory (72) inventor Okikawa advance Shibaura, Minato-ku, Tokyo chome No. 2 No. 1 Hitachi in the metals Co., Ltd.

Claims (5)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】 半導体素子から信号を導くリード部と、 A lead portion for guiding a signal from 1. A semiconductor device,
    該リード部の一部に設けたランド部と、該ランド部から絶縁層を貫通して形成されたポスト部と、該ポスト部の先端に端子部を有する半導体素子搭載用配線板において、ランド部とポスト部の間に、リード部及びランド部とポスト部の両方または何れか一方とはエッチング特性が異なる導体層が形成されていることを特徴とする半導体素子搭載用配線板。 A land portion provided on a portion of the lead portion, and a post portion which is formed through the insulating layer from the land portion, in the semiconductor element mounting wiring board having a terminal portion at the tip of the post portion, a land portion and during the post portion, the lead portion and the land portion and the post portion of both or either the element mounting wiring board, characterized in that the etching characteristics are different conductor layers formed.
  2. 【請求項2】 半導体素子搭載用配線板の厚さが0.2mm 2. A semiconductor device thickness of the mounting wiring board 0.2mm
    以下であることを特徴とする請求項1に記載の半導体素子搭載用配線板。 Element mounting wiring board according to claim 1, wherein the or less.
  3. 【請求項3】 リード部及びランド部とポスト部がCuまたはCu合金からなり、且つ導体層がAgまたはAg合金からなることを特徴とする請求項1または2に記載の半導体素子搭載用配線板。 Wherein the lead portion and a land portion and a post portion is made of Cu or Cu alloy, and the semiconductor element mounting wiring board according to claim 1 or 2 conductor layer is characterized by comprising the Ag or Ag alloy .
  4. 【請求項4】 導体層は乾式成膜された乾式成膜層であることを特徴とする請求項1乃至3の何れかに記載の半導体素子搭載用配線板。 Wherein the conductor layer is a semiconductor element mounting wiring board according to any one of claims 1 to 3, characterized in that a dry film formation layer which is dry deposition.
  5. 【請求項5】 請求項1乃至4の何れかに記載の半導体素子搭載用配線板を用いてなることを特徴とする半導体素子搭載パッケージ。 5. A semiconductor element mounting package that characterized by using the element mounting wiring board according to any one of claims 1 to 4.
JP2001093719A 2001-03-28 2001-03-28 Wiring board for mounting semiconductor device and semiconductor device mounting package using the same Abandoned JP2002289749A (en)

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WO2010035509A1 (en) * 2008-09-29 2010-04-01 凸版印刷株式会社 Lead frame substrate manufacturing method and semiconductor device
CN102365736A (en) * 2009-03-30 2012-02-29 凸版印刷株式会社 Semiconductor device and method of manufacturing substrates for semiconductor elements
JP2014168094A (en) * 2004-06-25 2014-09-11 Tessera Inc Micro electronic component package and method therefor

Cited By (10)

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Publication number Priority date Publication date Assignee Title
JP2014168094A (en) * 2004-06-25 2014-09-11 Tessera Inc Micro electronic component package and method therefor
WO2010035509A1 (en) * 2008-09-29 2010-04-01 凸版印刷株式会社 Lead frame substrate manufacturing method and semiconductor device
CN102165581A (en) * 2008-09-29 2011-08-24 凸版印刷株式会社 Lead frame substrate manufacturing method and semiconductor device
KR101613828B1 (en) 2008-09-29 2016-04-19 도판 인사츠 가부시키가이샤 Manufacturing method of lead frame substrate
US8546940B2 (en) 2008-09-29 2013-10-01 Toppan Printing Co., Ltd. Manufacturing method of lead frame substrate and semiconductor apparatus
US8703598B2 (en) 2008-09-29 2014-04-22 Toppan Printing Co., Ltd. Manufacturing method of lead frame substrate
JP2010086983A (en) * 2008-09-29 2010-04-15 Toppan Printing Co Ltd Lead frame substrate manufacturing method and semiconductor device
US8466547B2 (en) 2009-03-30 2013-06-18 Toppan Printing Co., Ltd. Method for manufacturing substrate for semiconductor element, and semiconductor device
KR101609016B1 (en) 2009-03-30 2016-04-04 도판 인사츠 가부시키가이샤 Semiconductor device and method of manufacturing substrates for semiconductor elements
CN102365736A (en) * 2009-03-30 2012-02-29 凸版印刷株式会社 Semiconductor device and method of manufacturing substrates for semiconductor elements

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