JP2002268709A - Sequence arithmetic executing device for programmable controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the sequence arithmetic execution device of a programmable controller whose arithmetic speed is high. SOLUTION: A programmable controller to which a memory for performing reading and writing by every bit is connected is constituted so that a memory writing instruction can be executed by executing each arithmetic operation simultaneously with one time memory reading.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable controller and, more particularly, to a sequence operation execution device of a programmable controller for executing a sequence operation.

[0002]

2. Description of the Related Art Conventionally, in order to execute a sequence of a programmable controller, a command from a microcomputer is given to a CPU, and a calculation is performed by the CPU based on the command, and a calculation in a program memory is performed based on a result of the calculation. I have.

[0003]

However, such a configuration is not preferable in a field where a calculation speed is required both electrically and mechanically. The present invention has been made in view of the above points, and an object of the present invention is to provide a sequence operation execution device of a programmable controller having a high operation speed.

[0004]

In other words, a means for achieving the object is a programmable controller connected to a memory for reading and writing one bit at a time.
LOAD, AN as program memory command from U
Input means having D, OR, and STORE; determining means for determining which instruction is to be used from the input means; selecting means for selecting a memory command determined by the determining means; Holding means for holding an operation result;
The data of the holding means is stored as RAM and
A general-purpose memory for inputting an address of the AM, a logical operation means for performing an operation based on a command for calling the holding means, and a NOT for negating output data from the logical operation means
NOT instruction means for outputting an instruction, storage means for storing data at an address designated in the general-purpose memory, operation selection means for arithmetically selecting whether the data of the storage means or the data of the selection means, Inverting means for inverting the output data of the selecting means in response to the input of the NOT instruction means, an internal register address, that is, an execution instruction for executing which register and an index value of the execution instruction are specified. An address offset means capable of inputting each of the index register designation commands and designating an address offset with respect to the address of the general-purpose memory in advance is provided. Programmable computer characterized by being executed It is a sequence operation execution device of the roller. Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing an embodiment of the present invention. Reference numeral 1 denotes input means having LOAD, AND, OR, and STORE as program memory commands from a CPU; Determining means for determining which instruction is to be used; 3 means selecting means for calculating the memory command determined by the determining means 2; 4 holding means for holding the calculation result of the selecting means 3; Data of R
This is a general-purpose memory that stores as an AM and inputs the address of the RAM.

Further, reference numeral 6 denotes a logical operation means for performing an operation based on a command for calling the holding means 4, and 7 denotes a logical operation means 6.
NO to output NOT instruction to negate output data from
T instruction means, 8 is storage means for storing data at an address designated by the general-purpose memory 5, 9 is operation selection means for performing operation selection of data of the storage means 8 or data of the selection means 3, and 10 is a NOT instruction. Inverting means for inverting the output data of the selecting means 3 by the input of the means 7;
Reference numeral 1 denotes an address of the general-purpose memory 5 by inputting an internal register address, that is, an execution command 11a for executing which register and an index register specification command 11b for specifying which of the index values of the execution command are valid. Is an address offset means that can specify an address offset in advance for.

That is, in a programmable controller connected to a memory configured to read and write for each bit configured as described above, the above-described operations are performed and a memory write instruction is executed at the same time as reading the memory once. Things. Since the address offset means 11 is a known technique, its description is omitted here.

Next, the operation will be described. In FIG. 1, when performing memory writing, a CPU (not shown) transmits a LOAD, AND, OR, or STORE operation instruction for each bit to the determination means 2.
(D20, D21) Then, one of the commands determined here is transmitted to the selection means 3. Thereafter, the holding unit 4 holds the result of the operation on the selected data. Further, the held select data is input to the general-purpose memory 5 as a RAM, and is stored as an address of the RAM.

Next, in the case of reading, the arithmetic unit 12 (RD) determines whether to select the data of the storage means 8 for storing data at the address designated by the general-purpose memory 5 or the data of the selection means 3. Is selected by the operation selecting means 9 via the CPU. (D0 to D18) The output data from the logical operation means 6 is a NOT instruction (NO
N that outputs TLOAD, NOTAND, NOTOR)
OT command means 7 (1 or 0 of B contact D19 not shown)
Regulated by

[0010]

As described above, according to the present invention, the above-mentioned operations are performed and the memory write instruction is executed at the same time when the memory is read once. This makes it possible to execute the operation in a short time and eliminate the need for a microcomputer, which is extremely useful in practice.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a control circuit showing one embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Input means 2 Discrimination means 3 Selection means 4 Holding means 5 General-purpose memory 6 Logical operation means 7 NOT instruction means 8 Store means 9 Operation selection means 10 Inversion means 11 Address offset means 11a Execution command 11b Index register designation command 12 Computing unit

Claims (1)

[Claims] In a programmable controller to which a memory for reading and writing data for each bit is connected, LOAD, AND, and O are supplied as program memory commands from a CPU.
Input means having R and STORE, determining means for determining which instruction is to be used from the input means, selecting means for selecting a memory command determined by the determining means, and a calculation result of the selecting means Holding means, a general-purpose memory for storing data of the holding means as a RAM and inputting an address of the RAM, a logical operation means for performing an operation based on a command for calling the holding means, and a logical operation means NOT instruction means for outputting a NOT instruction for negating output data from the memory, storage means for storing data at an address designated by the general-purpose memory,
Operation selecting means for calculating and selecting whether the data of the storing means or the data of the selecting means, inverting means for inverting the output data of the selecting means by the input of the NOT instruction means, and an internal register address, that is, a register Address offset means for inputting an execution command for executing the command and an index register specifying command for specifying which of the index values of the execution command are to be valid, and specifying an address offset in advance for the address of the general-purpose memory A sequence operation execution device for a programmable controller, wherein each of the operations is performed to execute a memory write instruction at the same time as one read operation of the memory.