JP2002262573A - Power device - Google Patents

Power device

Info

Publication number
JP2002262573A
JP2002262573A JP2001055225A JP2001055225A JP2002262573A JP 2002262573 A JP2002262573 A JP 2002262573A JP 2001055225 A JP2001055225 A JP 2001055225A JP 2001055225 A JP2001055225 A JP 2001055225A JP 2002262573 A JP2002262573 A JP 2002262573A
Authority
JP
Japan
Prior art keywords
resistor
smoothing capacitor
circuit
fet
discharge
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001055225A
Other languages
Japanese (ja)
Inventor
Hitoshi Uemura
仁 植村
Original Assignee
Nichicon Corp
ニチコン株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nichicon Corp, ニチコン株式会社 filed Critical Nichicon Corp
Priority to JP2001055225A priority Critical patent/JP2002262573A/en
Publication of JP2002262573A publication Critical patent/JP2002262573A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide a power device which reduces power loss generated by a discharging circuit when an AC input is applied. SOLUTION: In a power device for converting a DC voltage obtained from a rectifying and smoothing circuit composed of a rectifying circuit and a first smoothing capacitor into a specified voltage, a series circuit composed of a second smoothing capacitor and a first resistor connected to an AC input side is connected to an emitter of an NPN transistor. A second resistor and a third resistor connected in parallel with the second smoothing capacitor are connected to the base of the NPN transistor, and its collector is connected to the gate of an FET. Also, a discharging resistor is connected between the drain of the FET and the positive electrode of the first smoothing capacitor. A fourth resistor is connected between the gate and the discharging resistor, and a fifth resistor is connected between the gate and the source. The negative electrode of the second smoothing capacitor, the third resistor and the fifth resistor, the emitter of the NPN transistor, and the source of the FET are connected to the negative electrode of the first smoothing capacitor, to form a discharging circuit for the first smoothing capacitor.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION
【0001】[0001]
【発明の属する技術分野】本発明は電力消費を抑えた電
源装置に関するものであり、交流入力オフ時にのみ放電
抵抗に電流を流し、オン時には電流を流さない放電回路
を接続し、放電抵抗による電力消費を抑えた電源装置に
関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply device which suppresses power consumption. The present invention relates to a power supply device which supplies a current to a discharge resistor only when an AC input is off and connects a discharge circuit which does not flow a current when the AC input is on. The present invention relates to a power supply device with reduced consumption.
【0002】[0002]
【従来の技術】図4は、従来の電源装置の回路図で、整
流・平滑回路3の出力側の正〜負極間に放電抵抗13を
接続して放電を行っているが、放電の評価に際しては、
安全規格である、UL1950 2.1.4項の確認試
験、CAPACITOR STORED ENERGY
TESTがあり、これによれば、電源遮断1分後の平
滑コンデンサ2の電圧が、60V(危険電圧)以下にな
らなければならないとされており、当該規格を満足する
ためには、放電回路によりコンデンサの放電を行う必要
がある。図4では、整流・平滑回路3の出力側の正〜負
極間に放電抵抗13を接続して放電を行っているが、交
流入力オン時において、放電抵抗13に電力消費が発生
し、特に整流・平滑回路3の平滑用コンデンサ2が大容
量になればなるほど、上記安全規格を満たすため放電抵
抗13に大きな抵抗が必要であり、放電抵抗13による
電力消費が大きくなり、最近厳しくなってきた待機時の
消費電力・発熱規制において問題となる。
2. Description of the Related Art FIG. 4 is a circuit diagram of a conventional power supply device, in which a discharge resistor 13 is connected between a positive electrode and a negative electrode on the output side of a rectifying / smoothing circuit 3 to perform discharge. Is
Confirmation test of UL1950 2.1.4 which is a safety standard, CAPACITOR STORED ENERGY
According to TEST, it is stated that the voltage of the smoothing capacitor 2 one minute after the power is turned off must be 60 V (dangerous voltage) or less. It is necessary to discharge the capacitor. In FIG. 4, the discharge is performed by connecting the discharge resistor 13 between the positive and negative electrodes on the output side of the rectifying / smoothing circuit 3. As the capacity of the smoothing capacitor 2 of the smoothing circuit 3 increases, the discharge resistor 13 needs to have a larger resistance to satisfy the above safety standards, and the power consumption by the discharge resistor 13 increases, and the standby which has recently become severer It becomes a problem in regulation of power consumption and heat generation at the time.
【0003】[0003]
【発明が解決しようとする課題】上記のような問題があ
ったため、交流入力オン時において、放電抵抗13によ
る電力消費を抑えることができる回路構成が要求されて
いた。
Due to the above-mentioned problems, there has been a demand for a circuit configuration capable of suppressing power consumption by the discharge resistor 13 when the AC input is ON.
【0004】[0004]
【課題を解決するための手段】本発明は、上記の課題を
解決するものであり、交流入力オフ時のみ放電抵抗に電
流を流し、オン時には流さない放電回路を接続すること
により、交流入力オン時の電力消費を抑えようとするも
のである。すなわち、交流電圧を整流回路1と第1の平
滑コンデンサ2からなる整流・平滑回路に入力し、得ら
れた直流電圧をDC/DCコンバータ4により所定の電
圧に変換する電源装置において、交流入力側に接続した
第1の抵抗6と第2の平滑コンデンサ7の直列回路をN
PNトランジスタ10のエミッタに接続し、第2の平滑
コンデンサ7と並列接続した第2の抵抗8および第3の
抵抗9をNPNトランジスタ10のベースに、コレクタ
をFET14のゲートに接続し、また、該FET14の
ドレインと第1の平滑コンデンサ2の正極との間に放電
抵抗13を、ゲートと放電抵抗13との間に第4の抵抗
11を、ゲート・ソース間に第5の抵抗12を接続し、
第2の平滑コンデンサ7の負極と、第3の抵抗9および
第5の抵抗12と、NPNトランジスタ10のエミッタ
と、FET14のソースとを第1の平滑コンデンサ2の
負極に接続して、第1の平滑コンデンサの放電回路を構
成したことを特徴とする電源装置である。
SUMMARY OF THE INVENTION The present invention is to solve the above-mentioned problem. The present invention is to solve the above-mentioned problem by connecting a discharge circuit which allows a current to flow through the discharge resistor only when the AC input is off and does not flow the current when the AC input is on. It is intended to reduce power consumption at the time. That is, in a power supply device that inputs an AC voltage to a rectifying / smoothing circuit including a rectifier circuit 1 and a first smoothing capacitor 2 and converts the obtained DC voltage to a predetermined voltage by a DC / DC converter 4, The series circuit of the first resistor 6 and the second smoothing capacitor 7 connected to
A second resistor 8 and a third resistor 9 connected to the emitter of the PN transistor 10 and connected in parallel with the second smoothing capacitor 7 are connected to the base of the NPN transistor 10, and the collector is connected to the gate of the FET 14. A discharge resistor 13 is connected between the drain of the FET 14 and the positive electrode of the first smoothing capacitor 2, a fourth resistor 11 is connected between the gate and the discharge resistor 13, and a fifth resistor 12 is connected between the gate and the source. ,
The negative electrode of the second smoothing capacitor 7, the third resistor 9 and the fifth resistor 12, the emitter of the NPN transistor 10, and the source of the FET 14 are connected to the negative electrode of the first smoothing capacitor 2, And a discharge circuit for the smoothing capacitor.
【0005】[0005]
【発明の実施の形態】図1に示すように、交流入力側に
接続した第1の抵抗6と第2の平滑コンデンサ7の直列
回路をNPNトランジスタ10のエミッタに接続し、第
2の平滑コンデンサ7と並列接続した第2の抵抗8およ
び第3の抵抗9をNPNトランジスタ10のベースに、
コレクタをFET14のゲートに接続し、また、該FE
T14のドレインと第1の平滑コンデンサ2の正極との
間に放電抵抗13を、ゲートと放電抵抗13との間に第
4の抵抗11を、ゲート・ソース間に第5の抵抗12を
接続し、第2の平滑コンデンサ7の負極と、第3の抵抗
9および第5の抵抗12と、NPNトランジスタ10の
エミッタと、FET14のソースとを第1の平滑コンデ
ンサ2の負極に接続して、第1の平滑コンデンサの放電
回路を構成する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS As shown in FIG. 1, a series circuit of a first resistor 6 and a second smoothing capacitor 7 connected to an AC input side is connected to an emitter of an NPN transistor 10, and a second smoothing capacitor is connected. 7, a second resistor 8 and a third resistor 9 connected in parallel to the base of the NPN transistor 10,
A collector is connected to the gate of FET 14 and the FE
A discharge resistor 13 is connected between the drain of T14 and the positive electrode of the first smoothing capacitor 2, a fourth resistor 11 is connected between the gate and the discharge resistor 13, and a fifth resistor 12 is connected between the gate and the source. The negative electrode of the second smoothing capacitor 7, the third resistor 9 and the fifth resistor 12, the emitter of the NPN transistor 10, and the source of the FET 14 are connected to the negative electrode of the first smoothing capacitor 2, One discharging circuit of the smoothing capacitor is formed.
【0006】[0006]
【実施例】本発明の実施例による電源装置の回路を図1
に示す。交流入力オン時には、図2に示すような電流が
流れ、第1の抵抗6を経由して第2の平滑コンデンサ7
に電圧が印加され、平滑された後、第2の抵抗8と第3
の抵抗9とで分圧されてNPNトランジスタ10のベー
スに入力されることにより、トランジスタ10がオン
し、FET14をオフさせて、放電抵抗13に電流が流
れないようにし、電力消費しないようにさせる。交流入
力オフ時には、NPNトランジスタ10がオフになり、
図3に示すような電流が流れ、整流・平滑回路3内の第
1の平滑コンデンサ2の電圧が、第4の抵抗11と第5
の抵抗12とで分圧されてFET14のゲートに入力さ
れ、設定電圧以下になるまでは、FET14がオンし続
けるようにする。第1の抵抗6、第2の抵抗8、第3の
抵抗9、第4の抵抗11、第5の抵抗12を適正値に設
定することにより、交流入力オン時の放電回路による電
力消費を抑えることができる。
FIG. 1 is a circuit diagram of a power supply device according to an embodiment of the present invention.
Shown in When the AC input is on, a current as shown in FIG. 2 flows and passes through the first resistor 6 to the second smoothing capacitor 7.
After the voltage is applied and smoothed, the second resistor 8 and the third
Is divided by the resistor 9 and inputted to the base of the NPN transistor 10, the transistor 10 is turned on and the FET 14 is turned off, so that no current flows through the discharge resistor 13 and power is not consumed. . When the AC input is off, the NPN transistor 10 turns off,
A current as shown in FIG. 3 flows, and the voltage of the first smoothing capacitor 2 in the rectifying / smoothing circuit 3 is changed by the fourth resistor 11 and the fifth resistor 11.
The voltage is divided by the resistor 12 and input to the gate of the FET 14, and the FET 14 is kept turned on until the voltage drops below the set voltage. By setting the first resistor 6, the second resistor 8, the third resistor 9, the fourth resistor 11, and the fifth resistor 12 to appropriate values, power consumption by the discharge circuit when the AC input is turned on is suppressed. be able to.
【0007】図1の実施例による電源装置と図2の従来
例とで、放電回路による電力損失を測定し比較した。そ
の結果を〔表1〕に示す。なお、入力電圧はAC120
Vとし、第1の平滑コンデンサ2の容量は4400μF
とし、放電抵抗13の抵抗値は交流入力オフ後1分間で
第1の平滑コンデンサの電圧を60V以下にできる値と
して、13kΩに設定した。また、交流入力オン時のN
PNトランジスタ10のオン動作、および交流入力オフ
時のFET14のオン動作が適正に行われるように、第
1〜第5の抵抗値は、第1の抵抗6を220kΩ、第2
の抵抗8を100kΩ、第3の抵抗9を10kΩ、第4
の抵抗11を470kΩ、第5の抵抗12を47kΩに
設定した。〔表1〕より明らかなように、本発明の実施
例による電源装置は、従来例によるものより放電回路に
よる電力損失が著しく低減されていることが分かる。
The power loss by the discharge circuit was measured and compared between the power supply device according to the embodiment of FIG. 1 and the conventional example of FIG. The results are shown in [Table 1]. The input voltage is AC120
V and the capacity of the first smoothing capacitor 2 is 4400 μF
The resistance value of the discharge resistor 13 was set to 13 kΩ so that the voltage of the first smoothing capacitor could be reduced to 60 V or less in one minute after the AC input was turned off. Also, when the AC input is on, N
The first to fifth resistance values are such that the first resistor 6 is set to 220 kΩ, the second resistor is set to 220 kΩ, so that the ON operation of the PN transistor 10 and the ON operation of the FET 14 when the AC input is OFF are properly performed.
Of the resistor 8 is 100 kΩ, the third resistor 9 is 10 kΩ,
The resistance 11 was set to 470 kΩ, and the fifth resistance 12 was set to 47 kΩ. As is clear from Table 1, the power supply according to the embodiment of the present invention has significantly reduced power loss due to the discharge circuit as compared with the conventional power supply.
【0008】[0008]
【表1】 [Table 1]
【0009】[0009]
【発明の効果】上記したように、本発明による放電回路
を接続することにより、交流入力オン時の放電回路によ
る電力損失を著しく低減させることができる。
As described above, by connecting the discharge circuit according to the present invention, it is possible to significantly reduce the power loss due to the discharge circuit when the AC input is turned on.
【図面の簡単な説明】[Brief description of the drawings]
【図1】本発明の実施例による電源装置の回路図であ
る。
FIG. 1 is a circuit diagram of a power supply device according to an embodiment of the present invention.
【図2】図1において、交流入力をオンにした時の電流
の流れを示す図である。
FIG. 2 is a diagram showing a current flow when an AC input is turned on in FIG.
【図3】図1において、交流入力をオフにした時の電流
の流れを示す図である。
FIG. 3 is a diagram showing a current flow when an AC input is turned off in FIG.
【図4】従来例による電源装置の回路図である。FIG. 4 is a circuit diagram of a power supply device according to a conventional example.
【符号の説明】[Explanation of symbols]
1 整流回路 2 第1の平滑コンデンサ 3 整流・平滑回路 4 DC/DCコンバータ 6 第1の抵抗 7 第2の平滑コンデンサ 8 第2の抵抗 9 第3の抵抗 10 NPNトランジスタ 11 第4の抵抗 12 第5の抵抗 13 放電抵抗 14 FET DESCRIPTION OF SYMBOLS 1 Rectifier circuit 2 1st smoothing capacitor 3 Rectifying / smoothing circuit 4 DC / DC converter 6 1st resistor 7 2nd smoothing capacitor 8 2nd resistor 9 3rd resistor 10 NPN transistor 11 4th resistor 12th Resistance of 5 13 Discharge resistance 14 FET

Claims (1)

    【特許請求の範囲】[Claims]
  1. 【請求項1】 交流電圧を整流回路と第1の平滑コンデ
    ンサからなる整流・平滑回路に入力し、得られた直流電
    圧をDC/DCコンバータにより所定の電圧に変換する
    電源装置において、 交流入力側に接続した第1の抵抗と第2の平滑コンデン
    サの直列回路をNPNトランジスタのエミッタに接続
    し、第2の平滑コンデンサと並列接続した第2および第
    3の抵抗をNPNトランジスタのベースに、コレクタを
    FETのゲートに接続し、また、該FETのドレインと
    第1の平滑コンデンサの正極との間に放電抵抗を、ゲー
    トと放電抵抗との間に第4の抵抗を、ゲート・ソース間
    に第5の抵抗を接続し、第2の平滑コンデンサの負極
    と、第3および第5の抵抗と、NPNトランジスタのエ
    ミッタと、FETのソースとを第1の平滑コンデンサの
    負極に接続して、第1の平滑コンデンサの放電回路を構
    成したことを特徴とする電源装置。
    1. A power supply device for inputting an AC voltage to a rectifying / smoothing circuit comprising a rectifier circuit and a first smoothing capacitor, and converting the obtained DC voltage to a predetermined voltage by a DC / DC converter. Is connected to the emitter of the NPN transistor, the second and third resistors connected in parallel with the second smoothing capacitor are connected to the base of the NPN transistor, and the collector is connected to the NPN transistor. Connected to the gate of the FET, a discharge resistor between the drain of the FET and the positive electrode of the first smoothing capacitor, a fourth resistor between the gate and the discharge resistor, and a fifth resistor between the gate and the source. And the negative electrode of the second smoothing capacitor, the third and fifth resistors, the emitter of the NPN transistor, and the source of the FET are connected to the negative electrode of the first smoothing capacitor. Connected to the power supply apparatus characterized by being configured to discharge circuit of the first smoothing condenser.
JP2001055225A 2001-02-28 2001-02-28 Power device Pending JP2002262573A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001055225A JP2002262573A (en) 2001-02-28 2001-02-28 Power device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001055225A JP2002262573A (en) 2001-02-28 2001-02-28 Power device

Publications (1)

Publication Number Publication Date
JP2002262573A true JP2002262573A (en) 2002-09-13

Family

ID=18915436

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001055225A Pending JP2002262573A (en) 2001-02-28 2001-02-28 Power device

Country Status (1)

Country Link
JP (1) JP2002262573A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006204028A (en) * 2005-01-21 2006-08-03 Matsushita Electric Ind Co Ltd Direct-current power supply unit
JP2009112156A (en) * 2007-10-31 2009-05-21 Nichicon Corp Constant-power discharge circuit and power converter with it
JP2009165208A (en) * 2007-12-28 2009-07-23 Daikin Ind Ltd Discharging circuit for converters
JP2009254183A (en) * 2008-04-09 2009-10-29 Corona Corp Power-supply board with discharge circuit for smoothing capacitor
JP2011193667A (en) * 2010-03-16 2011-09-29 Konica Minolta Business Technologies Inc Power supply and image forming apparatus
JP2011234481A (en) * 2010-04-27 2011-11-17 Daikin Ind Ltd Discharge device and air conditioning device
CN103444067A (en) * 2011-04-25 2013-12-11 爱信艾达株式会社 Discharge control circuit
CN104901297A (en) * 2015-06-26 2015-09-09 珠海格力电器股份有限公司 Discharge circuit of air conditioner and discharge method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6377383A (en) * 1986-09-20 1988-04-07 Pfu Ltd Starting circuit
JPH0583944A (en) * 1991-09-19 1993-04-02 Matsushita Electric Ind Co Ltd Power supply equipment
JPH08336281A (en) * 1995-04-07 1996-12-17 Sankyo Seiki Mfg Co Ltd Residual voltage protector for electric circuit
JP2000184718A (en) * 1998-12-10 2000-06-30 Sharp Corp Switching power supply device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6377383A (en) * 1986-09-20 1988-04-07 Pfu Ltd Starting circuit
JPH0583944A (en) * 1991-09-19 1993-04-02 Matsushita Electric Ind Co Ltd Power supply equipment
JPH08336281A (en) * 1995-04-07 1996-12-17 Sankyo Seiki Mfg Co Ltd Residual voltage protector for electric circuit
JP2000184718A (en) * 1998-12-10 2000-06-30 Sharp Corp Switching power supply device

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006204028A (en) * 2005-01-21 2006-08-03 Matsushita Electric Ind Co Ltd Direct-current power supply unit
JP4682624B2 (en) * 2005-01-21 2011-05-11 パナソニック株式会社 DC power supply
JP2009112156A (en) * 2007-10-31 2009-05-21 Nichicon Corp Constant-power discharge circuit and power converter with it
JP2009165208A (en) * 2007-12-28 2009-07-23 Daikin Ind Ltd Discharging circuit for converters
JP2009254183A (en) * 2008-04-09 2009-10-29 Corona Corp Power-supply board with discharge circuit for smoothing capacitor
JP2011193667A (en) * 2010-03-16 2011-09-29 Konica Minolta Business Technologies Inc Power supply and image forming apparatus
JP2011234481A (en) * 2010-04-27 2011-11-17 Daikin Ind Ltd Discharge device and air conditioning device
CN103444067A (en) * 2011-04-25 2013-12-11 爱信艾达株式会社 Discharge control circuit
CN104901297A (en) * 2015-06-26 2015-09-09 珠海格力电器股份有限公司 Discharge circuit of air conditioner and discharge method thereof

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