JP2002258957A - Fet driving circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an FET driving circuit available for a circuit using various power supply voltages capable of supplying a high voltage to the gate electrode of an FET. SOLUTION: This FET driving circuit is provided with a first power supply voltage supply terminal, a second power supply voltage supply terminal whose polarity is the same as that of the first power supply voltage, and whose absolute value is high, a three terminal regulator circuit having a voltage input terminal, a ground terminal, and a fixed voltage output terminal whose voltage input terminal is connected to the second power source supply terminal and whose ground terminal is connected to the first power source supply terminal, and a sink circuit for allowing fixed currents to run from the ground terminal of the three terminal regulator circuit to the first power source supply terminal so that a prescribed potential difference can be formed between the output terminal of the three terminal regulator circuit and the first power source supply terminal. The first power source supply terminal is connected to the drain electrode of an FET to be driven, and the output terminal of the fixed voltage of the three terminal regulator circuit is connected to the gate electrode.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an FET drive circuit.

[0002]

2. Description of the Related Art An FET (field-effect transistor) has a high input impedance,
Unlike a bipolar transistor, it is often used as a switching transistor because it has no offset voltage and has excellent high-speed switching characteristics.

The above-mentioned FET is turned on when a voltage higher than a predetermined threshold is applied to the gate electrode. In this case, the drain-source voltage drops (losses) by a predetermined potential due to the ON resistance of the FET. The loss due to the on-resistance is preferably low from the viewpoint of suppressing power consumption.

FIG. 6 shows that the gate voltage V _GS is 4 V, 10 V
ON resistance R between drain and source in the case of
₉ is a graph showing a relationship between _DS and a drain current _ID .
As appears, who gate voltage V _GS is high on-resistance R _DS is seen to be lower.

[0005] In order to reduce the on-resistance of the FET, various FET driving circuits for applying a high voltage to the gate electrode have been proposed. For example, the FE of model number MAX620 / 621 provided by Maxim Japan Co., Ltd.
The T drive circuit contains four MOSFET drivers and one charge pump high side power supply. The charge pump type high side power supply supplies a stabilized voltage 11 V higher than the power supply voltage Vcc to the internal driver. The operation of the internal driver drives the FET connected to the subsequent stage.

[0006]

In the conventional FET drive circuit, the power supply voltage Vcc = 4.5 to 16.5 V, and the input signal threshold level (threshold for recognizing H and L) is Low: MAX 0.8 V. , High: MIN 2.4V. For this reason, a circuit using a lower power supply voltage such as a 1.8 V system, a 2.5 V system, and a 3.3 V system may not be used as it is. For example, the power supply voltage Vcc =
F using a switching transistor that turns on at 5V
In the case of an ET drive circuit, the switching transistor cannot be switched even when used in a system using a low power supply voltage such as the 1.8 V system described above, and cannot function normally.

[0007] Therefore, the present invention is not limited to the 5V system,
It can be used for circuits using various power supply voltages _Vcc1 , such as 1.8V system, 2.5V system, and 3.3V system.
_An object of the present invention is to provide an FET drive circuit capable of supplying a voltage _Vcc3, which is higher than _cc1 by a predetermined potential ΔV, to a gate electrode of an FET.

[0008]

A first FET drive circuit according to the present invention comprises a supply terminal for a first power supply voltage Vcc1 and the first terminal.
The supply terminal of the second power supply voltage Vcc2 having the same sign as the power supply voltage Vcc1 and having an absolute value higher than the first power supply voltage Vcc1, the voltage input terminal Vin, the ground terminal GND, and the output terminal Vout of the constant voltage Vcc3 are connected. A three-terminal regulator circuit having the voltage input terminal Vin connected to the supply terminal of the second power supply voltage Vcc2 and the ground terminal GND connected to the supply terminal of the first power supply voltage Vcc1; The predetermined potential difference ΔV is formed between the output terminal Vout of the circuit and the supply terminal of the first power supply voltage Vcc1,
From the ground terminal GND of the three-terminal regulator circuit to the first
A sink circuit for supplying a constant current to a supply terminal of the power supply voltage Vcc1, a supply terminal of the first power supply voltage Vcc1 is connected to a drain electrode of a FET to be driven, and a constant voltage Vcc3 of the three-terminal regulator circuit is connected to a gate electrode. (= Vcc1 + Δ
V) is connected to the output terminal Vout.

A second FET drive circuit according to the present invention is characterized in that, in the first FET drive circuit, the three-terminal regulator circuit is a variable type.

According to a third FET drive circuit of the present invention, in any one of the above-mentioned FET drive circuits, the sink circuit has one end connected to a supply terminal of the first power supply voltage Vcc1, and the other end grounded. It is characterized by being.

In a fourth FET drive circuit according to the present invention, in the first or second FET drive circuit, the sink circuit is configured such that a ground terminal GND of a three-terminal regulator circuit is connected to a negative-phase input terminal; The operational amplifier is characterized in that the supply terminal of the power supply voltage Vcc1 is connected to the positive phase input terminal and negative feedback is applied.

[0012]

FET drive circuit of the Summary of the Invention Detailed Description of the Invention] (1) invention, voltage input terminal _{V in,} the ground terminal GND, and and, the output terminal _{V out} of _the constant voltage _{V cc3}
And a constant voltage _Vcc3 (= Vcc1 +) that is higher by a predetermined potential difference ΔV by regarding the first power supply voltage _Vcc1 as a ground potential.
ΔV), and an output terminal V of a constant voltage _Vcc3 of the three-terminal regulator circuit.
_out and so that the potential difference ΔV is formed between the supply terminal of the first power supply voltage V _cc1, sink circuit for supplying a constant current to supply terminal of the first power supply voltage V _cc1 from the ground terminal GND of the three terminal regulator circuit And the driving target F
The supply terminal of the first power supply voltage _Vcc1 is connected to the drain electrode of ET, and the output terminal _Vout of the constant voltage _Vcc3 (= _Vcc1 + ΔV) of the three-terminal regulator circuit is connected to the gate electrode. Features. By adopting this configuration, regardless of the value of the first power supply voltage V _cc1, it becomes always V _{cc1 +} [Delta] V constant voltage V _{cc 3} elevated to can be applied to the gate electrode of the driving target of the FET. Hereinafter, Embodiments 1 to 4 of the FET drive circuit having the above features will be described with reference to the accompanying drawings.

(2) First Embodiment FIG. 1 is a circuit diagram of an FET drive circuit 100 according to a first embodiment. The FET drive circuit 100 has a first power supply voltage V
_cc1 is regarded as a ground potential and a constant voltage V boosted by ΔV
_{It is characterized} by including a variable three-terminal regulator circuit A1 that outputs _cc3 to the gate electrode of the N-channel FET 4, and a sink circuit C1 that _{generates a} current flow so that the three-terminal regulator circuit functions.

Before explaining the circuit shown in FIG. 1, the variable type 3 which is also used in the three-terminal regulator circuit A1 will be described.
Configuration of terminal regulator circuit IC 2 and said IC
The configuration of a well-known variable three-terminal regulator circuit using the circuit No. 2 will be briefly described.

FIG. 2 is for a variable three-terminal regulator circuit.
Internal equivalent circuit of IC2 and configuration using IC2
FIG. 1 is a diagram showing a known variable three-terminal regulator circuit.
is there. The variable type three-terminal regulator circuit IC2 calculates
Consists of an amplifier 21, a transistor 22, and a power supply 23
Is done. The negative-phase input terminal of the operational amplifier 21 outputs a constant voltage.
Force terminal V_outAnd the positive-phase input terminal is connected to the output 1.
Connected to ADJ terminal via 25V power supply 23 and output
The terminal is connected to the gate electrode of the transistor 22.
The drain electrode of the transistor 22 is connected to the voltage input terminal V_in
And the source electrode is a constant voltage output terminal V_outTo
It is connected. For a three-terminal regulator circuit with this configuration
Inside the IC2, the output terminal V of the IC2_outMore output
Voltage after passing through a predetermined load (resistor R1).
The potential is changed to the reference voltage V by the power supply 23. _ref= 1.25V
The boosted value is compared by the operational amplifier 21 to determine the ratio.
The gate electrode of the transistor 22 is marked based on the comparison result.
Feedback control for adjusting the applied voltage is performed. Specifically, the ratio
When the returned voltage is low, the comparator 21
The value of the voltage supplied to the gate electrode of the star 22 is increased.

A well-known variable three-terminal regulator circuit is:
The constant voltage output terminal _Vout and the terminal AD of the IC2 having the above-described configuration.
A resistor R1 is interposed between J and J, and an ADJ terminal is grounded via a variable resistor R2. Resistance R1
Is provided for flowing a constant current required for setting the output voltage _Vout between the output terminal _Vout and the ADJ terminal of the IC2. As described later, the variable resistor R2
Can be controlled to control the potential of the constant voltage _Vcc3 output from the output terminal _Vout .

[0017] Hereinafter, for convenience of explanation, a current flowing through the resistor R1 from the sandwiched therebetween point a to point b represent the I _{a b,} represents the potential difference between points a and b and V _ab, the variable three-terminal regulator The current flowing into the variable resistor R2 from the ADJ terminal of the circuit IC 2 is represented as I _ADJ . In the illustrated IC2, V _ab
= R1 × I _ab = 1.25 V, and the constant voltage V _out output from the output terminal V _out is R1 × I _ab
ab + R2 × ( _Iab + _IADJ ) = R1 × _Iab (1
+ R2 / R1) + R2 × I _ADJ = 1.25 (1 + R2
/ R1) + R2 represented as × _{I ADJ.} As described above, in the variable three-terminal regulator circuit, it is understood that the value of ΔV can be adjusted by changing the value of the variable resistor R2.

[0018] Note that the value of voltage applied to the voltage input terminal _{V in} of IC2 is specified according to the characteristics of IC2 to be used. For example, when using the model number LM317 manufactured by National Semiconductor Corporation as IC 2, dropout voltage _V in _{-V out} such that within the range of The suggested 3V to 40V, the voltage applied to the voltage input terminal _{V in} Specify the value of.

Returning to FIG. 1, the configuration of the FET drive circuit 100 will be described. As shown, the variable three-terminal regulator circuit A1 has the same configuration as the well-known three-terminal regulator circuit shown in FIG.
ND is the supply terminal 3 of the first power supply voltage _{Vcc1 at} the point c.
Is connected to the terminal. In addition, the voltage input terminal V of the IC 2 constituting the three-terminal regulator circuit A1
_In is connected to the supply terminal 1 of the second power supply voltage _Vcc2 , and the output terminal _Vout is connected to the gate electrode of the FET 4 driven via a predetermined circuit resistor 10.

The drain terminal of the FET 4 is connected to the supply terminal 3 for the first power supply voltage _Vcc1 , and the source electrode is connected to the load 6 whose other end is grounded. Note that the supply terminal 1 for the first power supply voltage _Vcc1 and the second power supply voltage Vcc
_A predetermined wiring capacitance 11 is interposed between the _{cc2 and} the supply terminal 3.

The ground terminal G of the three-terminal regulator circuit A1
ND and the contact c of the supply terminal 3 of the first power supply voltage _{V cc1,} the voltage difference _{V ab} generated across the resistor R1 so as to maintain constant current flows to the variable resistor R2 _{I ADJ} +
As sink circuit C1 flowing I _ab, providing a resistor R3 is grounded at the other end. By providing the sink circuit C1, the three-terminal regulator circuit A1 operates with the first power supply voltage V
It can be made to function to output a constant voltage _{Vcc3 obtained} by boosting _cc1 by a predetermined potential ΔV.

The gate electrode of FET4 are 3 except that the constant voltage output terminal _{V o ut} of terminal regulator circuit A1 is connected, the switching transistor 5 of換Ru P-channel type turn off / on according to the FET ON / OFF signal Grounded. If the switching transistor is switched off in response to the FET ON signal and switched on in response to the FET OFF signal, instead of the P-channel type switching transistor 5, another photocoupler, a relay switch, or the like is used. A switch may be used.

In the FET drive circuit 100 having the above configuration, F
In response to the ET ON signal, the gate electrode of the FET 4
1 power supply voltage V_cc1Constant voltage boosted by potential difference ΔV from
Pressure V _cc3Is applied. Further, the FET drive circuit 100
Is the gate electrode of FET4 in response to the FET OFF signal.
To ground to switch off the FET 4.

FIG. 6 shows that the gate voltage V _GS is 4 V, 10 V
ON resistance R between drain and source in the case of
₉ is a graph showing a relationship between _DS and a drain current _ID .
As appears, who gate voltage V _GS is high on-resistance R _DS is seen to be lower. FET drive circuit 100
So it is possible to apply a constant voltage _{V cc3} boosted by the potential difference ΔV from the first power supply voltage _{V cc1} to the gate electrode of the FET 4, it is possible to effectively reduce the on-resistance of the FET 4.

Conventional FET designed exclusively for 5V system
The driver (eg, model number MAX620 provided by Maxim Japan Co., Ltd.) has an input signal threshold: Low = 0.8V, High = 2.4V
Therefore, in the output signal from the IC driven by the low power supply voltage, the High level becomes as low as, for example, 1.9 V in the Vcc = 2 V system and 2.9 V in the Vcc = 3 V system. There are times when signals cannot be transmitted properly between circuits. Further, the above-mentioned conventional FET drive circuit can output only a voltage that is 11 V step-up with respect to the drive power supply of 4.5 V to 16 V. On the other hand, FE
The T drive circuit 100 _applies a value obtained by boosting _Vcc1 by ΔV to the FET regardless of the level of the first power supply voltage _Vcc1.
4, and the value of ΔV can be adjusted by changing the value of the variable resistor R2. Thereby, an IC driven by a low power supply voltage
The FET 4 can also be driven directly by the output signal from.

(3) Second Embodiment FIG. 2 is a circuit diagram of an FET drive circuit 200 according to a second embodiment. FET drive circuit 100 according to the first embodiment
The same components as those described above are denoted by the same reference numerals, and redundant description is omitted here. The FET drive circuit 200 includes a resistor R instead of the sink circuit C1 included in the FET drive circuit 100.
Current I _ADJ that flows to maintain the potential difference across
Is provided with a sink circuit C2 including a negative feedback type operational amplifier 7 for flowing current.

As shown, the sink circuit C2 comprises an operational amplifier 7 and a resistor R4. The positive-phase input terminal of the operational amplifier 7 is connected to the supply terminal 3 for the first power supply voltage _Vcc1 , and the negative-phase input terminal is connected to a conductive line connected from the ADJ terminal via the variable resistor R2. The negative-phase input terminal and the output terminal of the operational amplifier 7 are connected by a resistor R4, and a negative feedback is applied.

By adopting this configuration, the first embodiment
_Has the advantage that the loss of the first power supply voltage _Vcc1 in the sink circuit C2 can be eliminated as compared with the FET drive circuit 100 according to the first embodiment. The other configurations and operations on the circuit are the same as those of the above-described FET drive circuit 100, and thus further description will be omitted.

(4) Third Embodiment FIG. 4 is a circuit diagram of an FET drive circuit 300 according to a third embodiment. The FET drive circuit 300 operates the FET drive circuit 100 at a negative power supply voltage _-Vcc1 in order to drive the P-channel type FET _{54. The} basic configuration and operation are the same as those of the FET drive circuit 100. Is the same. The single-digit numbers of the reference numbers in the 50's attached to the components are the same as the reference numbers of the components of the corresponding FET drive circuit 100.

That is, the variable three-terminal regulator circuit A
1 ′ corresponds to the variable three-terminal regulator circuit A1 of the FET drive circuit 100, and the sink circuit C1 ′ corresponds to the sink circuit C1 of the FET drive circuit 100.

In FIG. 1, the circuit resistance 10 and the wiring capacitance 11 shown in FIG. 1 are not shown.
An FET drive circuit 400 according to a fourth embodiment described below
The same applies to

In the FET driving circuit 300, the FET
Instead of the P-channel type switching transistor 5 used in the drive circuit 100, FET ON / OF
As a switch to switch on / off according to the F signal,
The photo coupler 55 is employed. The photo coupler 55
Is a diode 55a that emits light in response to an ON signal, and a P-channel phototransistor 55 that is turned off when the diode 55a emits light and is turned on when the diode 55a is turned off.
b. Note that a P-channel type switching transistor, a relay switch, or the like may be used as long as it switches off / on in response to the FET ON / OFF signal.

The operation of the FET drive circuit 300 is the same as that of the FET drive circuit 100 according to the first embodiment except that it operates at the negative power supply voltage _-Vcc1 , and therefore, further description is omitted.

(5) Fourth Embodiment FIG. 5 is a circuit diagram of an FET drive circuit 400 according to a fourth embodiment. The FET drive circuit 400 drives the P-channel type FET 54, so that the FE according to the second embodiment is used.
The T drive circuit 200 operates at a negative power supply voltage _-Vcc1 , and has the same configuration as that of the FET drive circuit 200. The same components as the FET drive circuit 300 include:
They are denoted by the same reference numerals. In addition, the single digit number of the reference number in the 50s attached to each component is the corresponding FET.
It is the same as the reference number of each component of the drive circuit 200.

That is, the variable three-terminal regulator circuit A
1 'corresponds to the variable three-terminal regulator circuit A1 of the FET drive circuit 200, and the sink circuit C2' corresponds to the sink circuit C2 of the FET drive circuit 200.

In the FET drive circuit 400, the above F
Like the ET drive circuit 300, the photocoupler 55 is employed as a switch that switches off / on in response to a FET ON / OFF signal. The photocoupler 55 includes a diode 55a that emits light in response to an ON signal, and a P-channel phototransistor 55b that is turned off when the diode 55a emits light and turned on when turned off. Note that a P-channel type switching transistor, a relay switch, or the like may be used as long as it switches off / on in response to the FET ON / OFF signal.

The operation of the FET drive circuit 400 having the above configuration is the same as that of the FET drive circuit 200 according to the second embodiment except that the FET drive circuit 400 operates with the negative power supply voltage _-Vcc1 , and therefore, further description will be omitted. .

[0038]

The first FET driving circuit according to the present invention utilizes the well-known three-terminal regulator circuit, thereby achieving the first FET driving circuit.
Regardless of the value of the power supply voltage, a constant voltage higher than the power supply voltage by a predetermined potential can be applied to the gate electrode of the driving FET.

The second FET drive circuit of the present invention is the above-mentioned first FET drive circuit, and employs a variable three-terminal regulator circuit to adjust the amount of potential higher than the first power supply voltage. Can be. Thus, a predetermined constant voltage can be applied to the gate electrode of the FET irrespective of the value of the first power supply voltage.

The third FET driving circuit of the present invention can generate a constant voltage higher than the first power supply voltage by a predetermined potential by providing the sink circuit with the resistor R. Thus, a constant voltage higher than the first power supply voltage by a predetermined potential can be applied to the gate electrode of the driving FET regardless of the value of the first power supply voltage.

The fourth FET drive circuit of the present invention can generate a constant voltage higher than the first power supply voltage by a predetermined amount by providing an operational amplifier that is negatively fed back as a sink circuit. Thus, a constant voltage higher than the power supply voltage by a predetermined potential can be applied to the gate electrode of the driving FET regardless of the value of the first power supply voltage.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an FET drive circuit according to a first embodiment.

FIG. 2 is a circuit diagram of a three-terminal regulator circuit IC and a variable three-terminal regulator circuit using the IC.

FIG. 3 is a circuit diagram of an FET drive circuit according to a second embodiment.

FIG. 4 is a circuit diagram of an FET drive circuit according to a third embodiment.

FIG. 5 is a circuit diagram of an FET drive circuit according to a fourth embodiment.

FIG. 6 is a graph showing the relationship between the drain-source on-resistance _RDS and the drain current _ID, which changes according to the voltage applied to the gate electrode of the FET.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 2nd power supply voltage supply terminal, 2 variable type 3 terminal regulator circuit IC, 1st power supply voltage supply terminal, 4
FET, 5 switching transistor, 6 load, 1
0 circuit resistance, 11 wiring capacity, 21 operational amplifier, 2
2 transistors, 23 power supplies, A1, A1 '3-terminal regulator circuit, C1, C2 sink circuit, R1, R
3, R4 fixed resistance, R2 variable resistance.

Continuation of front page (72) Inventor Kenichi Yamada 1-3-6 Nakamagome, Ota-ku, Tokyo F-term in Ricoh Co., Ltd. 5H430 BB01 BB09 BB11 BB20 EE06 EE12 GG01 5J056 AA05 BB01 BB18 CC00 CC03 CC09 CC10 CC29 DD13 DD35 DD37 DD38 DD51 DD55 DD58 EE07 KK03

Claims (4)

[Claims] A supply terminal for a first power supply voltage Vcc1, a supply terminal for a second power supply voltage Vcc2 having the same sign as the first power supply voltage Vcc1, and having an absolute value higher than the first power supply voltage Vcc1; Input terminal Vin, ground terminal GND, and constant voltage Vcc
3, the voltage input terminal Vin is connected to the supply terminal of the second power supply voltage Vcc2, and the ground terminal G
A three-terminal regulator circuit whose ND is connected to the supply terminal of the first power supply voltage Vcc1, and the predetermined potential difference ΔV is formed between the output terminal Vout of the three-terminal regulator circuit and the supply terminal of the first power supply voltage Vcc1 A sink circuit for flowing a constant current from the ground terminal GND of the three-terminal regulator circuit to the supply terminal of the first power supply voltage Vcc1. The first power supply voltage V is applied to the drain electrode of the FET to be driven.
An FET drive circuit, wherein a supply terminal of cc1 is connected, and an output terminal Vout of a constant voltage Vcc3 (= Vcc1 + ΔV) of the three-terminal regulator circuit is connected to a gate electrode. 2. The FET drive circuit according to claim 1, wherein the three-terminal regulator circuit is a variable type. 3. The FET drive circuit according to claim 1, wherein the sink circuit is a resistor having one end connected to a supply terminal of the first power supply voltage Vcc1, and the other end grounded. A certain FET
Drive circuit. 4. The FET drive circuit according to claim 1, wherein said sink circuit has a ground terminal GND of a three-terminal regulator circuit connected to a negative phase input terminal, and a first power supply voltage Vcc1.
The FET drive circuit, which is an operational amplifier to which a supply terminal of the operational amplifier is connected to the positive phase input terminal and negative feedback is applied.