JP2002251160A - Display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a display device in which the reliability in connection among a power source circuit and driving circuits is enhanced and whose power consumption is reduced remarkably. SOLUTION: This display device 11 is provided with a liquid crystal display part 20 in which a unit pixel 45 having a pixel switching element Tr and a pixel electrode M is arranged in a matrix shape, a scanning-side driving circuit 21, a signal-side driving circuit 22, a driving circuit 23 for applying a compensation voltage and a power source circuit 24. The pixel switching elements Trs are thin film transistors winch are constituted of poly crystalline silicon semiconductors which are formed on a substrate 28 and the power source circuit 24 is the power source circuit of a charge pump system and moreover is constituted of the poly crystalline silicon semiconductors and is a built-in circuit which is integrally formed on the substrate 28.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device which can be suitably applied to a display section of a portable telephone.

[0002]

2. Description of the Related Art A liquid crystal display device is characterized in that it is thin, lightweight and consumes low power. Therefore, in recent years, it has been widely used for liquid crystal displays for laptop personal computers and notebook personal computers, and also for information display sections of portable information terminals such as mobile phones. Such a conventional liquid crystal display device is configured such that an external power supply circuit supplies a necessary power supply voltage to a drive circuit in the liquid crystal display panel. More specifically, as shown in FIG. 21, the conventional power supply circuit sets a reference voltage to a high voltage by a booster circuit 140 including a transformer, and includes a plurality of resistors (voltage dividing resistors) connected in series with the high voltage. A plurality of driving voltages V1 to V3 for driving the liquid crystal display element through the voltage follower 142 from each of the voltage dividing points by the voltage dividing circuit 141.
(For example, V3 = 15, V2 = 5, V = −3).

[0003]

Therefore, the above-mentioned prior art has the following problems. Since the conversion efficiency of the booster circuit including the transformer is poor, there is a problem that power consumption in this portion increases. Further, in order to obtain a plurality of desired driving voltages by dividing the boosted high voltage by a plurality of voltage dividing resistors connected in series,
This was essentially accompanied by wasteful power consumption by the voltage dividing resistor. Further, since the power supply circuit is an external circuit, the reliability in connection with the drive circuit of the liquid crystal display panel is poor.

[0004] An object of the present invention is to solve the above-mentioned problems, improve the reliability of connection between a power supply circuit and a drive circuit, and
An object of the present invention is to provide a display device in which power consumption is significantly reduced.

[0005]

In order to solve the above-mentioned problems, the invention according to claim 1 of the present invention provides a display unit in which unit pixels each having a pixel switching element and a pixel electrode are arranged in a matrix. A scanning-side driving circuit for supplying a scanning signal to a scanning line; a signal-side driving circuit for supplying an image signal to a signal line; a reference power supply voltage input; A power supply circuit for generating a drive power supply voltage for supplying the drive power supply voltage to the scan-side drive circuit and the signal-side drive circuit;
Wherein the pixel switching element is a thin film transistor formed of a polycrystalline silicon semiconductor formed on an insulating substrate, the power supply circuit is a power supply circuit of a charge pump system, further, this power supply circuit, It is a built-in circuit formed of a polycrystalline silicon semiconductor and integrally formed on the insulating substrate.

As described above, the use of the charge pump type power supply circuit eliminates the need for a voltage dividing circuit as in the conventional example, thereby reducing power loss in the voltage dividing circuit and the like.
A low power consumption liquid crystal display device including a power supply circuit with excellent voltage conversion efficiency can be realized. In addition, since the power supply circuit is formed integrally on the insulating substrate, connection failure that occurs in the external power supply circuit is eliminated, and the reliability is improved. Further, the manufacturing cost can be reduced.

According to a second aspect of the present invention, in the display device according to the first aspect, the display unit is a liquid crystal display unit.

According to a third aspect of the present invention, in the display device according to the first aspect, the display unit is an EL display unit that performs display by emitting light from an EL element. In addition to the pixel switching element and the pixel electrode, the pixel switching element has a current control element for controlling the amount of current to the EL element, the current control element is formed of a polycrystalline silicon semiconductor formed on the insulating substrate A thin film transistor.

According to a fourth aspect of the present invention, in the display device according to the second aspect, each of the unit pixels includes a voltage control capacitor having one electrode connected to the pixel electrode and the other of the voltage control capacitor. And a voltage control capacitor line connected to the electrode of the pixel for supplying a compensation voltage signal, wherein the voltage control capacitor line changes the potential of the compensation voltage signal after completion of writing to the pixel to change the potential of the pixel electrode. The power supply circuit is connected to a compensation voltage application drive circuit to be modulated, and the power supply circuit supplies a drive power supply to the compensation voltage application drive circuit in addition to a drive power supply voltage of the scan side drive circuit and the signal side drive circuit. It is characterized in that a voltage is also generated.

According to the above configuration, a liquid crystal display device which performs display by an independent capacitive coupling driving method based on a digital image signal is realized. By using the independent capacitive coupling drive method as the drive method, it is possible to reduce power consumption.

According to a fifth aspect of the present invention, in the display device according to the fourth aspect, when the capacitance value of the voltage control capacitance is Cs, Cs satisfies the following first formula. Cs = (Vbias / Vepp) · Ctot (1) where Vbias is a change in pixel voltage due to a change in compensation voltage,
Vepp is the voltage amplitude of the compensation voltage signal, and Ctot is the sum of the voltage control capacitance, the parasitic capacitance, and the liquid crystal capacitance.

If Cs is set so as to satisfy the above-described first equation, it is possible to optimally drive the liquid crystal with the minimum voltage amplitude. Therefore, power consumption can be further reduced.

The invention according to claim 6 is the display device according to claim 5, wherein the voltage amplitude Vepp of the compensation voltage signal is provided.
Is n times the reference power supply voltage input to the power supply circuit (n times
Is a natural number), where n is 1 ≦ n ≦ 4
Is set in the range.

With the above configuration, it is possible to realize a liquid crystal display device having a high aperture ratio while suppressing an increase in leakage current.

According to a seventh aspect of the present invention, in the display device according to the sixth aspect, the voltage amplitude of the scanning signal is set to m times (m is a natural number) of the reference power supply voltage. Is characterized in that the voltage amplitude of the scanning signal is set to a value that becomes the minimum voltage value within a voltage range in which an image signal can be written to the unit pixel.

According to the above configuration, the pixel switching element can be turned on, an image signal can be written, and the scanning signal can be set to the minimum voltage amplitude. As a result, the liquid crystal can be driven sufficiently and the power consumption can be reduced.

The invention according to claim 8 is a display unit in which unit pixels are arranged in a matrix, a scanning drive circuit for supplying a scan signal to a scan line, and a signal drive for supplying a digital image signal to a signal line. Circuit and a reference power supply voltage, and generates a drive power supply voltage for the scanning side drive circuit and the signal side drive circuit from the reference power supply voltage. The drive power supply voltage is used for the scan side drive circuit and the signal side drive circuit. A power supply circuit for supplying power to a circuit, wherein the unit pixel is divided into a plurality of sub-pixels, and each sub-pixel is individually formed of a sub-pixel electrode and a polycrystalline silicon semiconductor formed on an insulating substrate. And a sub-pixel switching element composed of a thin film transistor, wherein the power supply circuit is a charge pump type power supply circuit, and the power supply circuit is formed of a polycrystalline silicon semiconductor. Characterized in that it is a built-in circuit that is integrally formed on said insulating substrate.

With the above configuration, a display device that performs gradation display based on a digital image signal is realized.

According to a ninth aspect of the present invention, in the display device of the eighth aspect, the display unit is a liquid crystal display unit.

According to a tenth aspect of the present invention, in the display device according to the eighth aspect, the display unit is an EL display unit that performs display by emitting light from an EL element. In addition to the sub-pixel switching element and the sub-pixel electrode, the semiconductor device includes a current control element for controlling an amount of current to the EL element, and the current control element is a polycrystalline silicon semiconductor formed on the insulating substrate. It is a thin film transistor configured.

According to an eleventh aspect of the present invention, in the display device of the eighth aspect, the area of the sub-pixel electrode in the unit pixel is formed to have a size corresponding to the weight of the digital image signal. It is characterized by being.

According to the above configuration, it is possible to perform gradation display with improved display quality.

According to a twelfth aspect of the present invention, in the display device according to the eighth aspect, the scanning line is wired for each sub-pixel,
The signal line has a wiring structure commonly wired to all the sub-pixels.

As a wiring structure of the sub-pixel, a wiring structure in which a signal line is wired for each sub-pixel and a scanning line is commonly wired to all the sub-pixels can be considered. However, when such a wiring structure is applied to the wiring structure of the R, G, and B sub-pixels in a full-color display device, the number of connection lines increases, and the number of connection pins increases. This may lead to an increase in the number of connection failures, and further to a decrease in image quality such as display defects. In this regard, with the wiring structure of the present invention, even if the present invention is applied to the R, G, and B sub-pixels in the display device for full-color display, the number of connected wirings does not increase so much, and thus the above problem can be solved. It becomes possible.

According to a thirteenth aspect of the present invention, in the display device of the ninth aspect, each of the sub-pixels includes a voltage control capacitor having one electrode connected to the sub-pixel electrode, A voltage control capacitor line connected to the other electrode to supply a compensation voltage signal, wherein the voltage control capacitor line changes the potential of the compensation voltage signal after the end of writing to the sub-pixel to change the potential of the sub-pixel electrode. The power supply circuit is connected to a compensation voltage application drive circuit for modulating a potential, and the power supply circuit supplies a drive voltage to the compensation voltage application drive circuit in addition to a drive power supply voltage for the scan side drive circuit and the signal side drive circuit. It is also characterized by generating a power supply voltage for use.

With the above configuration, a liquid crystal display device that performs gradation display by an independent capacitive coupling drive method based on a digital image signal is realized. By using the independent capacitive coupling drive method as the drive method, it is possible to reduce power consumption.

According to a fourteenth aspect of the present invention, in the display device according to the thirteenth aspect, the area of the sub-pixel electrode in the unit pixel is formed to have a size corresponding to the weight of the digital image signal. It is characterized by being.

According to the above configuration, it is possible to perform gradation display with improved display quality.

According to a fifteenth aspect of the present invention, in the display device according to the thirteenth aspect, each of the sub-pixel switching elements in the unit pixel has an ON current capability of a size corresponding to the weight of the digital image signal. It is characterized by having been done.

According to the above configuration, the pixel transistor can obtain an ON current capability corresponding to the size of the electrode of the sub-pixel, and can sufficiently write an image signal. The ON current capability of the pixel transistor is set as follows.
The channel width may be changed, the channel length may be changed, or both the channel width and the channel length may be changed.

According to a sixteenth aspect of the present invention, in the display device of the thirteenth aspect, each of the voltage control capacitors in the unit pixel has a capacitance value corresponding to a weight of the digital image signal. It is characterized by being formed in.

According to the above configuration, the fluctuation of the electrode potential of each sub-pixel can be reduced as much as possible, and the display quality can be improved.

According to a seventeenth aspect of the present invention, in the display device of the thirteenth aspect, a storage capacitor is formed between a preceding scanning line among the scanning lines and the pixel electrode. And

With the above configuration, a required load capacitance can be obtained for each of the plurality of sub-pixels. Therefore, the holding characteristics of each sub-pixel are improved, and a decrease in image quality can be prevented.

According to an eighteenth aspect of the present invention, in the display device according to the first aspect, the scanning side driving circuit and the signal side driving circuit are made of a polycrystalline silicon semiconductor, and are integrated on the insulating substrate. It is characterized in that it is a built-in circuit that is formed in an integrated manner.

By using all of the peripheral driving circuits as built-in driving circuits, power consumption can be significantly reduced, and the entire display device can be reduced in weight and thickness.

According to a nineteenth aspect of the present invention, in the display device according to the first aspect, the signal side driving circuit is formed of a single crystal silicon semiconductor, and the scanning side driving circuit is formed of a polycrystalline silicon semiconductor, It is a built-in circuit integrally formed on the insulating substrate.

According to the above configuration, the film thickness of the transistor can be increased and the capacitance can be reduced, and the power consumption of the signal side drive circuit can be reduced, as compared with the case where the signal side drive circuit is a built-in circuit formed of a polycrystalline silicon semiconductor. can do.

According to a twentieth aspect of the present invention, in the display device according to the fourth aspect, the scan side drive circuit, the signal side drive circuit, and the drive circuit for applying a compensation voltage are made of a polycrystalline silicon semiconductor, It is a built-in circuit integrally formed on the insulating substrate.

By using all of the peripheral driving circuits as built-in driving circuits, power consumption can be significantly reduced, and the entire display device can be reduced in weight and thickness.

According to a twenty-first aspect of the present invention, there is provided the display device according to the first aspect, further comprising a level shifter circuit for supplying a control signal to the scanning side driving circuit and the signal side driving circuit. It is a built-in circuit formed of a polycrystalline silicon semiconductor and integrally formed on the insulating substrate.

With the above configuration, the weight and thickness of the entire display device can be further reduced.

[0043]

(Embodiment 1) FIG. 1 is a block diagram showing an electric configuration of a mobile phone 1 provided with a liquid crystal display device according to the present invention. In FIG. 1, reference numeral 2 denotes a CPU (Central Processing Unit) that controls the operation of each section of the mobile phone by executing a telephone function program. A communication unit 3 is connected to the antenna 4 and has a function of modulating a transmission signal and a function of demodulating a reception signal. 5 is a random access memory (RAM), which is
For example, it is a memory for storing user setting data. 6
Is a read only memory (ROM).
In advance, various transmission and reception telephone function programs executed by the CPU 2 are stored in advance. Reference numeral 7 denotes an audio processing unit. The audio processing unit 7 decodes the received signal demodulated by the communication unit 3 and outputs audio through a speaker 8. Is compression-encoded and can be transmitted through the communication unit 3 under the control of the CPU 2. Reference numeral 10 denotes an operation unit including numeric keys and function keys. Reference numeral 11 denotes a liquid crystal display device, which displays menus for telephone functions and displays according to operations of ten keys and function keys.

Reference numeral 12 denotes a battery.
Is supplied to a power supply circuit 13 to generate a driving voltage required for each part of the mobile phone (excluding the liquid crystal display device 11) and supply it to each part of the mobile phone.

As will be described later, the liquid crystal display device 11 has a battery 12 directly connected thereto and generates a drive voltage required for a drive circuit in the liquid crystal display device 11 by a power supply circuit in the liquid crystal display device 11. It is configured to supply.

FIG. 2 is a circuit diagram of the liquid crystal display device 11.
The liquid crystal display device 11 is an active matrix type liquid crystal display device employing a capacitive coupling drive system. The liquid crystal display device 11 includes a liquid crystal display unit 20, a scanning side driving circuit 21 for supplying a scanning signal to the scanning line SL, a signal side driving circuit 22 for supplying an image signal to the signal line GL, and a signal wiring for applying a compensation voltage. 26, a compensating voltage application driving circuit 23 for supplying a compensating voltage, a power supply circuit 24 for supplying a driving power supply voltage to each of the driving circuits 21, 22, 23, and a low-amplitude control signal supplied from the outside. Each of the driving circuits 21, 22 and 23 is converted into a high-amplitude control signal usable by the circuits 21, 22 and 23.
And a level shifter 25 circuit for supplying the level shifter 23 to the circuit. The liquid crystal display unit 20 includes a plurality of scanning lines GL and a plurality of signal lines S arranged in a matrix, and unit pixels 45 arranged in a matrix. The unit pixel 45 includes a pixel electrode M,
A pixel switching element Tr connected to the pixel electrode M;
A voltage control capacitor Cs for performing capacitive coupling driving. One electrode of the voltage control capacitor Cs is connected to the pixel electrode M, and the other electrode is connected to the compensation voltage application signal line 26. The pixel switching element Tr is a thin film transistor (TF) made of a polycrystalline silicon semiconductor.
T).

In the scanning side drive circuit 21, reference numeral 21a denotes a transfer clock input terminal, 21b denotes a start pulse input terminal, and 21c denotes a shift register. Further, in the compensation voltage applying drive circuit 23, 23a is a transfer clock input terminal, 23b is a start pulse input terminal, and 23c is a shift register. In the signal side driving circuit 22, reference numeral 22a denotes a transfer clock input terminal, 22b denotes a start pulse input terminal, 22c denotes a shift register, 22d denotes an image signal input terminal, and 22e denotes a transfer gate element.

Vc is the potential of the counter electrode formed on the counter substrate, 28 is the active substrate made of glass, 27
Is a liquid crystal layer held between the active substrate 28 and the counter substrate.

In the first embodiment, the power supply circuit 2
4. Scanning side drive circuit 21, Compensation voltage application drive circuit 2
3. Signal side drive circuit 22 and level shifter circuit 25
Are all composed of polycrystalline silicon semiconductors,
This is a built-in circuit integrally formed on the active substrate 28 at the same time as the manufacturing process of the pixel switching element Tr.

FIG. 3 shows a driving waveform diagram in the method of driving the liquid crystal display device. In FIG. 3, Vg1 and Vg2 are first and second scanning signals, Vs is an image signal, Vd is a pixel electrode potential, and Vc is a counter electrode potential. Scan signal Vg
1 includes a potential (Vgt) for turning on the switching element 4 and a potential (Vgb) for turning off. Further, the compensation voltage signal Vg2 is a binary bias potential (Ve (+), Ve (+)
(-)). In this capacitive coupling driving method, the counter electrode is fixed, and the potential ΔV due to the penetration voltage is compensated by adding an offset to the source electrode.
Further, by using the capacitive coupling driving method, the image signal voltage can be reduced, and the power consumption of the signal side driving circuit 22 can be reduced.

The pixel switching element T of the liquid crystal display unit 20
r turns on only during a period when the scanning signal Vg1 applied to the scanning line GL from the scanning side drive circuit 21 is at the on-potential (Vgt). At this time, the image signal Vs transmitted from the signal side driving circuit 22 to the signal line SL is applied to the pixel electrode M via the on-state switching element Tr. When the scanning signal Vg1 changes to the off potential (Vgb) and the switching element Tr is turned off, the pixel electrode potential Vd is held by the liquid crystal capacitor and the voltage control capacitor Cs, but the voltage control capacitor Cs and the compensation voltage application signal are applied. The shift is performed in accordance with the potential of the compensation voltage signal Vg2 supplied from the compensation voltage applying drive circuit 23 via the wiring 26. When the drawing of one screen is completed and the next frame is formed, the polarity of the image signal Vs is inverted with respect to the center potential Vsc, and the same operation is repeated. In this manner, display by the capacitive coupling driving method is performed.

It should be noted here that each of the drive circuits 21, 22, and 23 in the present embodiment has a drive voltage that is an integral multiple of the reference power supply voltage VDD. That is, the power supply circuit 24 is constituted by a charge pump type power supply circuit, converts the reference power supply voltage VDD into a drive power supply voltage that is an integral multiple of VDD and drives each of the drive circuits 21, 22.
The power supply 23 is configured to supply a drive power supply.

FIG. 4 shows a charge pump type power supply circuit 24.
FIG. 5 is a diagram for explaining the principle of the charge pump operation of the power supply circuit. In the first embodiment, the power supply circuit 24 generates three types of drive voltages V1, V2, and V3 from the reference power supply voltage VDD. The power supply circuit 24 has three charge pump circuits CP1, CP2 and CP3 as shown in FIG. The charge pump circuit CP1 is a circuit that boosts the reference voltage Vin by a factor of two, the charge pump circuit CP2 is a circuit that boosts the reference voltage Vin by a factor of six, and the charge pump circuit CP3 is a circuit that boosts the reference voltage Vin by a factor of -2. is there. Then, the drive voltage V1 doubled by the charge pump circuit CP1
Is supplied to the signal side drive circuit 22. The drive voltage V2 boosted six times by the charge pump circuit CP2 is supplied to the scan side drive circuit 21 and the compensation voltage application drive circuit 23. The charge pump circuit CP3 provides -2
The doubled drive voltage V3 is supplied to the scan side drive circuit 21 and the compensation voltage application drive circuit 23.

Here, the boosting principle of the charge pump circuit will be briefly described with reference to FIG. Note that a description will be given taking triple boosting as an example. First, the switches SW1 and SW
When the switch 3 is ON and the switch SW2 is turned OFF, the reference voltage Vin is applied to the capacitor C1, and the capacitor C1 is charged until the voltage between its terminals becomes VDD. Then
When the switches SW2, SW4 and SW6 are ON, the switch S
When W1, SW3 and SW5 are turned off, the capacitor C
2, the sum 2VDD of the charging voltage VDD of the capacitor C1 and the reference voltage VDD is applied, and the capacitor C2 is charged until the voltage between its terminals becomes 2VDD. Then, switch SW
1, SW5 and SW7 are ON and switches SW2 and SW
3, SW4 and SW6 are turned off, the capacitor C3
Is applied to the capacitor C2, the sum of 3VDD of the charging voltage 2VDD and the reference voltage VDD, and the capacitor C3 is charged until the voltage between its terminals becomes 3VDD. Therefore, the capacitor C
If the voltage between the three terminals is used as the output voltage, a voltage three times as high as the reference voltage can be output. Based on such a principle, the charge pump circuit CP1 boosts the reference voltage VDD twice, and the charge pump circuit CP2 boosts the reference voltage VDD six times.

In this embodiment, the reference voltage VDD =
1.8V, V1 = 3.6V, V2 = 10.8V, V
3 = −3.6V.

The use of such a charge pump type power supply circuit 24 eliminates the need for a voltage divider circuit as in the prior art, thereby reducing power loss in the voltage divider circuit and the like and providing a power supply with excellent voltage conversion efficiency. It is possible to realize a low power consumption liquid crystal display device including a circuit. In addition, by forming the power supply circuit 24 integrally with the substrate 28 as described above, a connection failure that occurs in an external power supply circuit is eliminated, reliability is improved, and manufacturing costs can be reduced. Further, by using such a power supply circuit 24, in an active matrix type liquid crystal display device employing a capacitive coupling driving method, the value of the voltage control capacitance can be optimized and the voltage amplitude of the scanning signal can be used to drive the liquid crystal. With the minimum voltage amplitude within the range, power consumption can be further reduced.

Hereinafter, a specific description will be given. (1) Optimization of voltage control capacitance In the liquid crystal display device according to the present embodiment, the voltage control capacitance Cs is determined by the following first equation. Cs = (Vbias / Vepp) · (Ctot) (1) where Vepp is the voltage amplitude of the compensation voltage, Vbias is the change in the pixel voltage due to the change in the compensation voltage, and Ctot is the liquid crystal capacitance Clc.
And the parasitic capacitance Cgd of the transistor and the voltage control capacitance Cs.

Since the power supply of the compensation voltage applying circuit 23 is an integral multiple of the reference power supply voltage VDD, the voltage amplitude Vepp of the compensation voltage (see FIG. 6) is equal to the reference power supply voltage VDD.
N, that is, Vepp = n.VDD (where n is a natural number). Therefore, the first equation can be expressed by the following equation. Cs = (Vbias / VDD) · (Ctot) · (1 / n) (2) Here, in the present embodiment, n is set in the range of 1 ≦ n ≦ 4. As a result, a liquid crystal display device having a high aperture ratio, suppressing an increase in leak current, and improving display characteristics can be configured. Hereinafter, the reason will be described in detail.

First, the introduction of the first formula will be described. When driving the liquid crystal, Vbias is in the range shown in FIG. 6 in consideration of the minimum voltage amplitude Vspp of the liquid crystal. And, in the capacitive coupling driving method as in the present invention, the compensation voltage V
By applying epp from one electrode of the voltage control capacitor, the amplitude required for the signal line can be set to be the same as the amplitude voltage (Vspp) of the liquid crystal. Therefore, Vbias is equal to Vbias
= (Cs / Ctot) · Vepp. By transforming this equation, the first equation is derived. If Cs is set so as to satisfy the second expression derived from the first expression, the liquid crystal can be optimally driven.

However, if n is an arbitrary value under the condition of the second equation, that is, if Cs is an arbitrary value, the following problem occurs. That is, when Cs is set to an arbitrary value (corresponding to setting n to an arbitrary value), Vbias shifts to the left and right.
Therefore, white is not displayed. Conversely, if you shift to the left, black will not sink sufficiently.
That is, an optimum contrast cannot be obtained. Of course, FIG. 7 shows the case of the normally white mode. In the case of the normally black mode, a phenomenon opposite to the above occurs according to the left and right shift of Vbias. On the other hand, if the amplitude is increased,
Although such a problem can be solved, power consumption increases. Therefore, the present invention satisfies the above-described second formula and obtains n in a range of 1 ≦ n ≦ 4 in order to obtain sufficient contrast with the minimum power consumption and the small amplitude. is there.

The following effects are also exerted by the regulation of n. That is, when n is large, Cs
Is small, and thus the leakage current increases. On the other hand, n
Is smaller, Cs becomes larger, and therefore the aperture ratio becomes smaller due to an increase in the area of the electrode for the voltage control capacitor. Therefore,
By setting the range of 1 ≦ n ≦ 4, it is possible to suppress an increase in leakage current and to realize a liquid crystal display device having a high aperture ratio.

(2) Optimization of Scanning Signal Voltage Amplitude Vgpp Since the power supply of the scanning side driving circuit 21 is an integral multiple of the reference power supply voltage VDD, the voltage amplitude Vgpp of the scanning signal is m of the reference power supply voltage VDD. Times, ie, Vgpp = m · VDD (however,
m is a natural number). And m is the voltage amplitude V
gpp is set to a value such that it becomes the minimum voltage value within a voltage range in which an image signal can be written to a unit pixel. As a result, the voltage amplitude Vgpp can be reduced, and power consumption can be reduced. For example, when VDD = 1.8 (V), Vepp = n · VDD = 2 × 1.8, and Vgpp = m ·
VDD = 7 × 1.8.

The operation will be described below with reference to FIG. In FIG. 8, Von is an on-margin, Voff is an off-margin, Vth is a threshold voltage of a TFT, Vspp is a minimum amplitude of the liquid crystal, Vlc is an ON voltage of the liquid crystal, and Voffse.
t indicates an offset voltage (difference between a video signal center and a counter voltage), Vsc indicates a signal center, and Vgpp indicates a scanning signal amplitude. For example, when m = 6, the voltage becomes equal to or lower than the threshold voltage Vth, and the liquid crystal display cannot be turned on. On the other hand, m =
In the case of 8, the liquid crystal display can be turned on, but this is not appropriate from the viewpoint of power consumption. It is understood that m = 7 is required to drive the liquid crystal with the minimum voltage amplitude. In this manner, since the voltage amplitude Vgpp of the scanning signal can be driven with the minimum amplitude,
Power consumption can be reduced.

As described above, in the present invention, in the liquid crystal display device of the capacitive coupling drive system, the voltage control capacitance is optimized, and the voltage amplitude Vepp of the compensation voltage and the voltage amplitude Vgpp of the scanning signal are optimized. The liquid crystal can be driven with the minimum voltage amplitude while maintaining the display quality, and the power consumption can be significantly reduced.

The image data input to the liquid crystal display device may be an analog signal or a digital signal. When the input image data is a digital signal, a signal side drive circuit 22 having a digital / analog conversion circuit may be used.

When a digital / analog conversion circuit is not used, one frame is composed of a plurality of sub-frames consisting of a writing period and a holding period, and a PWM (Pulse Width Modulation) for performing gradation display by the cumulative effect of the holding period. )
Driving method (for example, refer to JP-A-5-107561)
Is used, a digital signal can be supplied to the signal line SL as it is to perform digital driving.

(Embodiment 2) FIG. 9 is a circuit diagram of a liquid crystal display device according to Embodiment 2, and FIG. 10 is a circuit diagram showing a configuration of a unit pixel. The liquid crystal display device according to the second embodiment is similar to the above-described first embodiment, and corresponding portions are denoted by the same reference numerals. The second embodiment is characterized in that an area gradation display method is used. Note that the digital image signal used in the second embodiment has a 4-bit data configuration, and shows an active matrix liquid crystal display device capable of displaying 16 gradations.

The liquid crystal display device according to the second embodiment has
In order to adopt the area gradation display method, the unit pixel 45 includes a plurality of (four in the first embodiment) sub-pixels P1, P2, P
3, P4. The sub-pixel P1 includes a sub-pixel electrode M1 and a thin film transistor (TFT).
The sub-pixel transistor Tr1 includes a voltage control capacitor C1 for performing capacitive coupling driving. Similarly to the sub-pixel P1, the other sub-pixels P2 to P4 also have the sub-pixel electrodes M2 to M4 and the sub-pixel transistor Tr2.
To Tr4 and voltage control capacitors C2 to C4.

In the second embodiment, the sub-pixels M1 to M
The electrode area ratio of No. 4 is formed in a size corresponding to the weight of the digital image data. That is, the sub-pixel electrode M1
Area: area of sub-pixel electrode M2: area of sub-pixel electrode M3: area of sub-pixel electrode M4 = 1: 2: 4: 8. Then, the first bit data of the 4-bit image data corresponds to the sub-pixel P1, the second bit data corresponds to the sub-pixel P2, the third bit data corresponds to the sub-pixel P3, The fourth bit data corresponds to the sub-pixel P4. Since such a sub-pixel electrode has a size corresponding to the weighting of the digital signal, it is possible to display 16 gradations according to the digital image data. In addition,
The electrode area of the sub-pixel electrode is the area of a portion that effectively contributes to the modulation of light. For example, in the case of a transmission type, it means the effective area of the electrode area excluding the area of the portion covered with the light shield. I do.

Each unit pixel 45 has a wiring structure in which the scanning line GL is individually wired for each sub-pixel, and the signal line SL is commonly wired to all the sub-pixels. In addition,
The wiring structure of the sub-pixel is not limited to the above-described wiring structure, but may be a wiring structure in which the signal line SL is wired for each sub-pixel and the scanning line GL is commonly wired to all the sub-pixels. However,
When such a wiring structure is applied to a wiring structure of R, G, and B sub-pixels in a full-color display liquid crystal display device, the number of connection lines increases, resulting in a dramatic increase in the number of connection pins. There is a possibility that an increase in connection failure and further a decrease in image quality such as a display defect may occur. In this regard, in the case of the wiring structure according to the present embodiment, even when applied to the wiring structure of the R, G, and B sub-pixels in the liquid crystal display device for full-color display, the number of connected wires does not increase so much. The problem can be solved.

In the liquid crystal display device according to the second embodiment, the capacitive coupling driving method (constant counter electrode potential) is used as in the first embodiment. Explaining a specific configuration, the voltage control capacitance wiring 26 is wired for each unit pixel 45, and the respective voltage control capacitances C1 to C4 are connected via a common connection line 30 connected to the voltage control capacitance wiring 26.
Are connected to the voltage control capacitor wiring 26, respectively. Thus, it is possible to prevent a decrease in display quality due to the penetration voltage. Also,
By providing such an independent voltage control capacitor wiring 26, the voltage of the scanning side drive circuit 21 can be reduced as compared with a configuration in which a scanning signal and a compensation voltage are superimposed on a scanning line (for example, Japanese Patent Application Laid-Open No. 2-157815). Becomes possible.

As will be described later, as shown in FIG. 14, the compensation voltage applying drive circuit 23 changes the compensation voltage signal after the completion of the writing of all the sub-pixels constituting the unit pixel, as shown in FIG. The pixel electrode potential is modulated at a time. Thereby, for example, the voltage control capacitor wiring 26 is wired for each sub-pixel and the voltage control capacitor C
Compared with a structure in which 1 to C4 are individually connected to the voltage control capacitance wiring 26, the number of wirings of the voltage control capacitance wiring 26 can be reduced, so that an aperture ratio can be improved and drive control can be simplified. it can. In addition, one horizontal scanning frequency (here, one horizontal scanning means that in the capacitive coupling driving method of this embodiment, the compensation voltage is changed after the writing of the subpixel is completed to modulate the potential of the subpixel electrode. ) Is reduced, and power consumption can be reduced. Further, in the driving method using the capacitive coupling method as in the present embodiment, inversion driving is performed for each sub-pixel (equivalent to 1H inversion driving when one sub-pixel is regarded as one ordinary pixel). ), The gradation characteristic (γ characteristic) is not linear due to the capacitive coupling, and becomes uneven and non-linear. Therefore, display quality is deteriorated. In this regard, as in the present embodiment, the inversion drive (1
If one sub-pixel is regarded as one normal pixel, it corresponds to 4H inversion driving), so that the linearity of the γ characteristic can be improved and the display quality can be improved.

Instead of the compensation voltage applying drive circuit 23, the scan side drive circuit 21 may be provided with a compensation voltage applying function, and the scanning side drive circuit 21 may be connected to the voltage control capacitor wiring 26. By doing so, the circuit area can be reduced by the compensation voltage application drive circuit 23.

Here, the area ratio of the sub-pixel electrodes is 1: 2:
Since the ratio is set to 4: 8, the voltage control capacitance is also configured to have a capacitance value corresponding thereto. That is, the value of the voltage control capacitor C1: the value of the voltage control capacitor C2: the value of the voltage control capacitor C3: the value of the voltage control capacitor C4 = 1: 2: 4: 8. As a result, fluctuations in the pixel electrode potential can be suppressed to a small level, and good image quality can be obtained.

Further, each of the sub-pixel transistors Tr1 to Tr
In No. 4, the ON current capability is set to a magnitude corresponding to the weighting of the digital image signal. Specifically, in the present embodiment, the channel width of each of the sub-pixel transistors Tr1 to Tr4 has a size corresponding to the size of the electrode of the sub-pixel, that is, a channel width ratio of 1: 2: 4: 8. ing. With such a configuration, writing can be appropriately performed.
Instead of making the channel widths of the sub-pixel transistors Tr1 to Tr4 different, the channel length may be set to have a size corresponding to the weight of the digital image signal. Alternatively, both the channel width and the channel length may be different so that the capability of the ON current is set to a value corresponding to the weight of the digital image signal.

FIG. 11 is a block circuit diagram showing a specific configuration of the signal side drive circuit. The signal-side drive circuit 22A according to the second embodiment includes a shift register 40, a first latch circuit 41 that latches a digital image signal, a second latch circuit 42 that latches an output of the first latch circuit, and, for example, EX. And a polarity inversion circuit 43 implemented by an OR. The signal-side drive circuit 22A is made of a polycrystalline silicon semiconductor, similarly to the signal-side drive circuit 22 of the first embodiment, and includes a sub-pixel transistor Tr1.
Active substrate 28 at the same time as the manufacturing process of Tr4.
This is a built-in circuit integrated into the

FIG. 12 is a diagram showing a data string of image data, FIG. 13 is a diagram schematically showing an arrangement state of sub-pixels, and FIG. 14 is a timing chart of displacement of pixel electrode potential. In FIG. 5, (i, j) indicates the ith signal line S
The sub-pixels for Li and the j-th scanning line GLj are shown. As an example, a liquid crystal panel configuration compatible with VGA (640 × 480 pixels) is shown. Of course, the area of the sub-pixel has a size corresponding to the weight of the digital signal, and FIG. 1 in which the sub-pixel is drawn as the same size.
The arrangement state of No. 3 is different from the actual arrangement state. However, for the description of the display operation, it is sufficient to specify which sub-pixel of the whole sub-pixels by the signal line SL and the scanning line GL, and therefore, the schematic diagram of FIG. 13 will be used. FIG. 14A shows the timing for the n-th pixel, and FIG. 14B shows the timing for the (n + 1) -th pixel.

First, in the image signal, the original image data shown in FIG. 12A is previously converted into an image data sequence shown in FIG. 12B by an external data conversion circuit (not shown). That is, the image data shown in FIG. 12B is supplied to the input data line of the first latch circuit 41. Figure 1
In 2 (2), the bit data d (i, j) indicates data relating to sub-pixels relating to the i-th signal line SLi and the j-th scanning line GLj. As is clear from FIGS. 12A and 12B, one pixel is 4-bit data, and the 4-bit data is distributed to one line data for every four consecutive rows. For example, the sub-pixel (1, 1), the sub-pixel (1,
2), the pixel [1,1] composed of the sub-pixel (1,3) and the sub-pixel (1,4) will be described as an example.
The bit data d (1,1) for the sub-pixel (1,2) is stored in the first line data column.
(1, 2) is a sub-pixel (1, 3) in the second line data string.
The bit data d (1,3) related to the sub-pixel (1,4) is stored in the third line data column.
4) is assigned to the fourth line data string and is the first bit data of each of the first to fourth line data strings. Such distribution of the 4-bit image data for the unit pixel is also performed for other unit pixels.

First, when the image data shown in FIG. 12B is supplied to the input data line, a latch pulse is sequentially output from the shift register 40 in synchronization with the image data. Thus, each bit data of the first line data is sequentially latched by the first latch circuit 41. After each bit data of one line data is thus latched by the first latch circuit 41, a latch pulse is supplied to all the second latch circuits 42 in common. As a result, the line data is latched by the second latch circuit 42 from the first latch circuit 41 and output to the liquid crystal display unit 20 via the signal lines SL. In synchronization with this, the first scanning line GL1 is selected.
Thereby, the first line data is written to each sub-pixel electrode connected to the first scanning line GL1. Next, by the same operation, the second line data, the third line data,
The fourth line data is written. Then, after the writing of the fourth line data is completed (that is, after the writing of the unit pixels belonging to the first row is completed), as shown in FIG. Shift to Thereby, the pixel electrode potential of the unit pixel belonging to the first row is modulated to a predetermined potential. As a result, the first
The unit pixels belonging to the row are applied with a positive polarity with respect to the counter electrode potential Vc.

At this time, if attention is paid to the pixel [1, 1], the sub-pixel (1, 1) is written by writing the first line.
Is written with bit data d (1, 1). Similarly, by writing the second to fourth lines, bit data d (1, 2) is written to the sub-pixel (1, 2),
Bit data d (1,3) is written to the sub-pixel (1,3), and bit data d (1,4) is written to the sub-pixel (1,4). Next, the bit data d (1, 1) to bit data d are shifted by shifting the compensation voltage on the high potential side.
The image is modulated and displayed on the sub-pixel electrode potential corresponding to (1, 4), and the pixel [1, 1] is displayed with a predetermined gradation.

For example, if bit data d (1, 1) =
“1”, bit data d (1, 2) = “0”, bit data d (1, 3) = “0”, bit data d (1, 4)
= “0”, only the sub-pixel (1, 1) is ON, and the sub-pixels (1, 2), (1, 3), and (1, 1)
4) is OFF. Therefore, pixel [1, 1] is 16
The image is displayed at the brightness of level 1 among the gradations.
Further, for example, bit data d (1, 1) = “1”, bit data d (1, 2) = “1”, bit data d
(1,3) = “0”, bit data d (1,4) =
In the case of “0”, the sub-pixel (1, 1) and the sub-pixel (1,
2) is ON, sub-pixel (1, 3) and sub-pixel (1, 4)
Becomes OFF. Therefore, the pixel [1, 1] is displayed with the brightness of level 3 out of 16 gradations. Although the above example describes the pixel [1, 1], the same display operation is performed for the other pixels, and the display is performed with the brightness of the predetermined gradation level. Thus, gradation display according to the video signal is performed.

Next, writing of the fifth to eighth line data, that is, writing of the unit pixels belonging to the second row is performed. The writing of the fifth to eighth line data is basically the same as the writing operation of the first to fourth line data. However, after the completion of the writing of the fifth to eighth line data (that is, after the completion of the writing of the unit pixels belonging to the second row), as shown in FIG.
6, the compensation voltage shifts to the lower potential side. Thereby, the pixel electrode potential of the unit pixel belonging to the second row is modulated to a predetermined potential. As a result, the unit pixels belonging to the second row are:
This is applied with a negative polarity with respect to the counter electrode potential Vc.

Thereafter, the same operation is performed, and 4H inversion driving in which the polarity changes every four lines is performed (in terms of unit pixels, the polarity inversion driving is performed for each unit pixel). Therefore, generation of flicker can be prevented.

In the above example, an example of 4 bits (16 gradations) has been described. However, the present invention is not limited to this, and the number of unit pixels is 5, 6, or more. It may be constituted by sub-pixels, and may perform 5-bit (32 gradation), 6-bit (64 gradation) or other multi-gradation display.

In the above example, the liquid crystal display device for displaying black and white has been described, but R (red) G (green)
The present invention is also applicable to a full-color display liquid crystal display device having B (blue) sub-pixels. When applied to a full-color display liquid crystal display device, the unit pixel 4
5.45.45 are RGB sub-pixels, and the unit pixel 45.45
One pixel is constituted by three of 45 and 45,
It is sufficient that the unit pixels arranged in the horizontal direction (the horizontal direction of the liquid crystal display panel) are respectively allocated to RGB sub-pixels.

(Embodiment 3) Embodiment 3 is characterized in that a storage capacitor is formed for each sub-pixel in addition to a voltage control capacitor. With such a configuration, it is possible to increase the load capacitance, and it is possible to improve the good holding characteristics of the pixel electrode potential. This also makes it possible to improve image quality. Hereinafter, an embodiment of the present embodiment will be specifically described with reference to FIGS. FIG. 15 is a diagram showing a configuration of a unit pixel in the liquid crystal display device according to the third embodiment, and FIG. 16 is an equivalent circuit diagram of one sub-pixel. Note that the same reference numerals are given to portions corresponding to the second embodiment, and detailed description is omitted. In the sub-pixel P1 in the liquid crystal display device according to the present embodiment, in addition to the voltage control capacitor C1, a storage capacitor 60 is formed between the sub-pixel electrode and the preceding scanning line GL.
Other sub-pixels P2 to P4 have the same configuration as sub-pixel P1. Note that the capacitance value of the storage capacitor 60 is indicated by Cs1. Further, the capacitance value of the liquid crystal capacitance 27 is represented by Clc, and the capacitance values of the voltage control capacitances C1 to C4 are represented by Cc.

The conventional structure of the additional capacitor is provided on the voltage control capacitor wiring (FIG. 17A) or between the scanning lines in the preceding stage (FIG. 17B). On the other hand, in the present embodiment, the additional capacitance is provided on both the voltage control capacitance wiring and the preceding scanning line (FIG. 17C). As a result, the value of the capacitance added to the liquid crystal can be increased, and good holding characteristics can be obtained.

In particular, in the liquid crystal display device according to the present embodiment in which a unit pixel is divided to have a plurality of sub-pixels, a sufficient capacitance value is secured only by the voltage control capacitance formed in each sub-pixel. Therefore, it is possible to secure a necessary and sufficient capacitance value by a configuration in which a storage capacitor is separately formed in addition to such a voltage control capacitor.

Next, in this embodiment, an optimum driving condition is obtained. Table 1 shows how to determine the optimum driving conditions in the present embodiment.

[Table 1]

First, desirable conditions for driving the liquid crystal panel are determined. In the present embodiment, the amplitude Vepp of the compensation signal given to the voltage control capacitor wiring is set to 3.6V. This is because the controller of the liquid crystal panel is often driven by a voltage of 1.8 V, and the other signal voltage is 1.8 V.
This is because the power supply design efficiency is more advantageous when the power supply is designed with an integral multiple of. That is, by setting Vepp to be an integer multiplication of an externally applied reference voltage represented by a controller control voltage, a highly efficient DC / DC converter represented by a charge pump can be used as a power supply circuit.
Therefore, it is possible to reduce the power consumption of the system.

Next, the value of the bias voltage applied to the liquid crystal is determined by the compensation voltage Vepp. This is determined by the voltage / transmittance characteristics of the liquid crystal, and the value is, as shown in FIG.
If it is set at the center point where the transmittance changes, the amplitude value of the required signal voltage becomes minimum. In this embodiment, this value is set to 1.5V.

Next, the value of the storage capacitor formed between the preceding scanning lines is determined. This value is determined from the signal line width of the scanning electrode. In this embodiment, since the width of the scanning electrode is set to 6 μm, the value of the storage capacitance is designed to be 0.13 pF.

Next, the value of the control capacity Cc is determined according to the following equation (3). Ccc = {(Vbias / Vepp−Vbias)} · (Clc + Cs1) (3) where Vbias is the amount of change in the pixel voltage due to the change in the compensation voltage, Vepp is the voltage amplitude of the compensation voltage signal, Clc is the liquid crystal capacitance, and Cs1 is The storage capacity. The value is obtained by substituting the value and the liquid crystal capacitance Clc determined by the size of the pixel electrode into the equation (3). Finally, the sum of Clc, Cs1, and Cc was determined, and the design was performed so that the sum of the capacitances satisfied the liquid crystal holding characteristics. In this embodiment, the total sum is designed to be 0.25 pF or more in consideration of the off-resistance of the TFT.

Table 2 shows this combination.

[Table 2]

Table 2 shows the liquid crystal capacitance Clc, the storage capacitance Cs1, the voltage control capacitance Cc, and the total sum Ctot of all the capacitances in the present embodiment.
The liquid crystal display device was manufactured so as to obtain the combination shown in FIG. As a result, all the sub-pixels can be driven with the same bias voltage, and the necessary and sufficient holding characteristics in all the sub-pixels can be secured. Note that a polycrystalline silicon thin film transistor is preferably used for a circuit element of the scanning driver circuit and the signal driver circuit of the active substrate and a pixel switching element. This makes it possible to reduce the size of the transistor in the sub-pixel and facilitate the design. In addition, it becomes easy to incorporate a drive circuit on the active substrate, which can contribute to cost reduction and miniaturization.

In the above example, although one pixel is divided into a plurality of sub-pixels and each sub-pixel satisfies the condition shown in Table 2, the above-described optimization of the value of the voltage control capacitance is performed. The method can be applied to a normal unit pixel which is not a sub-pixel configuration.

(Embodiment 4) FIG. 19 is a block diagram showing a partial configuration of a liquid crystal display device of Embodiment 4. 70
Is a voltage detection circuit 70, and 71 is a circuit for compensating the drive power supply voltage from the power supply circuit 24. The power supply voltage level of the battery 12 is detected by the voltage detection circuit 70, and the detected signal is provided to the compensation circuit 71. This allows
The compensation circuit 71 compensates the level of the driving power supply voltage according to the detection signal. Therefore, even if the power supply voltage of the battery 12 fluctuates, a predetermined drive power supply voltage is always obtained. As a result, the drive circuits 21, 22, and 23 are driven in an optimal state without malfunction, and a desired liquid crystal display is achieved.

(Embodiment 5) FIG. 20 is an overall configuration diagram of a display device according to Embodiment 5. Embodiment 5
Are similar to the first embodiment, and corresponding portions are denoted by the same reference numerals. The display device according to the fifth embodiment is an active matrix EL (electroluminescence) display device. 20, reference numeral 80 denotes an EL element, and 81 denotes a current supply line for supplying a drive current to the EL element 80. Tra is a switching transistor as a pixel switching element, and Trb is a driving transistor that functions as a current control element for controlling the amount of current to the EL element. In the fifth embodiment, the switching transistor Tra and the driving transistor Tr
Each of b is a thin film transistor formed of a polycrystalline silicon semiconductor formed on the substrate 28. In addition,
The current supply line 81 is connected to a constant current source (not shown). The power supply for driving the constant current source may be configured to be supplied from the power supply circuit 24 or may be configured to be supplied from an external power supply circuit.

As described above, the present invention can be applied not only to a liquid crystal display device but also to an EL display device. However,
Since the EL display device cannot apply the capacitive coupling drive, the configuration related to the capacitive coupling drive such as the voltage control capacitor, the voltage control capacitor wiring, and the compensation voltage application drive circuit in the liquid crystal display device of the above embodiment is omitted. Therefore, the present invention relating to a liquid crystal display device having another sub-pixel configuration can be applied to an EL display device.

(Other Matters) In the above embodiment, although the level shifter circuit 25 is a built-in circuit formed of a polycrystalline silicon semiconductor, the level shifter circuit is formed of an IC chip formed of a single crystal silicon semiconductor. ,
It may be mounted on a substrate. Further, in the above embodiment, the signal-side drive circuit 22 is a built-in circuit formed of a polycrystalline silicon semiconductor. May be implemented. This makes it possible to increase the film thickness of the transistor and reduce the capacitance as compared with the built-in circuit, thereby reducing the power consumption of the signal side driving circuit. Further, in the case of a built-in circuit, if a defect is present, repair is impossible. In the case of an IC chip, only the defective IC chip needs to be replaced.
The yield is improved.

[0101]

According to the configuration of the present invention as described above, the following effects can be obtained. (1) The use of a charge pump type power supply circuit eliminates the need for a voltage divider circuit as in the conventional example, thereby reducing power loss in the voltage divider circuit and the like and providing a power supply circuit with excellent voltage conversion efficiency. It is possible to realize a liquid crystal display device with low power consumption. (2) By integrally forming the power supply circuit on the insulating substrate, the connection failure that occurs in the external power supply circuit is eliminated, and the reliability is improved. Further, the manufacturing cost can be reduced. (3) In the liquid crystal display device of the capacitive coupling drive system, by optimizing the voltage amplitude of the compensation voltage and the voltage amplitude of the scanning signal, the power consumption is reduced as much as possible, and the display quality is maintained. The aperture ratio can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an electrical configuration of a mobile phone 1 including a liquid crystal display device according to the present invention.

FIG. 2 is an overall configuration diagram of the liquid crystal display device according to the first embodiment.

FIG. 3 is a driving waveform diagram of the liquid crystal display device according to the first embodiment.

FIG. 4 is a specific circuit diagram of a charge pump type power supply circuit.

FIG. 5 is a diagram for explaining the principle of charge pump operation of the power supply circuit.

FIG. 6 is a graph showing a range of Vbias.

FIG. 7 is a graph showing a state where Vbias has shifted to the right.

FIG. 8 is a diagram illustrating a range of a voltage amplitude Vgpp of a scanning signal.

FIG. 9 is an overall configuration diagram of a liquid crystal display device according to a second embodiment.

FIG. 10 is a circuit diagram showing a configuration of a unit pixel of a liquid crystal display device according to a second embodiment.

FIG. 11 is a block circuit diagram showing a specific configuration of a signal-side drive circuit of the liquid crystal display device according to the second embodiment.

FIG. 12 is a diagram showing a data string of image data in the liquid crystal display device according to the second embodiment.

FIG. 13 is a diagram schematically showing an arrangement state of sub-pixels of the liquid crystal display device according to the second embodiment;

FIG. 14 is a timing chart of displacement of a pixel electrode potential in the liquid crystal display device according to the second embodiment.

FIG. 15 is a diagram showing a configuration of a unit pixel in a liquid crystal display device according to a third embodiment.

FIG. 16 is an equivalent circuit diagram of one sub-pixel in the liquid crystal display device according to the third embodiment.

FIGS. 17A and 17B are capacitance configuration diagrams of Embodiment 3 and a conventional example, respectively. FIGS. 17A and 17B are capacitance configuration diagrams of a conventional example, and FIG. FIG.

FIG. 18 is a driving waveform diagram of the liquid crystal display device according to the third embodiment.

FIG. 19 is a block diagram showing a partial configuration of a liquid crystal display device according to a fourth embodiment.

FIG. 20 is a configuration diagram of a liquid crystal display device according to a fifth embodiment.

FIG. 21 is a circuit diagram showing a configuration of a conventional power supply circuit.

[Explanation of symbols]

 Reference Signs List 11: liquid crystal display device 12: battery 20: liquid crystal display unit 21: scanning side drive circuit 22, 22A: signal side drive circuit 23: drive circuit for applying a compensation voltage 24: power supply circuit 25: level shifter circuit 26: signal for applying a compensation voltage Wiring 28: Active substrate 45: Unit pixel 80: EL element CP1 to CP3: Charge pump circuit VDD: Reference reference power supply voltage Tr, Tra: Pixel switching element Trb: Driving transistor (current control element) Tr1 to Tr4: Sub-pixel transistor Cs, C1 to C4: voltage control capacitance M: subpixel electrode M1 to M4: subpixel electrode P1 to P4: subpixel SL: signal line GL: scanning line

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G02F 1/133 520 G02F 1/133 520 1/1368 1/1368 G09G 3/30 G09G 3/30 Z 3 / 36 3/36 H04N 5/66 102 H04N 5/66 102Z (72) Inventor Shinbashi Takehashi 1006 Odakadoma, Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. F term (reference) 2H092 GA40 JA24 JB61 KA04 NA26 2H093 NA16 NA31 NA51 NC01 NC11 NC21 NC22 NC26 NC28 NC34 NC50 NC58 ND39 5C006 AA12 AF46 AF84 BB16 BC20 BF42 BF46 FA18 FA41 FA47 5C058 AA06 AB00 BA01 BA26 BB25 5C080 AA06 AA10 BB05 DD03 DD26 EE28 FF03 FF11 JJ02 JJ03 JJ03 JJ03 JJ03 JJ03 JJ02 JJ03 JJ02 JJ03

Claims (21)

[Claims] 1. A display unit in which unit pixels each having a pixel switching element and a pixel electrode are arranged in a matrix, a scanning driver circuit for supplying a scanning signal to a scanning line, and a signal for supplying an image signal to a signal line. A side drive circuit, a reference power supply voltage, and a drive power supply voltage for the scan side drive circuit and the signal side drive circuit is generated from the reference power supply voltage. The drive power supply voltage is used for the scan side drive circuit and the signal. And a power supply circuit for supplying a power supply circuit to the side drive circuit, wherein the pixel switching element is a thin film transistor formed of a polycrystalline silicon semiconductor formed on an insulating substrate; and the power supply circuit is a charge pump power supply circuit. Further, the power supply circuit is a built-in circuit formed of a polycrystalline silicon semiconductor and integrally formed on the insulating substrate. Display device. 2. The liquid crystal display according to claim 1, wherein the display is a liquid crystal display.
The display device according to the above. 3. The display section is an EL display section that performs display by emitting light from an EL element, and a unit pixel of the EL display section includes a current supplied to the EL element in addition to the pixel switching element and the pixel electrode. The display device according to claim 1, further comprising a current control element for controlling an amount, wherein the current control element is a thin film transistor formed of a polycrystalline silicon semiconductor formed on the insulating substrate. 4. Each of the unit pixels includes a voltage control capacitor having one electrode connected to the pixel electrode, and a voltage control capacitor line connected to the other electrode of the voltage control capacitor and supplying a compensation voltage signal. The voltage control capacitance wiring is connected to a compensation voltage application drive circuit that modulates the potential of the pixel electrode by changing the potential of the compensation voltage signal after the completion of writing to the pixel. 3. The display device according to claim 2, wherein a driving power supply voltage to be supplied to the compensation voltage applying driving circuit is also generated in addition to a driving power supply voltage of the scanning side driving circuit and the signal side driving circuit. 5. The display device according to claim 4, wherein Cs satisfies the following first expression, where Cs is a capacitance value of the voltage control capacitor. Cs = (Vbias / Vepp) · Ctot (1) where Vbias is a change in pixel voltage due to a change in compensation voltage,
Vepp is the voltage amplitude of the compensation voltage signal, and Ctot is the sum of the voltage control capacitance, the parasitic capacitance, and the liquid crystal capacitance. 6. The voltage amplitude Vepp of the compensation voltage signal is
6. The display device according to claim 5, wherein the display device is represented by n times (n is a natural number) of a reference power supply voltage input to the power supply circuit, wherein n is set in a range of 1 ≦ n ≦ 4. 7. The voltage amplitude of the scanning signal is set to m times the reference power supply voltage (m is a natural number).
7. The display device according to claim 6, wherein a voltage amplitude of the scanning signal is set to a value that is a minimum voltage value within a voltage range in which an image signal can be written to the unit pixel. 8. A display unit in which unit pixels are arranged in a matrix, a scanning drive circuit for supplying a scan signal to a scan line, a signal drive circuit for supplying a digital image signal to a signal line, and a reference power supply voltage. Power supply circuit for generating a drive power supply voltage for the scanning side drive circuit and the signal side drive circuit from a reference power supply voltage, and supplying the drive power supply voltage to the scan side drive circuit and the signal side drive circuit Wherein the unit pixel is divided into a plurality of sub-pixels, and each sub-pixel is individually formed of a sub-pixel electrode and a thin film transistor formed of a polycrystalline silicon semiconductor formed on an insulating substrate. A sub-pixel switching element; the power supply circuit is a charge pump type power supply circuit; and the power supply circuit is made of a polycrystalline silicon semiconductor; Display device, characterized in that the internal circuit integrally formed thereon. 9. The liquid crystal display according to claim 8, wherein the display is a liquid crystal display.
The display device according to the above. 10. The display unit is an EL display unit that performs display by emitting light from an EL element. A sub-pixel of the EL display unit is connected to an EL element in addition to the sub-pixel switching element and the sub-pixel electrode. 9. The display device according to claim 8, further comprising a current control element for controlling the amount of current, wherein the current control element is a thin film transistor formed of a polycrystalline silicon semiconductor formed on the insulating substrate. 11. The display device according to claim 8, wherein the area of the sub-pixel electrode in the unit pixel is formed to have a size corresponding to the weight of the digital image signal. 12. The display device according to claim 8, wherein the scanning line is wired for each sub-pixel, and the signal line has a wiring structure commonly wired to all the sub-pixels. 13. Each of the sub-pixels includes a voltage control capacitor having one electrode connected to the sub-pixel electrode, a voltage control capacitor line connected to the other electrode of the voltage control capacitor and supplying a compensation voltage signal. The voltage control capacitance line is connected to a compensation voltage application drive circuit that modulates the potential of the sub-pixel electrode by changing the potential of the compensation voltage signal after completion of writing to the sub-pixel, and the power supply circuit 10. The display device according to claim 9, further comprising: generating a drive power supply voltage to be supplied to the compensation voltage application drive circuit, in addition to the drive power supply voltage of the scan side drive circuit and the signal side drive circuit. 14. The display device according to claim 13, wherein the area of the sub-pixel electrode in the unit pixel is formed to have a size corresponding to the weight of the digital image signal. 15. The display device according to claim 13, wherein each of the sub-pixel switching elements in the unit pixel has an ON current capability corresponding to a weight of the digital image signal. 16. The display device according to claim 13, wherein each of the voltage control capacitors in the unit pixel is formed such that the capacitance value has a size corresponding to the weight of the digital image signal. 17. A storage capacitor is formed between a preceding scanning line among the scanning lines and the pixel electrode.
3. The display device according to 3. 18. The display device according to claim 1, wherein the scan-side drive circuit and the signal-side drive circuit are built-in circuits formed of a polycrystalline silicon semiconductor and integrally formed on the insulating substrate. 19. The signal-side drive circuit is formed of a single-crystal silicon semiconductor, and the scan-side drive circuit is formed of a polycrystalline silicon semiconductor, and is a built-in circuit integrally formed on the insulating substrate. Item 2. The display device according to Item 1. 20. The scan-side drive circuit, the signal-side drive circuit, and the compensation voltage application drive circuit are built-in circuits formed of a polycrystalline silicon semiconductor and integrally formed on the insulating substrate. Item 5. The display device according to Item 4. 21. A level shifter circuit for supplying a control signal to the scan side drive circuit and the signal side drive circuit, wherein the level shifter circuit is formed of a polycrystalline silicon semiconductor, and is integrally formed on the insulating substrate. The display device according to claim 1, wherein the display device is a built-in circuit.