JP2002238282A - Lock protection circuit of brushless motor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a lock protection circuit from being operated when activating a brushless motor using a soft start. SOLUTION: When an output signal is detected from a locked motor speed detection circuit after the output signal from a timer circuit that is generated when at least specific speed is reached and a PWM signal from a PWM output circuit are generated, the lock protection circuit is operated, a lock signal is outputted, and the supply of the signal to the motor is stopped.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lock protection circuit for a brushless motor which protects the motor when locked during rotation.

[0002]

2. Description of the Related Art In a brushless motor, there is a system that converts an input signal into digital data and controls the number of rotations of the motor as a target rotation speed. In the above system, the rotation speed is not increased from 0 to a target value at startup, but gradually increases to reach a target value. When the target value is reached, the motor is rotated at a fixed value.

FIG. 8 is a block diagram of a conventional brushless motor. Reference numerals 1, 2, and 3 denote Y-connected A-phase, B-phase, and C-phase drive coils, and 4, 5, 6, 7, 8, and 9 denote outputs. In the transistor, the collectors of the output transistor 4 and the output transistor 5 are connected, one end of the drive coil 1 is connected to the connection point, and the collectors of the output transistor 6 and the output transistor 7 are also connected. One end of the driving coil 2 is connected and an output transistor 8
And the collector of the output transistor 9 are connected, and one end of the drive coil 3 is connected to the connection point.

[0004] Reference numeral 11 denotes a Hall amplifier waveform conversion circuit, and Hall element signals INA +, INA-, INB +, I obtained by detecting the rotational position of the motor with a Hall element (not shown).
NB−, INC +, and INC− are terminals 12, 13, 14,
The Hall amplifier output signals A, B, and C are applied through the terminals 15, 16, and 17.

Reference numeral 20 denotes the Hall amplifier waveform conversion circuit 11
And output signals AT, AB, BT,
Generates BB, CT, and CB.

Reference numeral 30 denotes an A / D conversion circuit for converting an input signal input to set the number of revolutions into an 8-bit digital signal, and 31 denotes a rotation target value calculation circuit, which is converted by the A / D conversion circuit 30. A target value of the number of revolutions is calculated based on the data of the digital signal thus output, and a target value of the rotational speed Dfan is output. Reference numeral 32 denotes a counter which is a rotation speed control signal generation circuit, and outputs an 8-bit rotation speed control signal DSfan.

As shown in FIG. 5, the counter 32 has a rotation speed control signal Dfan as a target rotation speed target value signal Dfan.
Sfan, which outputs a rotation speed target value signal Dfa
When n rises from OFF (0%), it rises at a slope of 8% / sec. Note that the slope is set every bit.

Reference numeral 34 denotes a voltage correction calculation circuit for correcting a target value based on the rotation speed control signal DSfan from the counter 32. Reference numeral 35 denotes a PWM signal generation circuit for generating a PWM signal in accordance with an output signal of the voltage correction calculation circuit 34. , 36 are comparators for comparing the rotation speed target value signal Dfan from the rotation speed target value calculation circuit 31 and the rotation speed control signal DSfan from the counter 32, and the rotation speed control signal DSfan is calculated from the rotation speed control signal DSfan. Generates a stop signal when it becomes large,
Stop counting 2.

Next, the operation of the block diagram will be described with reference to FIGS. Output transistors 4, 5, 6,
When a pulse signal is forcibly applied to 7, 8, and 9 and these output transistors 4, 5, 6, 7, 8, and 9 are sequentially turned on, a drive current flows through the drive coils 1, 2, and 3 to forcibly start the motor. Rotate to.

When the motor starts to rotate, the rotational position is detected by the Hall element, and the detected Hall element signal INA +,
INA−, INB +, INB−, INC +, and INC− are applied to the Hall amplifier waveform conversion circuit 11 via terminals 12, 13, 14, 15, 16, and 17.

As shown in FIGS. 6 and 7, the Hall element signal IN applied to the Hall amplifier waveform conversion circuit 11 is provided.
A +, INA-, INB +, INB-, INC +, IN
C− is converted into a waveform, and the output signals A, B, and C of the hall amplifiers are converted.
And is applied to the output circuit 20. Then output circuit 2
From 0, output signals AT, AB, BT, BB, CT, and CB are generated.

The output signal AT is applied to the base of the output transistor 4 via the buffer 21, and the output signal AB is applied to the NAND circuit 24.
It is applied to the output transistor 5 together with the WM signal. Similarly, the output signal BT is supplied to the output transistor 6 via the buffer 22.
And the output signal BB is supplied to the NAND circuit 25.
To the output transistor 7 together with the PWM signal from the PWM output circuit 33. Further, the output signal CT is applied to the base of the output transistor 8 via the buffer 23, and the output signal CB is applied to the NAND circuit 26.
It is applied to the output transistor 9 together with the PWM signal from the M output circuit 33.

In FIG. 7, during a period X1 when the output signal AT is at the L level, the output transistor 4 is turned on and the output signal BB applied to the NAND circuit 25 is at the L level, so that the PWM signal from the PWM output circuit 33 is During the L level, the output signal of the NAND circuit 25 becomes H level, and the drive current flows through the drive coils 1 and 2 to turn on the output transistor 7.

In the period X2 in which the output signal AT is at the L level, the output transistor 4 is continuously turned ON and the output signal CB applied to the NAND circuit 26 is at the L level, so that the PWM signal from the PWM output circuit 33 is at the L level. During this period, the output signal of the NAND circuit 26 becomes H level, and the drive current flows through the drive coils 1 and 3 to turn on the output transistor 9.

Next, a period Y in which the output signal BT is at the L level
At 1, the output transistor 6 is turned ON, and the output signal CB applied to the NAND circuit 26 becomes L level.
While the PWM signal from the PWM output circuit 33 is at the L level, the output signal of the NAND circuit 2 is at the H level, and the drive coils 2 and 3
The drive current flows through.

In the period Y2 in which the output signal BT is at the L level, the output transistor 6 is continuously turned on and the output signal AB applied to the NAND circuit 24 is at the L level, so that the PWM signal from the PWM output circuit 33 is at the L level. During this period, the output signal of the NAND circuit 24 becomes H level, and the drive current flows through the drive coil 3 and the drive coil 1 to turn on the output transistor 5.

Further, a period Z in which the output signal CT is at the L level
At 1, the output transistor 8 is turned ON and the output signal AB applied to the NAND circuit 24 becomes L level.
While the PWM signal from the PWM output circuit 33 is at the L level, the output signal of the NAND circuit 24 is at the H level, and the drive current flows through the drive coil 3 and the drive coil 1 to turn on the output transistor 5.

In the period Z2 in which the output signal CT is at the L level, the output transistor 8 is continuously turned on and the output signal BB applied to the NAND circuit 25 is at the L level, so that the PWM signal from the PWM output circuit 33 is at the L level. During this period, the output signal of the NAND circuit 25 becomes H level, and the drive current flows through the drive coil 3 and the drive coil 2 to turn on the output transistor 7.

As described above, the drive current flows sequentially through the drive coils 1, 2, and 3 to rotate the motor.
2 is applied to the voltage correction value calculation circuit 34 to correct the rotation target value, and the corrected output signal is applied to the PWM output circuit 35 to output the PWM.
Generate a signal.

Since the rotation speed control signal DSfan is small at first, the output signal corrected by the voltage correction value calculation circuit 34 is also small. Therefore, the PWM signal output from the PWM output circuit 35 is a PWM signal having a short L-level period. The period in which 5, 7, 9 is turned on is short, and the driving coils 1, 2,
The driving current flowing through the motor 3 is small and the motor is rotated at a low speed.

As the counter 32 counts up little by little, the rotation speed control signal DSfan also increases,
The output signal corrected by the voltage correction value calculation circuit 34 also increases, and the PWM output circuit 35 outputs a PWM signal whose L level period is gradually increased, so that the output transistors 5, 7, 9 are turned on. The driving period gradually increases, the driving current flowing through the driving coils 1, 2, and 3 increases, and the motor speed increases.

The rotation speed control signal DS from the counter 32
fan and the rotation speed target value signal Dfan from the rotation target value calculation circuit 31 are compared by the comparator 36,
The rotation speed control signal DSfan is equal to the rotation speed target value signal Df.
When the value of “an” or more is reached, the stop signal is generated from the comparator 36 and the counting up of the counter 32 is stopped. Thereafter, the fixed rotation speed control signal DSfan from the counter 32 becomes the rotation speed target value signal Dfan,
It is added to the voltage correction value calculation circuit 34 to correct the rotation target value,
The corrected output signal is applied to the PWM output circuit 35 to generate a PWM signal, and is applied to the output transistors 5, 7, 9 to rotate the motor.

The rotation speed control signal DSfan from the counter 32 for soft start is the rotation speed target value signal D.
When the rotation speed reaches fan or more and the rotation speed reaches the target value, the counter 32 is stopped. After reaching the target value, the rotation speed target value signal directly from the rotation speed target value calculation circuit 31 is applied to the voltage correction value calculation circuit 34 instead of the signal from the counter, and the PWM output is output based on the rotation speed target value signal. The PWM signal of the circuit is generated, and the on-time of the output transformer is controlled to control the number of revolutions.

[0024]

As described above, in the brushless motor, the rotation speed does not suddenly change from 0 to the target value at the time of starting, but gradually increases to reach the rotation target value and reaches the target value. The motor is rotated at a predetermined number of revolutions when the motor reaches the predetermined speed. When the motor is rotating at the predetermined rotation speed, when the motor is locked, it is necessary to detect that the motor is locked and stop the motor.

The lock state is detected by detecting that the motor speed has become lower than a certain rotational speed. In the above-mentioned soft-start brushless motor in which the rotational speed is gradually increased to reach a target value, the soft start is performed. Because the lock state is the same as the lock state, the lock protection circuit may operate.

[0026]

SUMMARY OF THE INVENTION The present invention has a plurality of output transistors for supplying a drive current to a plurality of drive coils, and supplies a PWM signal from a PWM output circuit to the plurality of output transistors. In a brushless motor that controls the ON time of the motor and controls the rotation speed, a rotation target value calculation circuit that calculates the rotation speed of the set motor and generates a rotation speed target value signal Dfan, and a rotation speed control signal that counts with a clock signal A counter for generating DSfan; and a target rotational speed signal Dfan.
And a comparator that compares the rotation speed control signal DSfan with the control signal to generate an up-down switching signal and a stop signal;
A PWM output circuit for generating a PWM signal based on the rotation speed control signal DSfan, a motor / motor rotation speed detection circuit for generating an output signal when the motor is locked and the rotation speed falls below a predetermined number, and a target value is set. A timer circuit that starts counting and generates an output signal when a time period at which the rotation speed of the motor is equal to or more than the rotation speed at which lock is detected, an output signal of the motor rotation speed detection circuit, a timer circuit, and PWM. A lock protection circuit to which a PWM signal from an output circuit is added. At start-up, the counter is counted up by a clock signal, and a gradually increasing rotation speed control signal DSfan is generated and applied to a PWM output circuit to control the rotation speed control. PW based on signal DSfan
A PWM signal is generated from the M output circuit, the on-time of the output transistor is increased to increase the rotation speed, and the rotation speed is set to the target rotation speed determined by the rotation speed target value signal Dfan. The output signal from the timer circuit and the PWM circuit are sent to the lock protection circuit. PW from
In the state where the M signal is applied, when the motor is locked and the rotation speed is reduced and the output signal is detected from the motor rotation speed detection circuit,
Provided is a lock protection circuit for a brushless motor that operates a lock protection circuit, outputs a lock signal, and stops supplying a signal to the motor.

[0027]

1 to 5 show an embodiment of the present invention.
It will be described according to. The description of the same components as those in the related art is omitted.

In FIG. 1, reference numeral 29 denotes a duty ratio detection circuit for detecting the duty ratio of a digital signal input to set the number of rotations, and 30 denotes an 8-bit analog signal input to set the number of rotations. An A / D conversion circuit for converting into a digital signal, 31 is a rotation target value calculation circuit,
A rotation speed target value is calculated based on a data signal detected from the duty ratio detection circuit 29 or a digital signal converted by the A / D conversion circuit 30, and a rotation speed target value signal D is calculated.
Output fan. An up / down counter 38 generates a rotation speed control signal, and outputs an 8-bit rotation speed control signal DSfan.

As shown in FIGS. 4 and 5, the up / down counter 38 counts a clock signal applied via a clock switching circuit 39 and outputs a rotation speed control signal DS.
output fan. Rotation speed target value signal Df
When an rises from OFF (0%), the first clock signal is applied and rises at a slope of 8% / sec. After reaching the rotation speed target value, the clock switching circuit 39 is switched. With the addition of two clock signals, the rotation speed target value signal Dfan is changed at a slope of 100% / sec. The slope of the rotation speed target value signal Dfan is 1
Bit by bit.

Reference numeral 40 denotes a comparator, which is a rotation speed target value signal Dfan from the rotation speed target value calculation circuit 31 and a rotation speed control signal DSf from an up / down counter 38.
and the rotation speed target value signal Df.
When the rotation speed control signal DSfan is smaller than an, the level H signal is output from the comparator 40 to the up / down counter 38 as up / down switching.
When the rotation speed control signal DSfan is larger than the rotation speed target value signal Dfan, a signal of level L is output from the comparator 40 to the up / down counter 38 as up / down switching.

The up / down counter 38 counts up / down.
When the down switching signal is at level H, it acts as an up counter that increases the count, and when the up / down switching signal is at level L, it acts as a down counter that decreases the count. When the rotation speed target value signal Dfan and the rotation speed control signal DSfan match, a stop signal is generated, and the counting of the up / down counter 38 is stopped.

A flip-flop circuit 41 is set by a stop signal generated from the comparator 40,
In the stopped state, the rotation speed target value signal Dfan is reset by a signal from the latch circuit 42 when ALL = 0 and generates an output signal. 43 is a voltage correction calculation circuit for correcting a target value based on the rotation speed control signal DSfan from the up / down counter 38, and 44 is a PWM signal generation circuit for generating a PWM signal according to the output signal of the voltage correction calculation circuit 43 It is.

Reference numeral 46 denotes a timer circuit, which starts counting when the rotation target value changes from 0 (when the rotation speed target value is input), and becomes equal to or more than 100 rpm, which is a rotation speed for detecting a lock state described later. H after 5 seconds
Generates a level signal. 47 is a lock protection circuit, 48
Is a motor / motor speed detection circuit for detecting the motor speed by adding an input signal from the Hall amplifier waveform conversion circuit 11 or the like.

When the data signal from the PWM output circuit 44 is not 0 and the rotation speed from the motor / motor speed detection circuit 48 is low, the lock protection circuit 47 outputs, for example, 1
When the rotation speed becomes less than 00 rpm, a lock signal is generated. Reference numeral 50 denotes a two-time coincidence detection circuit, which generates a reset signal for resetting the timer circuit 46.

FIG. 2 is a block diagram of the two-time coincidence detection circuit 46. The NOR circuit 51 to which the rotation speed target value signal Dfan is added, two flip-flops 52 and 53, and output signals of these flip-flops 52 and 53 are shown. Is added to the NAND circuit 54.

FIG. 3 is a specific block diagram of the duty ratio detection circuit 29. Numeral 60 denotes a 2N-bit period counter, which in this embodiment uses a 16-bit counter.
A digital input signal for detecting a duty ratio and a clock signal are added. The period counter 60 is reset at the falling edge of the digital input signal from H level to L level, so that the digital input signal is counted by counting the number of pulses of the clock input signal applied from the reset to the next reset. Is counted, but when the target rotation speed is 0 (stop state), the digital input signal has a duty ratio of 0% (fixed to the H level), and overflows to generate a carry signal.

Reference numeral 61 denotes an N-bit shift circuit for shifting the count number counted by the period counter 60 by N bits. In this embodiment, 16 bits are shifted by 8 bits and the upper 8 bits are taken. Reference numeral 62 denotes an N-bit first L-level period counter, which employs an 8-bit counter in this embodiment, to which the digital input signal and the clock signal are added, and which operates only during the L-level period of the digital input signal. , The number of pulses of the clock signal added during the L-level period.

A comparator 63 compares the output signal from the 8-bit shift circuit 61 with the output signal from the first L-level period counter circuit 62, and when both output signals match, the second clock signal. Occurs. 64
Is an N-bit second L-level period counter. In this embodiment, an 8-bit counter is used. The digital input signal and the second clock signal are added to the L-level period of the digital input signal (hereinafter referred to as L level). Only during the L level period, the number of pulses of the second clock signal added to the L level period is counted.

A first latch circuit 65 latches a digital input signal with a carry signal from the period counter 60. Reference numeral 66 denotes a second latch circuit connected to the output terminal of the second L-level period counter 64, which is reset when a carry signal from the period counter 60 is applied. Reference numeral 67 denotes an OR circuit, to which a latched digital input signal from the first latch circuit 65 is added via an inverter 68 and a second L-level period counter 64
Is added.

The cycle counter 60 is reset when the digital input signal falls, and counts up every time a clock signal is input until the next digital input signal falls, so that during one cycle of the digital input signal. The number of pulses of the input clock signal is counted and a pulse signal of 16-bit count number data is generated.

The pulse signal of the counted 16-bit count data is divided by an 8-bit shift circuit 61 into 1 /
256. That is, the 16-bit count number data is shifted by 8 bits to obtain the upper 8-bit count number data. The pulse signal of the 8-bit count number data obtained by the 8-bit shift circuit 61 and the pulse signal of the count number data of the L-level period counted by the first L-level period counter 62 are applied to a comparator 63 and compared. When the pulse signals of both count number data coincide with each other, the comparator 63 generates a second clock signal.

Applying the second clock signal to a second L-level period counter 64 and counting the number of second pulses added to the L-level period of the digital input signal applied to the second L-level period counter 64 As a result, the duty ratio in the L level period can be obtained.

When the duty of the digital input signal is 0%, one cycle cannot be detected because the digital input signal remains fixed at the H level or the L level.
Since the falling edge of the digital input signal is not detected, the cycle counter 60 continues counting without being reset. When the count is finally completed, the counter overflows and generates a carry signal. The 8-bit shift circuit 6
Since the pulse signal of the 8-bit count number data obtained in 1 and the count number data pulse signal of the L level period counted by the first L level period counter 62 do not match, the comparator 63 outputs the second clock signal. Does not occur.

The carry signal is applied to the first latch circuit 65 to latch the digital input signal and reset the second latch circuit 66.

Assuming that the duty ratio at which the digital input signal is fixed to the H level is 0%, the H level digital input signal latched by the first latch circuit 65 is inverted by the inverter 68 to become the L level. It joins the OR circuit 67. On the other hand, the second latch circuit 66 is reset by the carry signal, and the second L-level counter 64 does not receive the second clock signal, so that the second L-level counter 64 is not counted. Therefore, the second latch circuit 46
Is 0 and the signal from the inverter 68 is also at the L level, so the OR circuit 67 outputs a data signal of 0 indicating that the duty ratio is 0%.

As described above, a drive current flows through the drive coils 1, 2, and 3 sequentially to rotate the motor. At the time of startup, since the rotation speed target signal Dfan is larger than the rotation speed control signal Dsfan, a level H switching signal is generated from the comparator 40 and added to the up / down counter 38. Further, the latch circuit 41 is latched by the activation signal ALL, resetting the flip-flop 41, and setting one input of the AND circuit 45 to the H level.

The other input of the AND circuit 45 receives the H-level signal from the comparator 40, so that a level H clock switching signal is generated from the output of the AND circuit 45, and the switching circuit 39 outputs the first clock signal. Is switched so that is output.

When the first clock signal is applied to the up / down counter 38, the up / down counter 38 counts up at 8% / sec of n bits. The up / down counter 38 counts up to generate a rotation speed control signal Dsfan.

As shown in FIG. 4, as the up / down counter 38 counts up, the rotation speed control signal DSfan rises at a slope of 8% / sec. The rotation speed control signal DSfan is corrected by the voltage correction value calculation circuit 43, and the voltage correction value calculation circuit 43 generates an output signal that gradually increases. The output signal is applied to the PWM output circuit 44, and a PWM signal whose L level period is gradually increased is output. As a result, the period during which the output transistors 5, 7, 9 are turned on gradually increases, the drive current flowing through the drive coils 1, 2, 3 increases, and the motor speed increases.

The rotation speed control signal DSfan from the up / down counter 38 and the rotation speed target value signal Dfan from the rotation target value calculation circuit 31 are compared by a comparator 40. When the rotation speed control signal DSfan reaches the rotation speed target value, the rotation speed control signal DSfan is converted. The signal coincides with the rotation speed target value signal Dfan, a stop signal is generated from the comparator 40, and the up / down counter 38 stops counting up.

When the rotation target value is reached, the flip-flop 41 is set by the stop signal generated from the up / down counter 38, and one of the AND circuits 41 is set to L level. Accordingly, an L-level clock switching signal is generated from the output of the AND circuit 41 to switch the clock switching circuit 39, and the second clock signal is applied to the up / down counter 38.

The comparator 40 compares the rotation target value signal with the rotation speed control signal DSfan. If the rotation target value signal is larger than the rotation speed control signal DSfan, the up / down counter 38 is incremented by the second clock signal. I do. Conversely, when the rotation target value signal is smaller than the rotation speed control signal DSfan, the up / down counter 3
In step 8, the count is down-counted by the second clock signal. The up / down counter 38 counts up or down at 100% / sec of n bits. For example, in the case of an 8-bit digital data signal, it counts up or down from 0 to 255 in one second.

Therefore, as shown in FIG. 4, after reaching the rotation target value, the rotation speed control signal DSfan changes at a slope of 100% / sec. The rotation speed control signal DSfan is corrected by the voltage correction value calculation circuit 43, and the voltage correction value calculation circuit 43 generates an output signal. The output signal is PW
The PWM signal is output to the M output circuit 44, and the output transistor is controlled to rotate the motor at the rotation target value.

By the way, the lock protection circuit 47 starts counting when the timer circuit 46 inputs the target number of revolutions, and adds the H-level signal generated when 3.5 seconds have elapsed. Further, the PWM signal output from the PWM output circuit 44 is applied to the lock protection circuit 47 while the motor is rotating. As described above, the lock protection circuit 47 is locked in a state where the output signal from the timer circuit 46 and the PWM signal from the PWM output circuit 44 are added, the rotation speed becomes 100 prm or less, and the output signal from the motor rotation speed detection circuit 48 becomes Is detected. Then, a lock signal is generated from the lock protection circuit 47 to stop the signal to the motor, and the up / down counter 38 is reset and protected.

As described above, the timer circuit 46
Counting starts when the rotation speed target value is input,
An H-level signal is generated when 3.5 seconds have elapsed, which is equal to or higher than 100 rpm, which is the rotation speed for detecting the lock state. Then, when the rotation target value is set to 0 to stop, the L level is set.

That is, the duty ratio detection circuit 2 for stopping
If the duty ratio of the digital signal added to 9 is set to 0,
The rotation speed target value signal Dfan calculated from the rotation speed target value calculation circuit 31 becomes ALL = 0. ALL = 0
The set rotation speed target value signal Dfan is set to the two-time matching circuit 5.
0 is applied to the D terminal of the flip-flop 52 via the NOR circuit 51, and the D terminal is set to level H.

On the other hand, when the duty ratio of the digital input signal is 0
As described above, when the 16-bit cycle counter 60 overflows as described above, a carry signal is generated, the carry signal is applied to the S terminal of the flip-flop 52, and the Q terminal of the flip-flop 52 is set to the H level.

When the time further elapses, the 16-bit cycle counter 60 overflows again, and when a carry signal is further generated and applied to the S terminal of the flip-flop 53, the D terminal is at the H level.
Both the Q terminal and the output become H level, these signals are applied to the NAND circuit 54, taken out as a high level reset signal from the NAND circuit 54, resetting the timer circuit 46, and resetting the timer circuit 46 by an erroneous signal. I try not to.

As described above, the rotation speed target value signal D set to ALL = 0 before the timer circuit 46 is stopped.
The fan was reset by turning on the fan switch → O
When the FF is turned on, the lock protection circuit 47 operates and the motor remains stopped if the timer circuit 46 is not reset when the timer circuit 46 is turned on after the speed becomes 100 rpm or less when the FF is turned off. This is to prevent it.

When the locked state is released, and the duty ratio is specified again to set the rotation speed target value, the signal from the duty ratio detection circuit 29 is applied to the rotation target value calculation circuit 31, and the rotation speed target calculation circuit 31 is set. Outputs a rotation speed target value signal Dfan. Since the up / down counter 38 has been reset, soft start is performed and the rotation is increased to the set rotation speed target value in the same manner as described above.

In the above description, after reaching the rotation speed target value, the up / down counter 38 is repeatedly rotated up and down by the second clock signal at the rotation speed target value. As described above, the fixed rotation speed control signal DSfan from the up / down counter is applied to the voltage correction value calculation circuit 43 to correct the rotation target value, and the corrected output signal is applied to the PWM output circuit 44 to generate a PWM signal. Alternatively, in addition to the output transistors 5, 7, and 9, the motor may be rotated at a target rotation speed.

After reaching the rotation speed target value, the up / down counter is stopped, and the rotation speed target value signal Dfan from the rotation speed target value calculation circuit is directly applied to the voltage correction value calculation circuit 43, and the rotation target value is calculated. The corrected output signal may be applied to the PWM output circuit 44 to generate a PWM signal, and the output signal may be applied to the output transistors 5, 7, and 9 to rotate at the target rotation speed.

[0063]

According to the lock protection circuit for a brushless motor of the present invention, an output signal is generated when the motor is locked by a motor / motor speed detection circuit and the speed becomes equal to or less than a predetermined value. When it is set, counting starts and an output signal is generated when the time when the number of rotations of the motor is equal to or more than the number of rotations for detecting lock is output, and the lock protection circuit outputs an output signal from a timer circuit and a signal from a PWM circuit. When the PWM signal is applied and the output signal is detected from the motor speed detection circuit after being locked, the lock protection circuit is operated to output the lock signal and stop supplying the signal to the motor. Even in a brushless motor employing a soft start, a lock protection circuit that does not malfunction at startup can be obtained.

Since the counter is reset by the lock signal from the lock protection circuit, when the locked state is released,
The counter is operated again to count and soft start.

Further, when the timer circuit is stopped, the timer circuit is reset before the rotation speed at which the output signal is generated from the motor rotation speed detection circuit. Therefore, when the timer circuit is stopped, the lock protection circuit operates. There is no danger if the lock does not work when activated.

[Brief description of the drawings]

FIG. 1 is a block diagram of a lock protection circuit of a brushless motor according to the present invention.

FIG. 2 is a block diagram of a twice match detection circuit used in the present invention.

FIG. 3 is a block diagram of a duty ratio detection circuit used in the present invention.

FIG. 4 is a characteristic diagram of a rotation speed control signal at the time of slow start of the lock protection circuit of the present invention and a conventional brushless motor.

FIG. 5 is a characteristic diagram of a rotation speed control signal of the lock protection circuit of the present invention and the conventional brushless motor after reaching a target rotation speed.

FIG. 6 is a waveform diagram of a part of a lock protection circuit of the present invention and a conventional brushless motor.

FIG. 7 is a waveform diagram of another portion of the lock protection circuit of the present invention and the conventional brushless motor.

FIG. 8 is a circuit diagram of a conventional soft start circuit of a brushless motor.

[Explanation of symbols]

 1, 2, 3 drive coil 4, 5, 6, 7, 8, 9 output transistor 29 duty ratio detection circuit 30 A / D conversion circuit 31 rotation target value calculation circuit 38 up / down counter 39 clock signal switching circuit 40 comparator 43 voltage Correction value calculation circuit 44 PWM signal generation circuit 46 Timer circuit 47 Lock protection circuit 48 Motor Motor rotation speed detection circuit 50 Twice match circuit

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Hirotaka Morita 2-5-5 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. F-term (reference) 5G044 AA07 AB03 AC06 AD07 CA07 5H560 BB04 BB07 DA02 DA20 DB02 EB01 GG03 HA01 JJ07 RR10 TT01 TT02 TT04 TT07 UA03 XA12

Claims (6)

[Claims] An output transistor for supplying a drive current to a plurality of drive coils, a PWM signal from a PWM output circuit being supplied to the plurality of output transistors, and an on-time of these output transistors being controlled to rotate. In a brushless motor that controls the speed, a rotation target value calculation circuit that calculates a set rotation speed of the motor and generates a rotation speed target value signal Dfan, and a rotation speed control signal DSfan that counts with a clock signal.
Counter for generating the rotation speed target value signal Dfan and the rotation speed control signal D
Sfan, a comparator for generating an up / down switching signal and a stop signal, a PWM output circuit for generating a PWM signal based on the rotation speed control signal DSfan, A motor / motor rotation number detection circuit that generates an output signal, and starts counting when a rotation number target value is set, and outputs an output signal when a time period at which the motor rotation number becomes equal to or more than the rotation number for detecting lock is elapsed. A timer circuit to be generated; a lock protection circuit to which an output signal of the motor rotation speed detection circuit, a timer circuit, and a PWM signal from a PWM output circuit are added;
A gradually increasing rotation speed control signal DSfan is generated and applied to a PWM output circuit to generate the rotation speed control signal DSfan.
A PWM signal is generated from a PWM output circuit based on the fan, the ON time of the output transistor is increased to increase the rotation speed, and the rotation speed is set to a target rotation speed determined by a rotation speed target value signal Dfan. Signal and P
When the PWM signal from the WM circuit is applied and the motor is locked and the number of rotations of the motor is reduced and an output signal is detected from the motor speed detection circuit, the lock protection circuit operates to output a lock signal to the motor. A lock protection circuit for a brushless motor, characterized by stopping supply of a signal. 2. The lock protection circuit for a brushless motor according to claim 1, wherein a signal to the motor is stopped by a lock signal from the lock protection circuit, and a counter is reset. 3. The lock protection circuit for a brushless motor according to claim 1, wherein said timer circuit starts counting when a target value is set, and generates an output signal when 3.5 seconds have elapsed. . 4. The lock protection circuit for a brushless motor according to claim 1, wherein said motor rotation number detection circuit is locked and generates an output signal when the rotation number becomes 100 rpm or less. 5. The timer circuit is reset before the output signal is output from the motor rotation speed detection circuit when the rotation target value signal of the rotation speed target value calculation circuit becomes 0 for stopping. The lock protection circuit for a brushless motor according to claim 1, wherein: 6. An ALL = 0 signal generated from a target rotation value calculation circuit when a target rotation value is set to 0 to stop the double detection circuit, and a duty ratio is set to 0 from a duty ratio detection circuit. 2. The lock protection circuit for a brushless motor according to claim 1, wherein the timer circuit is reset by an output signal generated from the two-time coincidence circuit at the time of adding the carry signal twice.