JP2002198518A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and a manufacturing method thereof wherein the channel width of the device can be selected arbitrarily without restriction on its chip area, and the high-speed operations and the low power consumptions of the devices are made possible without preventing the increase of their integration density. SOLUTION: The semiconductor device is so formed that the main current of the transistor is distributed over a channel width W in the depthwise direction of a buried gate electrode 115. That is, the low direction of the main current is vertical to the surface of the semiconductor substrate of the device, and the direction of its distribution is vertical to the surface of the semiconductor substrate. By using such a structure, the channel width can be selected arbitrarily without restriction on the chip area of the semiconductor device. By connecting in parallel with each other these semiconductor devices, the high- speed operations and the low power consumptions of operational circuits are made possible without preventing the increase of their integration density.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an insulated gate transistor structure and a method of manufacturing the same, and more particularly to a transistor having a structure in which a gate electrode is embedded in a trench and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, with the development of the information communication field, semiconductor devices are required to have higher integration, higher speed, and lower power consumption. Due to the demand for higher integration, the gate dimensions of semiconductor devices composed of insulated gate transistors have been reduced. As the gate width becomes narrower as the gate size shrinks, problems such as an increase in channel resistance, a decrease in transistor drive capability, and a deterioration in transistor characteristics due to a narrow channel effect, which hinder high speed and low power consumption, are solved. Inviting. Such a problem is often seen particularly in power devices in which importance is placed on transistor drive capability.

In order to solve these problems without hindering high integration, there is a method of shortening the channel length to lower the channel resistance. However, by shortening the channel length, the breakdown voltage of the transistor is reduced. However, problems such as a reduction in transistor driving capability and deterioration of transistor characteristics due to a short channel effect are caused.

[0004] Conventional semiconductor devices composed of insulated gate transistors are broadly classified into lateral (horizontal) transistors and vertical (vertical) transistors. A lateral transistor refers to a semiconductor device in which a main current flows parallel to the surface of a semiconductor substrate, and the main current is localized near the semiconductor surface and distributed parallel to the semiconductor surface. Here, the main current is a current flowing between the first main electrode region (source region) and the second main electrode region (drain region), and is a control voltage applied to the gate electrode or a control voltage flowing through the gate electrode. This is the current controlled by the current.

FIGS. 13 (a) to 14 (g) show an example of a lateral transistor. Hereinafter, a method for manufacturing a MOS-structured lateral transistor will be described in detail as a conventional method for manufacturing a semiconductor device. First, as shown in FIG. 13A, a thick silicon oxide film 602 is formed in an arbitrary region on a semiconductor substrate 601, and an element formation region 603 and an element isolation region 604 are formed. This element isolation step is performed, for example, by using LOCOS (Local O
xidation of Silicon) method or the like.

For example, when an n-type MOS transistor is formed, an impurity such as boron is implanted in a region to be formed by using, for example, lithography and ion implantation.
A p-type well region is formed in 601. Next, in order to set the threshold value of the MOS transistor to a desired value, the element formation region
After injecting desired impurities into the surface of the element forming region 603, a gate insulating film 605 is formed on the surface of the element forming region 603 by oxidation or the like. Further, for example, a gate electrode formed of the barrier metal 606 is formed.

Next, as shown in FIG. 13B, a barrier metal 606 is deposited on the surface of the gate insulating film 605 by using a CVD method or the like.

Next, as shown in FIG. 13C, a resist is applied to the surface of the barrier metal 606 to form a resist film, and a resist pattern serving as a gate electrode pattern is formed using lithography and etching techniques. Form.
Next, using the patterned resist pattern as a mask, the barrier metal 606 is sequentially etched to separate the resist pattern, thereby forming a gate electrode.

Next, as shown in FIG. 13 (d), an impurity such as phosphorus is introduced into the surface of the element forming region 603 by ion implantation or the like to form n and n first and second main electrode regions. ^{+ A} diffusion region 607 is formed.

Next, as shown in FIG. 14E, an interlayer insulating film 608 is deposited by a CVD method or the like, and the surface is polished and flattened by a CMP method.

Next, as shown in FIG.
A predetermined portion of the interlayer insulating film 608 on the second main electrode region and the gate electrode is patterned to open a contact hole. Subsequently, a wiring material 609 is formed by embedding a conductive material such as W, and a MOS transistor is formed.
In a semiconductor device and a lateral transistor formed in this manner, the main current has a gate width, that is, a channel width.
It is distributed in the direction of W. That is, the direction in which the main current flows is parallel to the surface of the semiconductor substrate, and the direction of distribution, that is, the direction of the channel width W, is parallel to the surface of the semiconductor substrate.

On the other hand, in the vertical transistor, the direction in which the main current flows is perpendicular to the surface of the semiconductor substrate, and the direction of distribution, that is, the direction of the channel width W is parallel to the surface of the semiconductor substrate. As an example of a vertical transistor, FIGS. 15H and 15I are a top view and a cross-sectional view. The manufacturing method is omitted because it can be formed by a combination of the manufacturing steps of the lateral transistor.

[0013]

In the conventional semiconductor device having such a structure, the channel width W is reduced by reducing the gate size, and thereby, the channel which causes an increase in speed and a reduction in power consumption is hindered. This causes an increase in resistance and a deterioration in transistor characteristics due to a narrow channel effect. In addition, an increase in channel resistance causes a decrease in current for driving a transistor, which causes a problem such as a reduction in transistor driving capability. This is a serious problem particularly when used as a power device in which transistor drive capability is emphasized due to a requirement for a large current.

On the other hand, as a method of solving these problems without hindering high integration, there is a method of shortening the channel length to lower the channel resistance. However, by shortening the channel length, the breakdown voltage of the transistor is reduced. Is reduced, which causes problems such as a reduction in transistor driving capability, which is not desirable. There is a trade-off between high integration and improvement in transistor driving capability.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems. The present invention is not limited to a chip area, and can freely select a channel width. To provide a semiconductor device capable of realizing, for example, a reduction in channel resistance, improvement in transistor driving capability, prevention of transistor characteristic deterioration due to a narrow channel effect, and a method for manufacturing the same, which can realize high power consumption and low power consumption. The purpose is. Therefore, by applying the present invention, high integration, high speed, and low power consumption can be achieved and the transistor driving capability can be improved.

[0016]

In order to achieve the above object, a semiconductor device according to the present invention comprises, in a first region on a substrate, an element forming region formed by a thin insulating film, and an element forming region other than the element forming region. Forming an element isolation region formed by a thick insulating film in a region, and forming a mask pattern in a part of the element formation region, and introducing an impurity of a carrier type opposite to a substrate or a well using the mask pattern as a mask. By the first and second main electrode diffusion regions formed apart from each other, at least a part of the first main electrode diffusion region, and at least a part of the second main electrode diffusion region, First and second main electrodes formed by selectively forming a conductive material, and a gate groove formed by etching in a part of a region where the mask pattern is formed. And a buried gate electrode formed by burying a conductive material in the gate groove having the gate insulating film formed on the side wall and the bottom, and a gate insulating film formed on the side wall and the bottom of the gate groove. And an insulating film formed on the element formation region including the element isolation region and the buried gate electrode, the first and second main electrodes; and the buried gate electrode, the first and second main electrodes. And a contact formed by selectively forming a conductive material in the opening to expose the surface of the first electrode and the second main electrode. The direction of the component of the main current controlled by the buried gate electrode in the main current flowing between the diffusion regions is substantially parallel to the surface of the element formation region, and the direction of the main current distribution is Wherein a surface of the forming region and are substantially perpendicular.

Further, a method of manufacturing a semiconductor device according to the present invention
In a first region on the substrate, a step of forming a thin insulating film to form an element forming region, and a step of forming a thick insulating film in a region other than the element forming region to form an element isolation region,
A first and second main electrode diffusion regions are separated by forming a mask pattern in a part of the element formation region and introducing an impurity of a carrier type opposite to a substrate or a well using the mask pattern as a mask. Forming, and at least a part of the first main electrode diffusion region,
In at least a part of the second main electrode diffusion region,
By selectively forming conductive materials,
Forming a first and a second main electrode, forming a gate groove by etching in a part of a region where the mask pattern is formed, and forming a gate insulating film on a side wall and a bottom of the gate groove. Forming, forming a buried gate electrode by burying a conductive material in the gate groove in which the gate insulating film is formed on the side wall and the bottom, and forming the buried gate electrode, Forming an insulating film on the element formation region including the first and second main electrodes, and forming the opening by exposing the surface of the buried gate electrode and the first and second main electrodes; Forming a contact by selectively forming a conductive material in the opening.

According to the present invention, it is possible to arbitrarily select a channel width without being limited by a chip area. Therefore, it is possible to realize reduction in channel resistance, improvement in transistor driving capability, prevention of transistor characteristic deterioration due to a narrow channel effect, and the like, which enable high speed and low power consumption without hindering high integration. A semiconductor device and a method for manufacturing the same can be provided.
Further, since the semiconductor device has a SOI structure in a direction parallel to the surface of the semiconductor substrate, the first and second main electrode regions and the second
The connection capacitance between the first and second main electrodes can be reduced, and the speed can be further increased.

Further, a part of the gate groove is formed on the element isolation region. According to the present invention, one channel can be controlled by one buried gate electrode.

Further, the first and second main electrodes are connected to the first and second main electrodes.
A conductive material is selectively formed in at least a part of the first main electrode diffusion region and at least a part of the second main electrode diffusion region.

Further, the buried gate electrode formed between the first and second main electrodes is formed by arranging two in parallel. According to the present invention, an OR circuit or a NOR circuit can be configured by combining the above-described semiconductor devices, and high integration, high-speed operation of the arithmetic circuit, and low power consumption are realized. In addition, by improving the driving capability of the transistor, it is possible to reduce signal transmission errors, and it is possible to further improve the reliability of the semiconductor device.

In addition, a plurality of or two of the above-described semiconductor devices having the same conductivity as the carrier type of the first main electrode diffusion region or the second main electrode diffusion region are used, and the first and second semiconductor devices are used. It is characterized by comprising two main electrodes connected in parallel. According to the present invention, it is possible to configure an OR circuit or a NOR circuit.

[0023] In addition, the first main electrode diffusion region or the second main electrode diffusion region has two kinds of semiconductor devices, each having a carrier type opposite to that of the first main electrode diffusion region.
And a second main electrode connected in parallel. According to the present invention, it is possible to configure a transmission gate circuit.

[0024] Further, the buried gate electrodes are connected by using the two semiconductor devices described above, wherein the carrier type of the first main electrode diffusion region or the second main electrode diffusion region has opposite conductivity. It is characterized by comprising. According to the present invention, it is possible to configure an inverter circuit.

A first element forming area and a second element forming area formed by a thin insulating film in the first area and the second area on the substrate; and the first and second element forming areas. In other regions, an element isolation region formed by a thick insulating film and a first mask pattern are formed in a part of the first element formation region, and impurities of a carrier type opposite to a substrate or a well are formed in the second region. By introducing the first mask pattern as a mask, the first and second main electrode diffusion regions formed separately and the second mask pattern are formed in a part of the second element formation region. The third and fourth main electrode diffusion regions formed separately by introducing an impurity of a carrier type opposite to that of the substrate or the well using the second mask pattern as a mask; and
A first main electrode formed by selectively forming a conductive material in a part of the main electrode diffusion region and the third main electrode diffusion region, and the second main electrode diffusion region. A second main electrode formed by selectively forming a conductive material on a part of the fourth main electrode diffusion region,
In a part of the region where the first mask pattern and the second mask pattern are formed, first and second gate grooves respectively formed by etching, and the first and second gate grooves. The first and second gate trenches formed by embedding a conductive material in the gate insulating film formed on the side wall and the bottom, and the first and second gate trenches on which the gate insulating film is formed on the side wall and the bottom. A second buried gate electrode, an insulating film formed on the device forming region including the device isolation region, the first and second buried gate electrodes, the first and second main electrodes, First and second embedded gate electrodes, a contact formed by exposing a surface of the first and second main electrodes to form an opening, and selectively forming a conductive material in the opening. A semiconductor device comprising: The main current flowing between the first and second main electrode diffusion regions and the main current flowing between the third and fourth main electrode diffusion regions are controlled by the first or second buried gate electrode. The direction of the component of the main current is substantially parallel to the surface of the first or second element formation region, and the direction of the distribution of the main current is substantially equal to the surface of the first or second element formation region. It is characterized by being vertically vertical.

A step of forming a thin insulating film on the first region and the second region on the substrate to form a first element forming region and a second element forming region; Forming a thick insulating film in a region other than the element formation region to form an element isolation region; and forming a first region in a part of the first element formation region.
The first and second main electrode diffusion regions are formed apart by forming a mask pattern and introducing an impurity of a carrier type opposite to that of the substrate or the well using the first mask pattern as a mask. Forming a second mask pattern in a part of the second element formation region, and removing impurities of a carrier type opposite to a substrate or a well by the second mask pattern.
Forming the third and fourth main electrode diffusion regions apart from each other by introducing the mask pattern as a mask, and forming the third main electrode diffusion region and the third main electrode diffusion region. Forming a first main electrode by selectively forming a conductive material in some regions; and forming a second main electrode diffusion region and a partial region of the fourth main electrode diffusion region in the fourth main electrode diffusion region. Second by selectively forming a conductive material
A step of forming a main electrode, and a step of forming first and second gate grooves by etching in each of partial regions of the region where the first mask pattern and the second mask pattern are formed, Forming a gate insulating film on sidewalls and bottoms of the first and second gate trenches; and forming the first and second gate insulating films on sidewalls and bottoms.
By embedding a conductive material in the gate groove of
Forming a second buried gate electrode, and forming an insulating film on the device forming region including the device isolation region, the first and second buried gate electrodes, and the first and second main electrodes. Forming an opening by exposing surfaces of the first and second buried gate electrodes, the first and second main electrodes, and selectively forming a conductive material in the opening. Forming a contact.

According to the present invention, it is possible to configure a circuit using the two semiconductor devices described above. further,
By separating the formation regions of the two semiconductor devices by the element isolation regions, it is possible to prevent a malfunction of a signal generated due to the overlap of two channels during a circuit operation. This increases the degree of freedom and reliability of circuit design. Further, since the structure has an SOI structure in a direction parallel to the surface of the semiconductor substrate, it is possible to reduce the connection capacitance between the first and second main electrode regions and the first and second main electrodes. And the speed can be further increased.

Further, the first and second gate trenches are partially formed on the element isolation region. According to the present invention, one channel can be controlled by one buried gate electrode.

Further, the first main electrode is formed in a part of the first main electrode diffusion region and the third main electrode diffusion region.
Selectively formed by embedding a conductive material,
The second main electrode includes the second main electrode diffusion region and the fourth main electrode.
Is selectively formed by embedding a conductive material in a part of the main electrode diffusion region.

Further, the carrier type of the substrate or well in the first and second regions has the same conductivity. According to the present invention, it is possible to configure an OR circuit or a NOR circuit.

The carrier type of the substrate or well in the first and second regions has opposite conductivity. According to the present invention, it is possible to configure a transmission gate circuit.

A first element forming area and a second element forming area formed by a thin insulating film on the first area and the second area on the substrate; and the first and second element forming areas. In other regions, an element isolation region formed by a thick insulating film and a first mask pattern are formed in a part of the first element formation region, and impurities of a carrier type opposite to a substrate or a well are formed in the second region. By introducing the first mask pattern as a mask, the first and second main electrode diffusion regions formed separately and the second mask pattern are formed in a part of the second element formation region. The third and fourth main electrode diffusion regions formed separately by introducing an impurity of a carrier type opposite to that of the substrate or the well using the second mask pattern as a mask; and
A conductive material is selectively formed in a part of the fourth to fourth main electrode diffusion regions.
First to fourth main electrodes, and a part of a region where the first mask pattern and the second mask pattern are formed,
One gate groove formed by etching, a gate insulating film formed on the side wall and the bottom of the gate groove, and a conductive material in the gate groove formed with the gate insulating film on the side wall and the bottom. A buried gate electrode formed by burying, the element isolation region, the buried gate electrode, an insulating film formed on the element formation region including the first to fourth main electrodes, the buried gate electrode, A semiconductor device comprising: an opening formed by exposing a surface of the first to fourth main electrodes; and a contact formed by selectively forming a conductive material in the opening. A main current flowing between the first and second main electrode diffusion regions, and a main current controlled by the buried gate electrode among main currents flowing between the third and fourth main electrode diffusion regions. Direction is substantially parallel to the surface of the first or second element formation region, and the direction of main current distribution is substantially perpendicular to the surface of the first or second element formation region. It is characterized by being.

A step of forming a thin insulating film on the first region and the second region on the substrate to form a first element forming region and a second element forming region; Forming a thick insulating film in a region other than the element formation region to form an element isolation region; and forming a first region in a part of the first element formation region.
The first and second main electrode diffusion regions are formed apart by forming a mask pattern and introducing an impurity of a carrier type opposite to that of the substrate or the well using the first mask pattern as a mask. Forming a second mask pattern in a part of the second element formation region, and removing impurities of a carrier type opposite to a substrate or a well by the second mask pattern.
The step of forming the third and fourth main electrode diffusion regions apart by introducing using the mask pattern as a mask, and a part of the first to fourth main electrode diffusion regions, A step of forming first to fourth main electrodes by selectively forming a conductive material, and a part of a region where the first mask pattern and the second mask pattern are formed, A step of forming one gate groove by etching, a step of forming a gate insulating film on a side wall and a bottom of the gate groove, and a step of forming a conductive film on the gate groove on which the gate insulating film is formed on the side wall and the bottom. Forming a buried gate electrode by burying a material, the element isolation region, the buried gate electrode,
Forming an insulating film on the element formation region including the first to fourth main electrodes, and forming openings by exposing surfaces of the embedded gate electrode and the first to fourth main electrodes. Forming a contact by selectively forming a conductive material in the opening.

According to the present invention, it is possible to configure a circuit using the two semiconductor devices described above. further,
By separating the formation regions of the two semiconductor devices by the element isolation regions, it is possible to prevent a malfunction of a signal generated due to the overlap of two channels during a circuit operation. This increases the degree of freedom and reliability of circuit design. Further, since the structure has an SOI structure in a direction parallel to the surface of the semiconductor substrate, the connection capacitance between the first and second main electrode regions and the first and second main electrodes, or the third and the second main electrodes. The connection capacitance between the fourth main electrode region and the third and fourth main electrodes can be reduced, and the speed can be further increased.

Further, the first to fourth main electrodes are partially formed on the element isolation region.

Further, the first to fourth main electrodes are connected to the first
The first to fourth main electrode diffusion regions are selectively formed by embedding a conductive material in a part of the regions.

The carrier type of the substrate or well in the first and second regions has opposite conductivity. According to the present invention, it is possible to configure an inverter circuit.

[0038]

Embodiments of the present invention will be described below in detail with reference to the drawings. (First Embodiment) In this embodiment, a novel insulated gate type MO having a structure different from that of a conventional semiconductor device such as a lateral transistor or a vertical transistor is described.
An S transistor structure is described.

FIGS. 1 (a) to 4 (d) and FIGS. 1 (a ') to 4 (d')
Next, the steps of a method for manufacturing a MOS transistor will be described with reference to a top view and cross-sectional views in cross section A or B shown in the top view.

First, FIGS. 1A and 1A show a top view of the first step and a cross-sectional view of the cross section A. As shown in FIG. 1A, a thick silicon oxide film 102 is formed in an arbitrary region on a semiconductor substrate 101, and an element formation region 103 and an element isolation region 104 are formed.

This element isolation step is performed by STI (Shallow Trenc
h Isolation) and LOCOS (Local Oxidation of Silicon)
This is performed using a method. Subsequently, an impurity such as boron is formed in a region for forming an n-type MOS transistor, and an impurity such as phosphorus, arsenic, or antimony is formed in a region for forming a p-type MOS transistor. In the semiconductor substrate 101, a p-type well or
An n-type well region is formed.

Here, a method of forming an n-type MOS transistor will be particularly described. However, a p-type transistor can also be manufactured by a similar method. As the ion implantation conditions, for example, the p ^- diffusion region 105 is formed using an acceleration voltage of 500 keV and a dose of 3 × 10 ¹³ cm ⁻² . The dose is not particularly limited.

Next, similarly, as shown in FIGS. 2B and 2B, a source electrode and a drain electrode are formed. First, a resist pattern 106 having a gate length L is formed on the element formation region 103.
Is formed, and ions are implanted into the p-type well region by using an ion implantation method or the like. As ion implantation conditions, for example,
Performed using an acceleration voltage of 250 keV and a dose of 5 × 10 ¹⁵ cm ^-2 ,
First and second n ⁺ diffusion regions serving as first and second main electrode regions
107 and 108 are formed. The dose is not particularly limited.

Next, for example, using the RIE etching method,
First and second main electrode grooves 109 and 110 are formed, and the first and second main electrode grooves 109 and 110 are formed of, for example, Ti /
A barrier metal such as TiN and Al are buried, and the first step to become a source electrode and a drain electrode is performed by the same process as the STI method.
And the second main electrodes 111 and 112 are formed.

The depths of the first and second main electrode grooves 109 and 110 are as follows:
For example, it may be 0.2 μm, but may be shallower. Alternatively, they may be selectively formed on the first and second main electrode regions without forming a groove. The first and second main electrodes 111 and 112 may be formed so that at least a part of the first and second main electrodes 111 and 112 overlap the first and second n ⁺ diffusion regions 107 and 108. The position is not particularly limited.

The depth of the first and second main electrode grooves 109 and 110 is not particularly limited, and may be, for example, 0.2 μm. The conductive material to be embedded is not particularly limited, and examples thereof include polysilicon, a high melting point metal, a high melting point metal silicide, Cu, and a laminated film thereof.

Next, FIGS. 3C and 3C show a top view and a cross section B, respectively.
FIG. As shown in FIG. 3C, a buried gate electrode is formed. The resist pattern formed on the p ^- diffusion region 105 serving as a buried gate electrode region is removed, and a gate groove 113 is formed by RIE etching, and a gate insulating film is formed on the side and bottom of the gate groove 113. 1
14 is formed by oxidation or the like. The depth of the gate groove 113 can be freely selected, and can be, for example, 0.2 μm, which is about the same as the first and second main electrode grooves 109 and 110. It may be deeper.

The gate groove 113 only needs to be formed so that only a part of it extends over the p ^- diffusion region 105, and the formation position when viewed from above is not particularly limited. The gate insulating film 114 is not particularly limited.
iO ₂ , SiN and the like. In the area where the buried gate electrode is not formed, the CMP (Chemica
The surface is polished and flattened by the mechanical polishing method.

Next, a laminated film of a barrier metal such as Ti / TiN and Al as a conductive material is buried in the gate groove 113, and a buried gate electrode 115 is formed by the same process as in the STI method. The conductive material to be embedded is not particularly limited, and examples thereof include polysilicon, a high melting point metal, a high melting point metal silicide, Cu, and a laminated film thereof.

Next, FIGS. 4D and 4D show a top view and a cross section B, respectively.
FIG. As shown in FIG. 4D, a silicon oxide film is deposited as an interlayer insulating film 116 by using a CVD method or the like. Next, the second region formed in the source and drain diffusion regions
First and second main electrodes 111 and 112 and the buried gate electrode
A predetermined portion on 115 is patterned to open a contact hole. Subsequently, by selectively forming a conductive material such as W, source, gate, and drain wiring electrodes 117 are formed, and a MOS transistor is formed. The conductive material forming the wiring electrode 117 is not particularly limited.

In the manufacturing method, the order of forming the main electrode and the buried gate electrode, the etching conditions, the timing of removing the resist, and the like are not particularly limited, and the manufacturing can be performed by freely selecting a normal process. Further, another process such as formation of a multilayer wiring by a contact may be additionally performed.

In the MOS transistor formed in FIG. 4D, the main current is distributed over the channel width W in the depth direction of the buried gate electrode 115. That is, the direction in which the main current flows is perpendicular to the surface of the semiconductor substrate, and the direction of distribution is perpendicular to the surface of the semiconductor substrate. With such a structure, the channel width can be arbitrarily selected without being restricted by the chip area. Therefore, it is possible to realize reduction in channel resistance, improvement in transistor driving capability, prevention of transistor characteristic deterioration due to a narrow channel effect, and the like, which enable high speed and low power consumption without hindering high integration. A semiconductor device and a method for manufacturing the same can be provided.

Further, SOI is applied in a direction parallel to the surface of the semiconductor substrate.
Since the structure has a structure, it is possible to reduce the connection capacitance between the first and second main electrode regions and the first and second main electrodes, and to achieve higher speed.

Therefore, by applying the present embodiment, it is possible to provide a semiconductor device which can achieve high integration, high speed, low power consumption, and can improve the transistor driving capability. . (Second Embodiment) In the present embodiment, a NOR circuit composed of two n-type MOS transistors described in the first embodiment will be described. A detailed description of the transistor and the method of manufacturing the same portion as those in the first embodiment will be omitted to avoid duplication.

FIG. 5A is a top view of a MOS transistor, and FIG.
FIG. 6A is a cross-sectional view of the MOS transistor in section A, and FIG. 6C is a cross-sectional view of the MOS transistor in section B. FIG. 6D shows an equivalent circuit thereof.

As shown in FIGS. 5A to 6C, as in the first embodiment, element isolation, ion implantation, and R
Perform IE etching and the like, and first and second
First and second n ⁺ diffusion regions 107 and 108 to be main electrode regions of
Then, a p ^- diffusion region 105 serving as a gate electrode region is formed. Next, after forming the first and second main electrodes 111 and 112 so that at least a part thereof respectively covers the first and second n ⁺ diffusion regions 107 and 108, two buried gate electrodes are formed. I do.

The first buried gate electrode 115 is formed so that a part of the first buried gate electrode 115 covers the p ⁻ diffusion region 105 in each of the element forming regions 103. In the formation region 103, the buried gate electrode 115 is formed at a position substantially line-symmetric with respect to the cross section B.
That is, the embedded gate electrodes 115 and 201 are connected to the first
And two second main electrodes 111 and 112 are arranged side by side in parallel. By forming in this manner, a MOS transistor circuit including two MOS transistors can be formed.

An equivalent circuit of this MOS transistor circuit is shown in FIG.
This is shown in FIG. 6 (d). This MOS transistor circuit consists of two MOS transistors.
If at least one of the transistors A and B turns ON, V
_in= V_{o ut}And can be used as an OR circuit or NOR circuit.
Wear. In this embodiment, an n-type MOS transistor is used.
However, the configuration is the same even if a p-type MOS transistor is used.
Can be configured using p-type MOS transistors
Can be used as an OR circuit or a NOR circuit.
You.

In the MOS transistors in the MOS transistor circuits shown in FIGS. 5A to 6C, the main current is
The buried gate electrodes 115 and 201 are distributed over a channel width W in the depth direction. That is, the direction in which the main current flows is perpendicular to the surface of the semiconductor substrate, and the direction of distribution is perpendicular to the surface of the semiconductor substrate. With such a structure, the channel width can be arbitrarily selected without being restricted by the chip area. Therefore,
Without hindering high integration, it is possible to realize a reduction in channel resistance, an improvement in transistor driving capability, a prevention of transistor characteristic deterioration due to a narrow channel effect, and the like, which enable high speed and low power consumption.

Further, by configuring a circuit by combining MOS transistors, high integration, high-speed operation and low power consumption of the arithmetic circuit are realized, and the driving capability of the transistor is improved. It is possible to provide a semiconductor device and a method for manufacturing the same, which can reduce transmission errors and further improve the reliability of a semiconductor device.

Therefore, by applying the present embodiment, it is possible to provide a semiconductor device which can achieve high integration, high speed and low power consumption, and can improve the transistor driving capability. . (Third Embodiment) In the present embodiment, a NOR circuit composed of two n-type MOS transistors described in the first embodiment will be described. A detailed description of a transistor and a method of manufacturing the same portion of the same portions as those of the first and second embodiments will be omitted to avoid duplication.

FIG. 7A is a top view of a MOS transistor, and FIG.
FIG. 8C is a cross-sectional view of the MOS transistor in section A, and FIG. 8C is a cross-sectional view of the MOS transistor in section B. FIG. 8D shows an equivalent circuit thereof.

As shown in FIGS. 7A to 8C, first,
A thick silicon oxide film 102 on an arbitrary region on a semiconductor substrate 101
Are formed to form two element formation regions 103 and an element isolation region 104. The width of the element isolation region 104 that separates the two element formation regions 103 is not particularly limited, and may be about 0.1 μm.

Next, ion implantation, RIE etching and the like are performed in the same manner as in the first and second embodiments to form first and second main electrode regions in the two element forming regions 103, which are first and second main electrode regions. Second n ⁺ diffusion regions 107 and 108 and p ⁻ diffusion region 105 serving as a buried gate electrode region are formed, respectively. 1st and 2nd
After the main electrodes 111 and 112 are formed so that at least a part thereof respectively covers the first and second n ⁺ diffusion regions 107 and 108, two buried gate electrodes are formed.

The two buried gate electrodes 115 and 201 are formed so that a part thereof covers the p ^- diffusion region 105 in each of the element formation regions 103. It is not limited. That is, two buried gate electrodes 115 and 201 are formed between the first and second main electrodes 111 and 112 in parallel.

By forming in this manner, two M
A MOS transistor circuit including an OS transistor can be formed. FIG. 8D shows an equivalent circuit of this MOS transistor circuit. In this MOS transistor circuit, at least one of the two MOS transistors A and B has
By performing the ON operation, V _in = V _out , and the circuit can be used as an OR circuit or a NOR circuit. In this embodiment mode, an n-type MOS transistor is used. However, a p-type MOS transistor can be used in the same manner, and a p-type MOS transistor can be used as an OR circuit or a NOR circuit. It becomes possible.

In the MOS transistors in the MOS transistor circuits shown in FIGS. 7A to 8C, the main current is
The buried gate electrodes 115 and 201 are distributed over a channel width W in the depth direction. That is, the direction in which the main current flows is perpendicular to the surface of the semiconductor substrate, and the direction of distribution is perpendicular to the surface of the semiconductor substrate. With such a structure, the channel width can be arbitrarily selected without being restricted by the chip area. Therefore,
Without hindering high integration, it is possible to realize a reduction in channel resistance, an improvement in transistor driving capability, a prevention of transistor characteristic deterioration due to a narrow channel effect, and the like, which enable high speed and low power consumption.

Further, by forming a circuit by combining MOS transistors, high integration, high-speed operation and low power consumption of the arithmetic circuit are realized, and the driving capability of the transistor is improved, so that the signal It is possible to provide a semiconductor device and a method for manufacturing the same, which can reduce transmission errors and further improve the reliability of a semiconductor device.

Further, since the formation region of the two MOS transistors is separated by the element isolation region, it is possible to prevent a malfunction of a signal generated when the channels of the two MOS transistors overlap during the operation of the transistor circuit. The degree of freedom and reliability of designing the transistor circuit such as the magnitude of the voltage and the size of the transistor are increased. Also,
Because the structure has an SOI structure in a direction parallel to the surface of the semiconductor substrate, it is possible to reduce the connection capacitance between the first and second main electrode regions and the first and second main electrodes, It is possible to further increase the speed.

Therefore, by applying the present embodiment, high integration, high speed, and low power consumption can be achieved, the transistor driving capability can be improved, and the degree of freedom and reliability of circuit design can be improved. And a semiconductor device that can perform the above. (Fourth Embodiment) In this embodiment, the n-type MOS transistor and the p-type MOS transistor described in the first embodiment are used.
A transmission gate circuit configured using two MOS transistors of a type transistor will be described. A detailed description of a transistor and a method of manufacturing the same part of the same portion as in the first to third embodiments will be omitted to avoid duplication.

FIG. 9A is a top view of a MOS transistor, and FIG.
FIG. 10A is a sectional view of the MOS transistor in section A, and FIG. 10C is a sectional view of the MOS transistor in section B. Also,
FIG. 10D shows an equivalent circuit thereof.

As shown in FIGS. 9A to 10C, first,
A thick silicon oxide film 102 on an arbitrary region on a semiconductor substrate 101
Are formed to form two element formation regions 103 and an element isolation region 104. The width of the element isolation region 104 that separates the two element formation regions 103 is not particularly limited, and may be about 0.1 μm. Next, ion implantation, RIE etching, or the like is performed to form the first and second n ⁺ diffusion regions 107 and 108 or the first and second n ⁺ diffusion regions 107 in the two element formation regions 103 as first and second main electrode regions. Is formed in each of the p ⁺ diffusion regions 401 and 402.

Further, a p ^- diffusion region 105 or an n ^- diffusion region 403 to be a buried gate electrode region is formed. When the buried gate electrode region is the p ^- diffusion region 105, the n-type MO
When an S transistor is configured and the gate electrode region is the n ⁻ diffusion region 403, a p-type MOS transistor is configured. Next, after the first and second main electrodes 111 and 112 are formed so that at least a part thereof respectively covers the first and second n ⁺ diffusion regions 107 and 108, two embedded gate electrodes are formed. Form.

The two buried gate electrodes 115 and 201 are formed so that a part thereof respectively covers the p ^- diffusion region 105 or the n ^- diffusion region 403 in each of the element formation regions 103, and is viewed from above. The formation position when it is formed is not particularly limited. That is, the buried gate electrode
Two of 115 and 201 are formed between the first and second main electrodes 111 and 112 in parallel.

By forming in this manner, two M
A MOS transistor circuit including an OS transistor can be formed. FIG. 10D shows an equivalent circuit of this MOS transistor circuit. This MOS transistor circuit is a gate circuit for opening and closing signal transmission by an external control signal, that is, a transmission gate circuit.

In the MOS transistors in the MOS transistor circuits formed in FIGS. 9A to 10C, the main current is distributed over the channel width W in the depth direction of the buried gate electrodes 115 and 201. are doing. That is, the direction in which the main current flows is perpendicular to the surface of the semiconductor substrate, and the direction of distribution is perpendicular to the surface of the semiconductor substrate. With such a structure, the channel width can be arbitrarily selected without being restricted by the chip area. Therefore, it is possible to realize reduction in channel resistance, improvement in transistor driving capability, prevention of transistor characteristic deterioration due to a narrow channel effect, and the like, which enable high speed and low power consumption without hindering high integration. .

Further, by forming a circuit by combining MOS transistors, high integration, high-speed operation and low power consumption of the arithmetic circuit are realized, and the driving capability of the transistor is improved. It is possible to provide a semiconductor device and a method for manufacturing the same, which can reduce transmission errors and further improve the reliability of a semiconductor device.

Further, since the formation region of the two MOS transistors is separated by the element isolation region, it is possible to prevent a malfunction of a signal generated due to the overlap of the channels of the two MOS transistors during the operation of the transistor circuit. The degree of freedom and reliability of designing the transistor circuit such as the magnitude of the voltage and the size of the transistor are increased.

Further, SOI is applied in the direction parallel to the surface of the semiconductor substrate.
Since the structure has a structure, the connection capacitance between the first and second main electrode regions and the first and second main electrodes can be reduced, and the speed can be further increased.

Therefore, by applying the present embodiment, it is possible to achieve high integration, high speed, and low power consumption, improve the transistor driving capability, and improve the degree of freedom and reliability of circuit design. And a semiconductor device that can perform the above. (Fifth Embodiment) In this embodiment, the n-type MOS transistor and the p-type MOS transistor described in the first embodiment are used.
An inverter circuit configured using two MOS transistors of a type transistor will be described. The detailed description of the transistor and the method for manufacturing the same portion as those in the first to fourth embodiments will be omitted to avoid duplication.

FIG. 11A is a top view of a MOS transistor.
(b) is a cross-sectional view of the MOS transistor in cross-section A, FIG.
A cross-sectional view of the MOS transistor at cross section B is shown in FIG. FIG. 12D shows an equivalent circuit thereof.

As shown in FIGS. 11A to 12C, first, a thick silicon oxide film 102 is formed in an arbitrary region on a semiconductor substrate 101, and two element formation regions 103 and an element isolation region 1 are formed.
Form 04. The width of the element isolation region 104 that separates the two element formation regions 103 is not particularly limited, and may be about 0.1 μm.

Next, ion implantation, RIE etching and the like are performed to form the first and second n ⁺ diffusion regions 107 and 108 or the first and second n ⁺ diffusion regions 107 in the two element forming regions 103 as first and second main electrode regions.
And either one of the second p ⁺ diffusion regions 401 and 402 is formed. Also, a p ^- diffusion region 105 serving as a gate electrode region
Alternatively, an n ^- diffusion region 403 is formed. When the gate electrode region is the p ^- diffusion region 105, an n-type MOS transistor is formed, and when the gate electrode region is the n ^- diffusion region 403, a p-type MOS transistor is formed.

Next, first and second main electrodes 111 and 112 are provided outside the element forming region 103 where the n-type MOS transistor is formed, at least a part of which is the first and second main electrodes 111 and 112.
Of n ⁺ diffusion regions 107 and 108. Further, the element forming region 10 in which the p-type MOS transistor is formed
The third and fourth main electrodes 501, 502 on the outside of 3 respectively.
Wherein at least a part thereof is the first and second p ⁺ diffusion regions.
It is formed so as to cover 401 and 402.

Subsequently, one buried gate electrode 503 is formed. The buried gate electrode 503 is a p ^- diffusion region 105 or an n ^- diffusion region 403 which is to be a buried gate electrode region.
Then, it is formed so that a part thereof is applied.

By forming in this manner, two M
A MOS transistor circuit including an OS transistor can be formed. FIG. 12D shows an equivalent circuit of this MOS transistor circuit. This MOS transistor circuit is an inverter circuit that inverts a signal.

In the MOS transistors in the MOS transistor circuits shown in FIGS. 11A to 12C, the main current is distributed over the channel width W in the depth direction of the buried gate electrode 501. I have. That is, the direction in which the main current flows is perpendicular to the surface of the semiconductor substrate, and the direction of distribution is perpendicular to the surface of the semiconductor substrate. With such a structure, the channel width can be arbitrarily selected without being restricted by the chip area. Therefore, it is possible to realize reduction in channel resistance, improvement in transistor driving capability, prevention of transistor characteristic deterioration due to a narrow channel effect, and the like, which enable high speed and low power consumption without hindering high integration. .

Further, by configuring a circuit by combining MOS transistors, high integration, high-speed operation and low power consumption of the arithmetic circuit are realized, and the driving capability of the transistor is improved. It is possible to provide a semiconductor device and a method for manufacturing the same, which can reduce transmission errors and further improve the reliability of a semiconductor device.

Further, since the formation region of the two MOS transistors is separated by the element isolation region, it is possible to prevent a malfunction of a signal generated due to the overlap of the channels of the two MOS transistors during the operation of the transistor circuit. The degree of freedom and reliability of designing the transistor circuit such as the magnitude of the voltage and the size of the transistor are increased.

Further, SOI is applied in a direction parallel to the surface of the semiconductor substrate.
Since the structure has a structure, the connection capacitance between the first and second main electrode regions and the first and second main electrodes can be reduced, and the speed can be further increased. Therefore, by applying this embodiment, it is possible to achieve high integration, high speed, and low power consumption, to improve the transistor driving capability, and to improve the degree of freedom and reliability of circuit design. Semiconductor device can be provided.

As described above, in the first to fifth embodiments,
As described above, the application of the present invention is not limited to the MOS transistor, but can be applied to a bipolar transistor or a junction field effect transistor. That is, the main electrode region may be an emitter region and a collector region, or a cathode region and an anode region, and the gate electrode may be a base electrode.

[0092]

As described in detail above, according to the present invention,
It is possible to provide a semiconductor device and a method of manufacturing the same, which can freely select a channel width without being limited by a chip area. Therefore, by applying the present invention, reduction in channel resistance, improvement in transistor driving capability, and prevention of transistor characteristic deterioration due to a narrow channel effect can be achieved without increasing high integration, thereby enabling high speed and low power consumption. Can be realized.

Further, by configuring a circuit using a semiconductor device to which the present invention is applied, it is possible to achieve high integration, high speed, and low power consumption of the circuit, and to further improve the characteristics and reliability of the operation. A circuit can be provided.

[Brief description of the drawings]

FIGS. 1A and 1B are a partial top view and a partial sectional view showing steps of a semiconductor device and a method of manufacturing the same according to a first embodiment of the present invention.

FIGS. 2A and 2B are a partial top view and a partial cross-sectional view illustrating steps of a semiconductor device and a method of manufacturing the same according to the first embodiment of the present invention. FIGS.

3A and 3B are a partial top view and a partial cross-sectional view illustrating steps of a semiconductor device and a method of manufacturing the same according to the first embodiment of the present invention.

FIG. 4 is a partial top view and a partial cross-sectional view showing steps of a semiconductor device and a method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 5 is a partial top view and a partial cross-sectional view illustrating a semiconductor device according to a second embodiment of the present invention.

FIG. 6 is a partial cross-sectional view showing a semiconductor device according to a second embodiment of the present invention and an equivalent circuit thereof.

FIG. 7 is a partial top view and a partial cross-sectional view illustrating a semiconductor device according to a third embodiment of the present invention.

FIG. 8 is a partial cross-sectional view showing a semiconductor device according to a third embodiment of the present invention and an equivalent circuit thereof.

FIG. 9 is a partial top view and a partial cross-sectional view illustrating a semiconductor device according to a fourth embodiment of the present invention.

FIG. 10 is a partial cross-sectional view showing a semiconductor device according to a fourth embodiment of the present invention, and an equivalent circuit thereof.

FIG. 11 is a partial top view and a partial cross-sectional view illustrating a semiconductor device according to a fifth embodiment of the present invention.

FIG. 12 is a partial cross-sectional view showing a semiconductor device according to a fifth embodiment of the present invention and an equivalent circuit thereof.

FIG. 13 is a partial top view and a partial cross-sectional view showing steps of a conventional semiconductor device and a method of manufacturing the same.

14A and 14B are a partial top view and a partial cross-sectional view illustrating steps of a conventional semiconductor device and a method of manufacturing the same.

FIG. 15 is a partial top view and a partial cross-sectional view showing steps of a conventional semiconductor device and a method of manufacturing the same.

[Explanation of symbols]

101: semiconductor substrate, 102: silicon oxide film, 103: element formation region, 104: element isolation region, 105: p ^- diffusion region, 106 ...
Resist pattern, 107 ... first n ⁺ diffusion region, 108 ... second
n ⁺ diffusion region, 109: first main electrode groove, 110: second main electrode groove, 111: first main electrode, 112: second main electrode, 113: gate groove, 114: gate insulating film, 115 ... buried gate electrode,
116 ... interlayer insulating film, 117 ... wiring electrode, 201 ... buried gate electrode, 401 ... first p ⁺ diffusion region, 402 ... second p ⁺ diffusion region, 403 ... n ^- diffusion region, 501 ... third main Electrode, 502: fourth main electrode, 503: embedded gate electrode, 601: semiconductor substrate,
602: silicon oxide film, 603: element formation region, 604: element isolation region, 605: gate insulating film, 606: barrier metal, 60
7… n ⁺ diffusion region, 608… interlayer insulating film, 609… wiring electrode

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 29/417 H01L 29/50 U 29/78 301H 301X F term (Reference) 4M104 BB01 BB04 BB13 BB14 BB24 CC01 CC05 FF18 FF27 GG09 GG10 GG14 5F040 DA01 DA02 DA12 DA22 DB01 DB03 DC01 EA09 EC02 EC04 EC20 EC26 ED04 EE02 EE04 EH01 EH02 EH03 EH07 EJ03 EK01 EK05 FC10 5F048 AA01 AB03 AC01 BA01 BB19 BD05 BD06 BG14

Claims (9)

[Claims] An element formation region provided on a substrate or a well; and a device formation region provided at a distance from the element formation region and having an impurity of a carrier type opposite to the substrate or the well introduced therein.
A first and a second main electrode diffusion region, a first main electrode provided so as to at least partially hang over the first main electrode diffusion region, and at least a part of the second main electrode diffusion region A second main electrode provided so as to hang, and a buried gate electrode provided so as to at least partially hang between the first and second main electrode diffusion regions in the element formation region. A semiconductor device characterized by the above-mentioned. 2. A direction of a main current component controlled by the buried gate electrode in a main current flowing between the first and second main electrode diffusion regions is substantially parallel to a surface of the element formation region. 2. The semiconductor device according to claim 1, wherein the direction of distribution of the main current is substantially perpendicular to the surface of the element formation region. A first element formation region and a second element formation region provided on a substrate or a well, and the substrate or the well provided apart from a part of the first element formation region; First and second main electrode diffusion regions into which impurities of the opposite carrier type have been introduced, and a carrier type opposite to the substrate or the well, provided at a distance from a part of the second element formation region. Third and fourth main electrode diffusion regions into which the first impurity is introduced, and a first main electrode provided so as to at least partially overlap the first main electrode diffusion region and the third main electrode diffusion region. An electrode, a second main electrode provided so as to at least partially overlap the second main electrode diffusion region and the fourth main electrode diffusion region, and the first main electrode in the first element formation region. A second main electrode diffusion region provided at least partially between
A first buried gate electrode and a third buried electrode provided so that at least part of the buried gate electrode hangs between the third and fourth main electrode diffusion regions in the second element formation region
A semiconductor device comprising: two embedded gate electrodes. 4. The first or second buried gate of a main current flowing between the first and second main electrode diffusion regions and a main current flowing between the third and fourth main electrode diffusion regions. The direction of the component of the main current controlled by the electrode is substantially parallel to the surface of the first or second element formation region,
4. The semiconductor device according to claim 3, wherein the direction of distribution of the main current is substantially perpendicular to the surface of the first or second element formation region. 5. A first device provided on a substrate or a well.
The first and second element formation regions and the second element formation region are provided separately from each other in a part of the first element formation region, and an impurity of a carrier type opposite to the substrate or the well is introduced. A second main electrode diffusion region, and a third and a fourth main electrode diffusion region which is provided at a part of the second element formation region and is separated by an impurity of a carrier type opposite to the substrate or the well. A region, a first main electrode provided at least partially over the first main electrode diffusion region, and a second main electrode provided at least partially over the second main electrode diffusion region. A main electrode, a third main electrode provided so as to cover at least part of the third main electrode diffusion region, and a third main electrode provided so as to cover at least part of the fourth main electrode diffusion region. A fourth main electrode; and the first and second electrodes in the first element formation region. And a buried gate electrode provided so as to at least partially overlap between the main electrode diffusion regions and between the third and fourth main electrode diffusion regions in the second element formation region. Semiconductor device. 6. A main current controlled by the buried gate electrode, of a main current flowing between the first and second main electrode diffusion regions and a main current flowing between the third and fourth main electrode diffusion regions. The direction of the current component is substantially parallel to the surface of the first or second element formation region, and the direction of the main current distribution is substantially perpendicular to the surface of the first or second element formation region. 6. The semiconductor device according to claim 5, wherein 7. A step of forming a thin insulating film in a first region on a substrate to form an element forming region, and forming a thick insulating film in a region other than the element forming region to form an element isolating region. Forming a mask pattern in a part of the element forming region, and introducing an impurity of a carrier type opposite to a substrate or a well using the mask pattern as a mask, thereby forming the first and second main electrodes. Forming a diffusion region at a distance; at least a part of the first main electrode diffusion region; and
By selectively forming a conductive material in at least a part of the main electrode diffusion region of each of the first and second main electrode diffusion regions,
Forming a main electrode, forming a gate groove in a part of the region where the mask pattern is formed by etching, and forming a gate insulating film on a side wall and a bottom of the gate groove. Forming a buried gate electrode by burying a conductive material in the gate groove in which the gate insulating film is formed on a side wall and a bottom; and forming the buried gate electrode,
Forming an insulating film on the element formation region including the first and second main electrodes, and forming an opening by exposing surfaces of the buried gate electrode and the first and second main electrodes; Forming a contact by selectively forming a conductive material in the portion. 8. A step of forming a thin insulating film in a first region and a second region on a substrate to form a first element forming region and a second element forming region; Forming a thick insulating film in a region other than the device formation region to form a device isolation region; forming a first mask pattern in a part of the first device formation region, and opposing a substrate or a well. A step of forming the first and second main electrode diffusion regions apart from each other by introducing impurities of the carrier type using the first mask pattern as a mask; Forming a second mask pattern on the portion and introducing an impurity of a carrier type opposite to that of the substrate or the well using the second mask pattern as a mask, thereby separating the third and fourth main electrode diffusion regions. Forming, and the first main electrode diffusion Forming a first main electrode by selectively forming a conductive material in a region and a partial region of the third main electrode diffusion region; andthe second main electrode diffusion region and the fourth main electrode diffusion region. Forming a second main electrode by selectively forming a conductive material on a part of the main electrode diffusion region; and forming a second mask pattern on the first mask pattern and the second mask pattern. Forming a first and a second gate groove in each of the partial regions by etching; forming a gate insulating film on a side wall and a bottom of the first and second gate grooves; And wherein the gate insulating film is formed on the bottom
Forming a first and second buried gate electrodes by burying a conductive material in the first and second gate trenches; andthe element isolation region, the first and second buried gate electrodes, the first and second buried gate electrodes, Forming an insulating film on the element formation region including a second main electrode, the first and second buried gate electrodes, the first and second
Forming an opening by exposing the surface of the main electrode, and forming a contact by selectively forming a conductive material in the opening, the method of manufacturing a semiconductor device. 9. forming a first element forming region and a second element forming region by forming a thin insulating film in a first region and a second region on a substrate; and forming the first and second element forming regions. Forming a thick insulating film in a region other than the device formation region to form a device isolation region; and forming a first mask pattern in a part of the first device formation region and opposing a substrate or a well. A step of forming the first and second main electrode diffusion regions apart from each other by introducing impurities of the carrier type using the first mask pattern as a mask; Forming a second mask pattern on the portion and introducing an impurity of a carrier type opposite to that of the substrate or the well using the second mask pattern as a mask, thereby separating the third and fourth main electrode diffusion regions. Forming, and the first to fourth main Forming a first to a fourth main electrode by selectively forming a conductive material in a part of the pole diffusion region; and forming the first mask pattern and the second mask pattern. A step of forming one gate groove by etching in a part of the formed area; a step of forming a gate insulating film on a side wall and a bottom of the gate groove; and a step of forming the gate insulating film on a side wall and a bottom. A step of forming a buried gate electrode by burying a conductive material in the formed gate groove; and forming the buried gate electrode;
Forming an insulating film over the element formation region including the first to fourth main electrodes; forming an opening by exposing surfaces of the buried gate electrode and the first to fourth main electrodes; Forming a contact by selectively forming a conductive material in the portion.