JP2002185989A - Method and device for accommodating subscriber circuit - Google Patents

Method and device for accommodating subscriber circuit

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Publication number
JP2002185989A
JP2002185989A JP2000374389A JP2000374389A JP2002185989A JP 2002185989 A JP2002185989 A JP 2002185989A JP 2000374389 A JP2000374389 A JP 2000374389A JP 2000374389 A JP2000374389 A JP 2000374389A JP 2002185989 A JP2002185989 A JP 2002185989A
Authority
JP
Japan
Prior art keywords
transmission
subscriber
circuit
transmission rate
time domain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000374389A
Other languages
Japanese (ja)
Inventor
Yutaka Fukushima
Hironobu Kashiwagi
Katsumi Nagumo
Yumiko Nishi
Yoichi Tsukioka
克美 南雲
陽一 月岡
博信 柏樹
豊 福島
由美子 西
Original Assignee
Hitachi Ltd
株式会社日立製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, 株式会社日立製作所 filed Critical Hitachi Ltd
Priority to JP2000374389A priority Critical patent/JP2002185989A/en
Publication of JP2002185989A publication Critical patent/JP2002185989A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To efficiently accommodate a plurality of subscriber circuits different in transmission rate in a common data bus transmitting system where a higher rank circuit accommodating the subscriber circuits and the subscriber circuit perform one to M transmission. SOLUTION: When the higher rank circuit 10 accommodating the subscriber circuits 11 and the subscriber circuits 11a to 11m realize one to M (M is an integer of >=1) signal transmission through a common data bus 12 using time division, the time area that is previously allocated is band-expanded only in the pertinent time area by increasing a clock frequency, thus the subscriber circuit having the plural types of transmission speeds can be accommodated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication apparatus, and more particularly, to a subscriber circuit accommodating apparatus or the like, in which a high-order circuit accommodating a subscriber circuit and a subscriber circuit use a common data bus to provide one-to-M communication. (M is an integer of 1 or more) The present invention relates to a subscriber circuit accommodating method for realizing communication and an apparatus using the method.

[0002]

2. Description of the Related Art FIGS. 1A and 1B show a conventional subscriber circuit accommodating method in the prior art. In the prior art, the upper circuit 10 accommodating the subscriber circuit and the subscriber circuit 1 are provided.
1a to 11m (maximum M) is a one-to-M transmission method, and in order to realize information transmission of N bits / frame per subscriber, at least M × N bits
/ Frame common data bus 12 in the time domain
The division is performed, and a frame pulse indicating each time domain is allocated to each subscriber circuit, and each subscriber circuit 11 is realized by recognizing a time domain used by itself. This transmission method can be realized by the same method as the transmission path in both the upstream and downstream directions.

[0003]

In recent years, it has become essential to increase the transmission speed of an access system or a relay system, and in an arbitrary subscriber circuit, a higher-speed subscriber than a conventional one in accordance with a request of the subscriber is required. It is desired to accommodate the circuit of the user.

However, the conventional method is based on the premise that the time domain corresponding to each subscriber circuit has a constant transmission rate (Nbit / frame), and accommodates a subscriber circuit having a transmission rate higher than the conventional one. In such a case, a plurality of unit time areas must be occupied, and transmission information must be collectively assigned to the unit time areas.

As a result, the method of allocating the unit time area to each subscriber circuit on the common data bus becomes complicated, and
The number of subscriber circuits that can be accommodated is greatly reduced by accommodating high-speed subscriber circuits, and a reduction in mounting efficiency is inevitable.

The present invention has been made in view of the above points, and has as its object to provide a method for accommodating a subscriber circuit capable of accommodating a subscriber circuit having a higher transmission rate than the conventional method and a method thereof. It is to provide a device used.

Another object of the present invention is to inherit the conventional method of allocating the unit time area allocated on the common data bus to the subscriber circuits on a one-to-one basis, and then, for each subscriber circuit, An object of the present invention is to realize a transmission rate changing process without affecting other subscriber circuits.

[0008]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a method for connecting between M (M is an integer of 1 or more) subscriber circuits and a higher-level circuit accommodating the M subscriber circuits. 1: a common data bus used for M signal transmission, in a subscriber circuit accommodating method for accommodating M subscriber circuits using a time division method, the subscriber circuits are assigned to the M subscriber circuits. In a time domain corresponding to at least one subscriber circuit j (j is an arbitrary integer) of the M time domains, a first clock frequency used for signal transmission is set to a time domain corresponding to another subscriber circuit. Is set to k times (k is an integer of 2 or more) the second clock frequency used in.

Further, in order to achieve the above object, the present invention is used in 1: M signal transmission performed between M subscriber circuits and an upper circuit accommodating the M subscriber circuits. In a subscriber circuit accommodating method for accommodating M subscriber circuits using a time division method on a common data bus, at least one subscriber among M time domains assigned to the M subscriber circuits is provided. In the time domain corresponding to circuit j,
The number of signal voltage levels used for signal transmission is 2 k .

In the subscriber circuit accommodating method according to the present invention, a predetermined number of bits in a time domain corresponding to the subscriber circuit j are determined by a predetermined bit for indicating a transmission rate to be used in the time domain. It may be configured to be used as a transmission rate notification bit for setting a pattern. Further, a predetermined number of bits in a time domain corresponding to the subscriber circuit j are used for a transmission rate trial for testing whether a target transmission rate desired to be used in the time domain can be recognized on a transmission / reception side. It is good also as a structure used as a bit.

Further, in order to achieve the above object, the present invention provides a high-order circuit for accommodating a plurality of subscriber circuits using a time division method, which is used for signal transmission in each time domain corresponding to each subscriber circuit. A transmitting / receiving unit capable of setting a plurality of clock frequencies or signal voltage levels to be set, and a clock frequency or signal voltage level number to be used in a time domain corresponding to a specific subscriber circuit; A selection unit that selects from the number of voltage levels and controls the transmission / reception unit such that the selected clock frequency or the number of signal voltage levels is used in the time domain.

Further, in order to achieve the above object, the present invention relates to a subscriber circuit among a plurality of subscriber circuits accommodated in one higher-level circuit using a time division method.
A transmission / reception unit for performing signal transmission using a clock frequency or a signal voltage level different from that of another subscriber circuit accommodated in the one subscriber circuit, and a clock frequency or signal used by the subscriber circuit for signal transmission A transmission rate notification unit that sets a bit pattern indicating the number of voltage levels for a predetermined number of bits in a time domain assigned to the subscriber circuit;

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present invention, the conventional method of assigning a unit time area to a subscriber circuit on a one-to-one basis is inherited. By transmitting the high-density information by partially increasing the transmission rate for each unit time area, it is possible to smoothly change the transmission rate for each subscriber circuit without affecting other subscriber circuits. ing.

In the first embodiment of the present invention, the first circuit is used for 1: M signal transmission between an upper circuit (one circuit) accommodating a subscriber circuit and M (M is an integer of 1 or more) subscriber circuits. In a subscriber circuit accommodating method for accommodating M subscriber circuits by using a time division method or the like on a common data bus, a transmitting side sets a clock frequency higher than usual for each time area allocated to each subscriber. The signal is transmitted by raising k times (k is an arbitrary positive integer) and the receiving side synchronizes the receiving clock frequency with the receiving data transmission speed within a range from the basic speed to the maximum receivable transmission speed. , Each of the accommodated subscriber circuits independently realizes data transmission at an arbitrary transmission rate from the basic rate to k times the transmission rate.

In the second embodiment of the present invention, a single circuit is used for 1: M signal transmission between an upper circuit (one) accommodating a subscriber circuit and M (M is an integer of 1 or more) subscriber circuits. In a subscriber circuit accommodating method for accommodating M subscriber circuits using a time division method or the like on a common data bus, the resolution of the signal voltage level is changed over the entire variable range for each time region assigned to the subscriber. 2 k pieces (k non-overlapping each other with respect
Is set to an integer of 2 or more), and k-bit different bit patterns are assigned to each level on a one-to-one basis and signal transmission is performed. To data transmission at an arbitrary transmission rate from k to k times.

In the second embodiment, in the signal voltage level increased to the 2 k value, the bits are allocated so that the hamming distance between any adjacent levels is minimized. Thereby, the bit error rate when the received data is erroneously recognized as an adjacent signal voltage level may be minimized.

Further, by applying the first and second embodiments in combination, a configuration may be adopted in which the transmission speed of any subscriber circuit accommodated is improved.

In the first or second embodiment, a specific number of bits in the time domain allocated on the common data bus transmitted from the transmission side to the reception side are allocated as transmission rate notification bits, The transmitting side determines an appropriate transmission rate to be adopted, transmits a transmission rate notification bit pattern that allows the transmission rate to be uniquely recognized in response to the transmission rate notification bit, and the receiving side receives the bit pattern. Alternatively, the transmission speed adopted by the transmission side may be recognized by the reception side.

Here, in the case of the first embodiment, when generating a transmission rate notification bit pattern corresponding to the transmission rate for the transmission rate notification bit, the H / L level is used at the clock frequency of the employed transmission rate. A pattern in which the transmission rate is uniquely recognized may be included in a part or all of the transmission rate communication use bits by alternately repeating the pattern.

On the other hand, in the case of the second embodiment, when generating a transmission speed notification bit pattern corresponding to the transmission speed for the transmission speed notification bit, the resolution of the signal voltage level of the employed transmission speed is used. The transmission rate may be uniquely recognized by including the adjacent voltage level in part or all of the transmission rate notification bit.

In the first or second embodiment, a specific number of bits in the time domain allocated on the common data bus transmitted from the transmitting side to the receiving side are allocated as transmission rate response bits, The transmitting side has a bit pattern for a transmission rate response corresponding to the transmission rate employed when receiving data in the time domain of the common data bus in the reverse direction,
Alternatively, intentionally, the transmission side transmits a bit pattern for a transmission rate response corresponding to a desired specific transmission rate different from the transmission rate adopted at the time of reception, and the receiving side receives the bit pattern, thereby performing a reverse operation. It is also possible to adopt a configuration in which whether or not the data is correctly received at the transmission rate adopted in the time domain data transmission of the common data bus in the direction is recognized.

Here, in setting a bit rate notification / response bit pattern corresponding to an arbitrary transmission rate, F bit patterns capable of uniquely indicating a specific transmission rate (F is an arbitrary bit rate) (Integer), and may be configured to form a multi-frame of F period so as to reduce the required number of transmission rate notification / response bits by 1 / F.

Further, in setting the bit pattern for transmission rate notification / response, an individual line for transmission rate notification / response is prepared independently of the common data bus, and all exchanges of information related to transmission rate control are performed in this manner. It is also possible to adopt a configuration in which all the time domains of the common data bus are used for data transmission by processing with individual lines.

In the first or second embodiment, when realizing bi-directional transmission in an arbitrary time domain that is paired on a common data bus in both the upper and lower directions, one side is a master side and the other side is a slave side. Then, a transmission rate notification bit is allocated from the master side to the slave side (forward direction), and the master side arbitrarily determines the transmission rate in the forward time domain and transmits data. Sends out a bit pattern corresponding to that transmission rate,
The slave recognizes the transmission rate of the received data in the forward time domain from the received transmission rate notification bit,
The transmission speed in the time domain from the slave side to the master side (reverse direction) is also adjusted to the transmission speed in the forward direction, so that bidirectional data transmission is possible at the transmission speed assumed by the master side. Is also good.

Further, in the first or second embodiment, when realizing bidirectional transmission in an arbitrary time domain which is a pair on the common data bus in both the upper and lower directions, the transmission rate notifying bit is provided in each direction. The transmission side arbitrarily determines the transmission rate in the forward time domain and transmits the data, and transmits a bit pattern corresponding to the transmission rate to the transmission rate notification bit, and the receiving side transmits the received transmission rate. By recognizing the transmission speed of the received data from the speed notification bit, the transmission side may control the transmission speed in each direction independently to enable bidirectional data transmission.

Here, in response to the assigned transmission rate notification bits, transmission rate response bits are allocated in the opposite transmission direction, and the side receiving the transmission rate notification bit sets the recognized transmission rate to the recognized transmission rate. By transmitting the corresponding bit pattern using the transmission rate response bit, the transmission rate recognized by the reception side can be confirmed by the transmission side,
If necessary, the transmitting side may use the information as a condition for determining the transmission speed.

In addition to the transmission rate notification / response bit for controlling the existing transmission rate, the transmission rate notification / response bit is used for the purpose of testing the feasibility of an arbitrary transmission rate. By independently assigning, when changing the employed transmission rate, it is possible to try and confirm in advance whether or not transmission at the transmission rate to be changed is possible. It is good also as a structure which prevents a speed change beforehand.

Another embodiment of the present invention will be described with reference to FIGS.

The communication apparatus according to the present embodiment includes, for example, an upper circuit 10 as shown in FIG. 1A, subscriber circuits 11a to 11m accommodated in the upper circuit 10, and a common data bus connecting these circuits. 12 is provided. Here, it is assumed that a time region for M subscribers is bit-assigned to the common data bus 12 as shown in FIG.

In this embodiment, as shown in FIG. 1B, as means for partially increasing the transmission rate in each of the M divided time regions, the following two methods (A) and (A) are used. Use at least one of the types.

(A) The clock frequency is increased.

(A) The signal voltage level is changed from binary to multi-level.

In the means (A), for example, as shown in FIG. 1 (c), a clock frequency (basic speed) corresponding to N bits in a unit time area allocated to the subscriber's circuit is k times N × N bits. By increasing the speed to a considerable clock frequency, only a specific subscriber circuit (subscriber circuit j in this example) can transmit data by k times.

In realizing the above means (A), in addition to the specific subscriber circuit j side, the transmitting and receiving sides of the higher-level circuit 10 accommodating the subscriber circuit are previously set up from the basic speed frequency to the k-times clock frequency. Has a transmission / reception capability in which the range can be set arbitrarily.

In the above means (a), in the unit time domain, transmission / reception was performed at the binary level of H / L in the conventional method, whereas a specific subscriber circuit (subscriber in this example) as shown in FIG. By changing the voltage level at which only the circuit j) can transmit and receive data from binary to 2 k values, k-times data transmission is enabled.
Here, FIG. 2 (a) shows bit allocation in the time domain for M subscribers used in the above means (a), and FIG. 2 (b), FIG.
(C) shows an example of bit allocation in the time domain per subscriber to which the present means is applied, and distribution of voltage levels in the allocated bits, respectively.

In order to realize the above means (a), in addition to the specific subscriber circuit side, the transmitting and receiving sides of the higher-level circuit 10 accommodating the subscriber circuit have two transmission / reception capabilities in advance.
It is configured to have a resolution of k values. For example, as shown in FIG. 3, the voltage level is subdivided (2 k
Value), and all the k-bit bit patterns (2 k patterns) are assigned one-to-one to each of the subdivided voltage levels. Here, (3-1) of FIG. 3 shows the transmission level and the reception level when the basic rate is used, (3-2), (3-3).
Shows an example of the transmission level and the reception level when the double speed (k = 2) and the triple speed (k = 3) are used, respectively.

The above means (A) and (A) are basically means for independently improving the band. For this reason, it is good also as a structure which combines and applies both simultaneously.
By combining the two, the effect of improving both transmission speeds is exerted as a product of them, so that the transmission speed can be more efficiently improved.

By using the above means (A) and (A), the transmission rate of each subscriber circuit is inherited, while inheriting the conventional method of assigning the unit time area to the subscriber circuits on a one-to-one basis. The change processing can be realized smoothly without affecting other subscriber circuits.

Another embodiment of the present invention will be described with reference to FIGS.

In this embodiment, in the above embodiment,
By increasing the clock frequency in the means (A) and increasing the signal voltage level in the means (A),
In order to enable data transmission at an arbitrary transmission rate in a specific time region on the common data bus, means for agreeing on a transmission rate adopted by both the transmitting side and the receiving side shall be further provided.

For example, taking the case of the above means (A) as an example, in the present invention, in order to enable the receiving side to recognize the transmission rate applied by the transmitting side, the time domain allocated as shown in FIG. Are assigned as transmission rate notification bits. FIG. 4 shows an example in which the first to fourth bits are used as transmission rate notification bits.

On the other hand, the transmitting side of this embodiment transmits a specific bit pattern that can uniquely determine the applied transmission rate by using the transmission rate notification bit, and the receiving side transmits the received transmission rate notification bit. By interpreting the bits, the transmission side recognizes the transmission rate applied.

As a specific bit rate notifying bit pattern capable of uniquely determining the transmission rate, for example, as shown in FIG. 5, the bit rate is inverted alternately without taking a continuous value at a clock frequency corresponding to the adopted transmission rate. It is configured to take a pattern. Here, in FIG. 5A, since the transmission speed is a bit pattern for notification of the transmission speed corresponding to the basic speed, the received data is interpreted with a frequency clock of the transmission speed corresponding to the bit pattern. Similarly, when the transmission speed is doubled or quadrupled as shown in FIGS. 5B and 5C, the received data is interpreted at the transmission speed corresponding to the transmission speed notification bit pattern. Just do it.

Also, in the case of the means (a), similarly to the example of the means (a), a specific time is set so that the receiving side can recognize the transmission speed applied by the transmitting side. Several bits of a specific portion in the area are allocated as transmission rate notification bits. However, in this example, as shown in FIG. 6, a bit pattern is used such that the minimum value of the voltage level resolution corresponding to the transmission rate to be used is recognized for the bits assigned as the transmission rate notification bits. Constitute. Here, FIG. 6A shows a bit pattern for recognizing a binary voltage level when the basic speed is used, and FIGS. 6B and 6C each show a double speed (k = 2). 2) Bit patterns for recognizing 2 k voltage levels when using a triple speed (k = 3) are shown.

By using the transmission rate notification bit, even when a transmission / reception circuit that can handle only a specific transmission rate is used, the transmission capacity within a range of a fixed transmission rate notification bit time range. Transmission speed can be recognized.

Further, by using the above-mentioned bit pattern for transmission rate notification, it is possible to infinitely associate bit patterns with any transmission rate according to the transmission capacity.

Further, the transmission speed notification bit pattern can be used as a reference for the reception side to adjust the reception clock to the transmission speed.

FIGS. 7 to 9 show another embodiment of the present invention.
This will be described with reference to FIG.

In each of the above-described embodiments, when the transmission speed on the transmission side is higher than the transmission speed on the reception side, the transmission data may not be transmitted normally. The factors include, for example, a case where an error occurs in reading of received data, and a case where there is a bottleneck in the transmission speed in the transmission system at the subsequent stage on the receiving side. Therefore, the transmitting side recognizes the receiving state of the receiving side, so that the reliability of data transmission can be improved.

Therefore, in the present embodiment, as shown in FIG. 7, for example, several bits for transmission rate response are newly secured in addition to the bit for transmission rate notification. The example shown in FIG. 7 is an example in which the above-described means (a) is used. The first to fourth bits are used as transmission rate notification bits, and the fifth to eighth bits are used as transmission rate response bits. Is shown.

Further, in this embodiment, the receiving side of the forward common data bus has a transmission rate corresponding to the transmission rate employed for reception or, if necessary, the transmission rate requested by the receiving side to the transmitting side. The response bit pattern is
The transmission speed response bit on the common data bus in the reverse direction is described and returned. The transmission side in the forward common data bus can recognize whether the transmission information is normally received by the reception side by interpreting the transmission rate response bit returned from the reverse common data bus. it can.

As described above, by using the speed notification / response bit on the premise that the clock frequency is increased in the above means (A), it is possible to agree on the transmission speed adopted by both the transmitting side and the receiving side. Becomes Also, by replacing the clock frequency of the above-mentioned means with the signal voltage level, the multi-valued signal voltage level in the above-mentioned means (A) can be obtained in the same manner as in the above-mentioned means (A)
It is possible to agree on the transmission speed to be adopted by both the transmitting side and the receiving side.

Here, by occupying a part of the transmission data area as the transmission speed notification / response bit, the original data transmission efficiency is degraded. In particular, the above means (a)
In order to improve the transmission speed by multi-leveling the signal voltage level in the above, since the available bit width is constant,
In particular, deterioration in data transmission efficiency cannot be ignored.

Therefore, in the present embodiment, as a measure for minimizing the deterioration, a configuration may be adopted in which the number of bits allocated to the transmission rate notification / response bits is reduced. That is, multi-frame conversion is applied to the transmission rate notification / response bits.

For example, as shown in FIG.
In order to improve the transmission speed by multi-leveling the signal voltage level in (1), as shown in FIG. 8 (a), the bit pattern of the voltage level normally transmitted continuously in one frame is replaced with a necessary bit. Build a multi-frame of only a few minutes.
According to such a configuration, the resolution of the intended voltage level, that is, the transmission speed, can be transmitted to the receiving side only by assigning at most one bit as the transmission speed notification / response bit.

On the other hand, when the transmission speed is improved by increasing the clock frequency in the above means (A),
As shown in FIG. 8B, by forming a multi-frame in which the bits are inverted at a period proportional to the speed-up multiple, at most one bit is transmitted and transmitted as a transmission speed notification / response as in the case of FIG. 8A. By simply allocating the bits, it is possible to inform the receiving side of the intended transmission speed.

An example of a circuit configuration in which the transmission speed can be controlled bidirectionally independently using a bidirectional common data bus using the transmission speed notification bit / transmission speed response bit as described above. It is shown in FIG. In this example, a higher-level circuit 10 accommodating the subscriber circuits 11a to 11m serving as transmission sides is connected to a common data bus 12 and is a transmission / reception circuit 1 serving as a main body of the circuit.
01, a transmission speed loopback circuit 102, a transmission speed collation circuit 103, and a transmission speed selection circuit 104.
In addition, each of the subscriber circuits 11a to 11m on the receiving side in this example has the same configuration as the higher-level circuit 10. For example, the subscriber circuit 11a includes a transmission / reception circuit 111, a transmission speed loopback circuit 112, a transmission speed collation circuit 113, and a transmission speed selection circuit 114.

In the upper circuit 10 on the transmitting side, first, a bit rate notifying bit pattern corresponding to the transmission rate requested by the transmission rate selecting circuit 104 is described in a transmission rate notifying bit. The transmission speed set here may be configured to be determined independently by the transmitting side, or may be configured based on an instruction from a higher-level control circuit.

In the subscriber circuit 11 on the receiving side, the transmission speed notifying bit 112 transmitted via the common data bus 12 receives the transmission speed notification bit, and interprets the transmission speed of the received data. The transmission rate response bit pattern corresponding to the adopted transmission rate or, if necessary, the transmission rate requested by the receiving side is described in the transmission rate response bit of the transmission path in the reverse direction and returned.

In the upper circuit 10 on the transmission side, the transmission speed collation circuit 103 collates the transmission speed notification bit pattern transmitted by the transmission speed selection circuit 104 with the returned transmission speed response bit pattern. The comparison result is transmitted to the transmission speed selection circuit 104.

The transmission rate selection circuit 104 checks the reception state to see if the receiving side is receiving at the required transmission rate with reference to the received collation result. If the collation results are inconsistent, the transmitting side recognizes that the receiving side cannot receive at the current transmission rate for some reason, and notifies the transmitting / receiving circuit (main body) 101 of an instruction to change the transmission data format to low speed. Then, the transmission speed notification bit pattern is changed to a corresponding bit pattern.

Here, the upper circuit 10 accommodating the subscriber circuits 11a-11b is the transmitting side, and the subscriber circuits 11a-11
b shows a procedure for confirming / controlling the transmission rate on the receiving side, that is, the transmission path in the downstream direction, but the same procedure can be implemented in the reverse direction.

With the above-described circuit configuration, it is possible to confirm the communication state of the transmission rate applied to each subscriber circuit (whether the transmission state is normal or abnormal) and to control (reduce the transmission rate or, if the transmission state is abnormal, change the transmission rate). ) Can be realized at an arbitrary timing independently for uplink and downlink.

As described above, instead of using a multi-frame for the transmission speed notification / response bit pattern, an individual line for transmission speed notification / response is prepared independently of the common data bus, and the transmission speed control-related All information exchanges are processed by this individual line, so that the entire time domain of the common data bus may be used for data transmission.

Further, in the above-described embodiment, a configuration may be further provided in which means for enabling trial of transmission quality at a transmission rate different from the current state is provided.

For example, as in the case of the above embodiment, when only one set of the transmission rate notification bit and the transmission rate response bit exists, the transmission state is constantly monitored. There is no means to try the transmission quality. In particular, when increasing the transmission speed, suddenly changing to a different transmission speed may cause a problem in transmission quality. Therefore, in order to test the feasibility of changing the transmission rate, another set of transmission rate notification / response bits is prepared.

According to such a configuration, confirmation / control of the transmission state is realized by one set of the transmission rate notification / response bit, and when the transmission rate is changed, the other transmission rate notification / response is performed. Confirm that there is no problem in the transmission quality at the transmission speed required in advance with the set of response bits. As a result, the transmission speed can be changed while maintaining the transmission quality.

Here, the transmission rate notification bit /
The transmission rate response bit set should be added without changing the number of allocated bits by using an appropriate multi-frame configuration, such as transmitting the existing transmission rate notification bit / transmission rate response bit alternately. Needless to say, this is also possible.

[0069]

According to the present invention, in a common data bus communication system in which a higher-order circuit accommodating a subscriber circuit and the subscriber circuit perform one-to-M transmission, a new subscriber circuit realizing different transmission speeds can be set at any time. It can be accommodated in the area.

Further, according to the present invention, the upper circuit which accommodates the subscriber's circuit is changed in advance to one corresponding to the maximum transmission speed and interface conditions of the new subscriber's circuit. Basically inheriting the time domain division as it is and partially expanding the bandwidth for each time domain, without changing the hardware configuration of the transmission path as it is,
Also, transmission different from the existing subscriber's circuit without affecting the accommodation of other existing subscriber's circuits and without changing the interface conditions of the existing subscriber's circuit if the transmission is at the existing basic rate. It becomes possible to accommodate a new subscriber circuit of a speed in an arbitrary time domain.

[Brief description of the drawings]

FIG. 1A is a block diagram showing an example of a circuit configuration to which the present invention is applied. FIG. 1B: M on the common data bus of FIG.
FIG. 4 is an explanatory diagram showing bit allocation in a time domain for a subscriber. FIG. 1C is an explanatory diagram showing an example of bit allocation in the time domain per subscriber to which the present invention is applied.

FIG. 2A is an explanatory diagram showing bit allocation in a time domain for M subscribers on a common data bus to which the present invention is applied. FIG. 2B is an explanatory diagram showing an example of bit allocation in the time domain per subscriber to which the present invention is applied. FIG. 2C is an explanatory diagram showing an example of multilevel signal voltage levels in the time domain per subscriber to which the present invention is applied.

FIG. 3 is an explanatory diagram showing an example of voltage level assignment when a signal voltage level is multileveled according to the present invention.

FIG. 4 is an explanatory diagram showing an example of bit allocation of transmission rate notification bits when a clock frequency is increased according to the present invention.

FIG. 5A is an explanatory diagram showing an example of a transmission speed notification bit pattern when the data transmission speed is a basic speed. FIG. 5B is an explanatory diagram showing an example of a transmission speed notification bit pattern when the data transmission speed is twice as fast. FIG. 5C is an explanatory diagram showing an example of a transmission speed notification bit pattern when the data transmission speed is a quadruple speed.

FIG. 6A is an explanatory diagram showing an example of a bit pattern for transmission rate notification when the data transmission rate is a basic rate. FIG. 6B is an explanatory diagram showing an example of a transmission speed notification bit pattern when the data transmission speed is twice as fast. FIG. 6C is an explanatory diagram showing an example of a transmission speed notification bit pattern when the data transmission speed is a quadruple speed.

FIG. 7 is an explanatory diagram showing an example of bit allocation of transmission speed response bits when the clock frequency is increased according to the present invention.

FIG. 8A is an explanatory diagram showing an example of allocation of bit patterns for transmission rate notification / response when using a multi-frame. FIG. 8B is an explanatory diagram showing another example of allocation of a bit pattern for transmission rate notification / response when using a multi-frame.

FIG. 9 is a block diagram illustrating a circuit configuration example according to an embodiment of the present invention.

[Explanation of symbols]

10: Upper circuit for accommodating subscriber circuits, 11a to 11m
... a subscriber circuit, 12 ... a common data bus, 101 ... a transmission / reception circuit (main body), 102 ... a transmission speed return circuit, 103 ...
Transmission speed check circuit, 104: Transmission speed selection circuit, 111
... Transceiver circuit (body), 112 ... Transmission speed loopback circuit,
113: Transmission speed collation circuit, 114: Transmission speed selection circuit

Continued on the front page (72) Inventor Yumiko Nishi 216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Hitachi, Ltd.Communications Division (72) Inventor Katsumi Namomo 216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Hitachi, Ltd. Inside the Manufacturing Division (72) Inventor Hironobu Kashiwagi 216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture F-term within the Hitachi Division Communication Division 5K028 AA06 AA11 CC02 CC06 DD07 GG03 KK01 LL02 LL15 MM12 RR01 RR03 5K029 AA11 DD03 DD13 EE17 FF02 GG10 HH08 HH29 5K030 GA01 GA04 HB16 HC14 JA01 JA02 JL08 KA13 LB14 5K050 AA01 AA07 BB02 BB06 BB12 BB14 CC02 DD21 DD30 EE24 EE25 EE32 FF13 FF15 FF16 GG10 CA11 FB12 CB03 FD17

Claims (6)

[Claims]
1. A common data bus used in 1: M signal transmission between M (M is an integer equal to or greater than 1) subscriber circuits and an upper circuit accommodating the M subscriber circuits. A method for accommodating M subscriber circuits using a time division method, wherein at least one of the M time domains allocated to the M subscriber circuits is at least one subscriber circuit j ( (j is an arbitrary integer) in the time domain corresponding to the first
Wherein the clock frequency is set to k times (k is an integer of 2 or more) a second clock frequency used in a time domain corresponding to another subscriber circuit.
2. A common data bus used in 1: M signal transmission between M (M is an integer of 1 or more) subscriber circuits and a higher-level circuit accommodating the M subscriber circuits. A method for accommodating M subscriber circuits using a time division method, wherein at least one of the M time domains allocated to the M subscriber circuits is at least one subscriber circuit j ( In the time domain corresponding to (j is an arbitrary integer), the number of signal voltage levels used for signal transmission is set to 2 k (k is an integer of 2 or more).
3. The method for accommodating a subscriber circuit according to claim 1, wherein a predetermined number of bits in a time domain corresponding to the subscriber circuit j are set to a transmission rate to be used in the time domain. A method for accommodating a subscriber circuit, wherein the method is used as a transmission rate notification bit for setting a predetermined pattern for indicating.
4. The method for accommodating a subscriber circuit according to claim 1, wherein a predetermined number of bits in a time domain corresponding to the subscriber circuit j are desired to be used in the time domain. A method for accommodating a subscriber circuit, wherein the method is used as a transmission rate trial bit for testing whether a target transmission rate is recognizable on a transmission / reception side.
5. A high-order circuit accommodating a plurality of subscriber circuits by using a time division method, wherein a plurality of clock frequencies or signal voltage levels used for signal transmission in each time domain corresponding to each subscriber circuit are set. A selectable clock frequency or signal voltage level number to be used in a time domain corresponding to a specific subscriber circuit, from the plurality of settable clock frequencies or signal voltage level numbers. A selection unit that controls the transmission / reception unit so that the clock frequency or the number of signal voltage levels is used in the time domain.
6. One of a plurality of subscriber circuits accommodated in one higher-level circuit using a time division method, wherein the other subscriber circuit accommodated in said one subscriber circuit is And a transmitting / receiving unit for performing signal transmission using different clock frequencies or signal voltage levels, and a bit pattern indicating a clock frequency or signal voltage level used by the subscriber circuit for signal transmission are assigned to the subscriber circuit. A transmission rate notification unit for setting a predetermined number of bits in a time domain.
JP2000374389A 2000-12-08 2000-12-08 Method and device for accommodating subscriber circuit Pending JP2002185989A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8027586B2 (en) 2007-10-11 2011-09-27 Hitachi, Ltd. Passive optical network system and optical line terminating apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8027586B2 (en) 2007-10-11 2011-09-27 Hitachi, Ltd. Passive optical network system and optical line terminating apparatus

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