JP2002158713A - Data packet switch node corresponding to interface at very high bit transmission speed - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data packet switch node that is used in an asynchronous digital network. SOLUTION: The data packet switch node is provided with an input stage that disassembles a packet into segments with a prescribed length, a switch matrix having an input output port that supports the same transmission rate B to replace the segment, and an output stage that re-assembles the packet from the segments supplied from an output port. The input stage includes an input interface having a rate equal to ki.B that is a multiple of B and a means that disassembles the packet into ki-sets of input ports of the matrix. The output stage includes an output interface with a rate equal to ko.B that is a multiple of B and a means that reconfigures the packet having a bit transmission rate equal to ko.B by connecting the segments supplied from ko-sets of the output ports of the matrix where a relation of ki.ko>1 is satisfied.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a data packet switching node used in an asynchronous digital network.

[0002]

2. Description of the Related Art A frame switching relay is disclosed in US Pat.
No. 37564. According to this patent, such a frame switching relay comprises n input ports and n output ports, each having the same bit rate D. The switching relay has a time reference at a frequency that is an integer multiple of the bit rate D. From this time reference, a number of clock signals required for various functions of the frame switching relay are derived using a frequency divider. Therefore, the internal implementation of the frame switching relay is determined by the bit rate D of the input and output ports.

However, the implementation of switching fabrics with ports that support very high bit rates (ie, 9.6 Gb / s or more) is at the limit of technical feasibility and therefore very expensive. It is. In fact, even if all other ports are being used at a lower bit rate and the packet-switched relay only needs to support one port at 9.6 Gb / s, the frame-switched relay must The port must be designed as if it supports a bit rate of 9.6 Gb / s. A further disadvantage is that the resources of the switching structure are wasted when the entire switching structure is designed for very high bit rates, while some ports support lower bit rates. is there.

[0004]

SUMMARY OF THE INVENTION It is therefore an object of the present invention to exchange very high bit rates (ie, higher bit rates than the switching node is designed for). It is to provide a simple implementation of a data packet switching node that can do.

[0005]

This object and other objects which will become apparent hereinafter are realized by a data packet switching node according to claim 1.

[0006] The invention also relates to a method according to claim 5.

[0007] Other advantageous features of the invention are defined in the dependent claims.

An advantage of the present invention is that it extends the functionality of a normal data packet switching node without changing the core of the switching matrix.

Another advantage of the present invention is that the input and output ports of a conventional data packet switching matrix can be flexibly configured as needed.

In a preferred embodiment of the method, the ports can be dynamically configured depending on the bit rate supported by the input interface.

The data packet switching node according to the present invention can be used in ATM switches, frame relay switches, IP routers, or any other device that combines ATM switching and IP routing.

[0012] Other features and advantages of the present invention will become apparent on reading the following description of a preferred implementation, provided by way of non-limiting example, and by referring to the accompanying drawings.

[0013]

FIG. 1 shows an embodiment of a data packet switching node 10 according to the present invention. The data packet switching node 10 has eight input ports IP1,. . . ,
IP8 and eight output ports OP1,. . . , OP8
Is provided. All input and output ports are designed to support the same bit rate (eg, B = 2.4 Gb / s).

According to the present invention, data packet switching node 10 has four input ports IP1,. . . , IP4 are bundled together so that it can accommodate one input interface II1 with a bit rate of kB (eg, k = 4 kB = 9.6 Gb / s, ie, interface OC192c). . The remaining four input ports IP5,. . . , IP8 each have an input interface II2,. . . , II5 (ie, interface OC48c).

The input interface II1 is connected to input ports IP1,. . . , IP4. Input ports IP5,. . . , IP8,
The input interfaces II2,. . . , II5, respectively.

According to the present invention, the data packet switching node 10 has four output ports OP1,. . . , OP4 are bundled together so that one output interface OI1 with a bit rate of 9.6 Gb / s
(Interface OC192c). The remaining four output ports OP5,. . . , OP8 each have an output interface OI2,... Having a bit rate of 2.4 Gb per second. . . , OI5 (interface OC48c).

The output ports OP1,. . . , OP4 are output via a multiplexer 12 to an output interface OI1.
It is connected to the. The output ports OP5,. . . , OP8
Are output interfaces OI2,. . . , OI5, respectively.

This configuration has been chosen for the sake of brevity, and any other configuration can be envisaged. A more general configuration consists of n input and output ports, k input interfaces with each input interface associated with a certain number of input ports, and k ′ input interfaces with each output interface associated with a certain number of output ports. Output interface. The following inequality must be satisfied.

(Equation 1)

Where (nip) _i is the number of input ports associated with the ith input interface, and
op) _i is the number of output ports associated with the ith output interface.

The data packet received on the input interface II1 is divided into segments of a fixed length, and the data rate of the bit rate received on the input interface II1 is divided by 1.
Input ports IP1 to IP4 at a bit rate of / 4
It is the role of the splitter 11 to retransmit them sequentially on one of the ports. Preferably, the segments are arranged in a cyclic manner on the input ports IP1,. . . , IP4.

As shown in FIG. 2, if a packet received on the input interface II1 can be divided into 11 segments a to k, the segments with the numbers a, e, and i are transmitted on the input port IP1, Number b,
f, j segments are transmitted on input port IP2,
The segments with numbers c, g, k are transmitted on input port IP3, and the segments with numbers d and h are transmitted on input port IP4. This function is called "demultiplexing in an ingress line" (the ingress line indicates an input interface).

In this example, it is assumed that all packets have the same length. However, the present invention is not limited to the input interfaces II1,. . . , II5 is not limited to the exchange of fixed length packets. Packets with variable lengths can be treated in the same way by cutting the packet into segments of the same length and filling the last segment of the packet with dummy bits if necessary.

The output ports OP1,. . . , OP4, multiplex the segments received on the output port OP
1,. . . , OP4, it is the role of the multiplexer 12 to reconstruct the packet on the output interface OI1 having a bit rate four times the bit rate. The segment preferably has an output port O
P1,. . . , OP4, read cyclically by the multiplexer 12 and output interface OI1
Retransmitted above. This function is called "multiplexing within the egress line" (the term egress line is equivalent to the output interface). The data packet switching node 10 has output ports OP1,. . . , OP4 are responsible for properly allocating the exchanged segments and ensuring that the segments are multiplexed at the multiplexer 12 on the output interface OI1 in the correct order.

FIG. 3 shows an example of this reconstruction mechanism. If a packet is divided into 11 segments m through w,
The switching node must allocate the segments of the output port as follows. Segments m, q, u are received on port OP4, segments n, r, v are received on port OP1, segments o, s, w are received on port OP2, and segments p and t
Must be received on output port OP3.
The mechanisms provided by the data packet switching node 10 to maintain the correct order of packets are described below.

FIG. 4 shows a block diagram of a data packet switching node according to the present invention. The data packet switching node includes a clock 40, a transport plane TP, and a control plane CP.

The transport plane TP includes an input stage 41, a buffer memory 42, and an output stage 43. The input stage 41 has an input interface II
1,. . . , IIk, and the buffer memory 42. The output stage 43 includes a buffer memory 42
And output interfaces OI1,. . . , OIk '
It is connected to the. Also, n input ports IP
1,. . . , IPn and the splitter 11 are also part of the input stage 41. Similarly, n output ports OO
P1,. . . , OPn and multiplexer 12 are part of output stage 43.

The mechanism for dividing the packet into segments in the input stage 41 has already been described with reference to FIG. Similarly, the mechanism for reconstructing the data packet in the output stage 43 has already been described with reference to FIG.

Clock 41 provides the clock frequency for the data packet switching node.

Preferably, if there are n input ports, each segment will be referred to substantially below as a word n
Divided into equal length portions, the clock period corresponds to the time required to write a word into the input queue.

If the clock is encoded with 5 bits (0 to 31), the memory contains enough space to store 32 segments.

The input ports IP1,. . . , IPn, the segment received on input port IPi starts with the previous input port IP (i-1).
It is synchronized so as to be delayed by one word (one clock cycle) from the start of the segment received above.

Such an organization of the input queue allows a high degree of parallel management at the data packet switching nodes. Next, buffer memory management will be described.

At each clock cycle, the next input port is the turn to write available segments waiting in the input queue into buffer memory 42.

At clock period i, the available segments are stored in location i of buffer memory 42.

FIG. 5 shows the contents of the buffer memory storing the segments of the packet containing the twelve segments a to l received on the input interface II1.

For example, if the input ports IP1 to IP4 are
When associated with input interface II1, segment a of a packet received on port IP1 at clock period i is stored at location i of buffer memory 42, and segment b received on port IP2 at clock period i + 1 is: Location (i + 1) MOD
(N) and the port IP3 at the clock cycle i + 2.
The segment c received above is located at location (i + 2)
The segment d stored on MOD (n) and received on port IP4 at clock period i + 3 is located at location (i
+3) stored in MOD (n), location (i +
4) MOD (n) and location (i + n-1) MOD
Segments stored during (n) (not shown in FIG. 5)
Is a segment received on IPn from input port IP5.

The segment e received on port IP1 at clock period i + 4 has a location (i + n) MOD
(N) and stored in port IP2 at clock cycle i + 5.
The segment f received above has the location (i + n +
1) A segment g stored on MOD (n) and received on input port IP3 at clock period i + 6 is segment h stored on location (i + n + 2) MOD (n) and received on port IP4 at clock period i + 7.
Is stored at location (i + n + 3) MOD (n), and the segment (not shown in FIG. 5) stored between location (i + n + 4) MOD (n) and location (i + 2n-1) MOD (n) is This is the segment received on IPn from port IP5.

The segment i received on port IP1 at clock period i + 8 is located at location (i + 2n) MO
D (n) and port IP at clock cycle i + 9
2 received on location (i + 2
n + 1) MOD (n), and so on.

This storage of the segments in the buffer memory 42 allows the implicit links between all segments of the packet to be easily retrieved.

FIG. 4 will be further described below.

The control plane CP comprises a translation table 45 and k 'control queues (each associated with an output interface) 461,. . . , 46k '.

The translation table 45 contains routing information, ie, information on which output interface a packet arriving on an input interface should be exchanged with. The translation table 45 can preferably control the exchange for several virtual connections on one input / output port simultaneously.

The contents of the conversion table 45 determine the type of exchange to be performed. Possible alternatives are point-to-point, point-to-multipoint, or multipoint-to-point exchanges.

In this example, the conversion table 45 indicates that the input interface II1 should be replaced by the output interface OI1. However, the bit transmission speed k
^{* It} is not necessary to exchange the input interface with B for an output interface with the same bit rate. Other routing combinations known by those skilled in the art are also supported by the present invention.

The translation table 45 also stores the input port IP stored in the first memory location.
1,. . . , IPn and their corresponding input interfaces II1,. . . , IIk. Similarly, the translation tables are stored in the output ports OP1,. . . , OPn and their corresponding output interfaces OI1,. . . , OIk '
Including the mapping between

The traffic management module 46 outputs the packets stored in the memory buffer 42 to the output interfaces OI1,. . . , OIk '. Traffic management module 46
Controls the provision of quality of service requirements for different packets. Each output interface is associated with as many control queues as available quality of service. In this example, for simplicity, all packets require the same quality of service, and thus one control queue 461,. . . , 46k 'only have one output interface OI1,. . . , OIk ′.

Each time a new packet is completely stored in the buffer memory 42, a new entry is added to the control queue in which this packet is to be exchanged according to the translation table 45. Each entry in the control queue 46i indicates to the output stage 43 the location in the buffer memory 42 of the first segment of the packet to be retransmitted on the output interface OIi.

Similarly, the conversion table 45 also includes the number of consecutive segments belonging to the same packet exchanged on the output interface OP1.

The control queues 461,. . . , 46k '
Are sequentially and cyclically checked by the output stage 43. Depending on the number of output ports associated with the output interface, the corresponding control queue will be checked by the output stage 43 for the same number of clock periods. In the above example, the output interface OI1 has four output ports OP1,. . . , OP4, so that after control queue 461 has been checked for four clock cycles, control queue 462 will be checked for one clock cycle, and so on.

The control queues 461,. . . , 46k '
Are handled on a FIFO (First In First Out) basis. At each clock cycle, the next control queue is checked by output stage 43. If the transmission of the packet has been initiated and not completed, retrieving the subsequent segment of this packet in the buffer memory 42 is performed by the output stage 4
The third role. Next, this mechanism will be described. If no entry is read from the control queue, output stage 43 jumps to the next control queue during the next clock cycle.

Otherwise, if no packets are currently being transmitted, output stage 43 checks the control queue and reads from buffer memory 42 the address of the first segment of the new packet to be retransmitted.

Also, appropriate output ports OP1,... Associated with the output interface OI1 for retransmitting the segment read from the buffer memory 42. . . , OP4 is also the role of the output stage 43. Preferably, the first segment is randomly assigned to one of the output ports associated with the output interface. Each subsequent segment is assigned to the next output port associated with the output interface. Alternatively, the output put is automatically determined from the value of the clock.

The mechanism used by output stage 43 to find the address of the subsequent segment after the first segment has been read in the control queue will now be described. The address in the buffer memory 42 of the next segment transmitted on the output port must be retrieved according to the following algorithm. Several conditions must be checked.

If the previous segment retransmitted on this output port was not the last segment of a packet retransmitted on this port, the address of the next segment is given by the following table.

[Table 1]

If the previous segment retransmitted on this port was the last segment of a packet transmitted on this port, two sub-cases must be considered.

If there is a new packet currently being transmitted on the output interface, and one of the segments of this packet will be transmitted on this port, the address of the next segment is: Given by the table.

[Table 2]

If there are no new packets being retransmitted on this port on its associated output interface, the address of the segment retransmitted on this port is read in the control queue 461 (this Is the address of the first segment of the new packet).

As already described with reference to FIG.
The segments received on the port associated with output interface OI1 are combined to reconstruct the original packet.

In the preferred embodiment of the present invention, the number of associated input ports / input interfaces, output ports / output interfaces, and each of the input and output interfaces is dynamically adjusted according to the needs of the data packet switching node. Must be configurable.

[Brief description of the drawings]

FIG. 1 illustrates an embodiment of a data packet switching node according to the present invention.

FIG. 2 is a diagram illustrating an example of demultiplexing on an input interface (ingress line).

FIG. 3 is a diagram illustrating an example of multiplexing on an output interface (egress line).

FIG. 4 is a block diagram illustrating a data packet switching node according to the present invention.

FIG. 5 illustrates the contents of a buffer memory that stores segments of a packet received on a very high speed interface.

[Explanation of symbols]

Reference Signs List 10 data packet switching node 11 splitter 12 multiplexer 41 input stage 42 buffer memory 43 output stage 45 conversion table 46 traffic management module 461, 462, 46k 'control queue CP control plane II1, II2, II3, II4, II5, IIk input interface IP1, IP2, IP3, IP4, IP5, IP6, I
P7, IP8 input ports OI1, OI2, OI3, OI4, OI5, OIk '
Output interface OP1, OP2, OP3, OP4, OP5, OP6, O
P7, OP8 Output port TP Transport plane

Claims (7)

[Claims] 1. An input stage (41) for cutting a data packet into segments of a fixed length, and an input port (I) supporting the same bit rate B.
P1,. . . , IPn) and the output port (OP
1,. . . , OPn), a switching matrix (42, 45, 46) for switching, and an output port (OP) of the switching matrix.
1,. . . , OPn), the output stage (4) reconstructing the data packets from the segments supplied from
3), wherein said input stage (41) has at least one input interface (II1,... II) having a bit rate equal to a multiple of B, ki · B. , IIk) and means (11) for dividing the data packets received on the interface into segments allocated to the ki input ports of the switching matrix, the output stage (43) comprising: By concatenating at least one output interface (OI1, ..., OIk ') having a bit rate equal to a multiple of k.o.B with the segments provided from the ko output ports of the switching matrix, Means for reconstructing a data packet having a bit rate equal to ko · B Wherein the data packet switching node, which is a ki · ko> 1. 2. The exchange matrix includes: a first memory location for storing an identifier representing an association between the input interface and the corresponding ki input ports; and an output interface and the corresponding ko input ports. A second memory location for storing an identifier representing an association between output ports. 3. A buffer memory (4) for storing a segment belonging to a packet received at the input interface (II1).
2); memory writing means for sequentially writing segments received on the ki input ports (IP1, ..., IP4) to the buffer memory (42); and exchanging the segments belonging to the packet. A translation table (45) for determining an output interface to be output (OI1); a traffic management module (46) for storing the address of the first segment of the packet in the buffer memory (42); Memory that retrieves successive segments belonging to the packet and assigns each of the segments to one of the ko output ports (OP1,..., OP4) associated with the output interface (OI1) in a cyclic manner. 2. The data according to claim 1, further comprising: reading means. Packet switching node. 4. The data packet switching node according to claim 1, wherein the data packet switching node is exclusively used in an ATM switch to exchange fixed-length data packets supplied on the input interface. 5. The data packet switching node according to claim 1, wherein the data packet switching node is used exclusively in an IP router for exchanging variable length data packets supplied on the input interface. 6. The data packet switching node according to claim 1, wherein the data packet switching node is used exclusively in a device that provides both an IP routing function and an ATM switching function. 7. An association between each input interface and a corresponding input port, and an association between each output interface and a corresponding output port, is dynamically configured in the first memory location and the second memory location. The data packet switching node according to claim 2, wherein