JP2002134704A - Method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a high-speed logic element by a method where a superior silicide layer is formed by eliminating carbon contamination on the surface of silicon substrate, and the contact resistance of the source/drain is reduced. SOLUTION: In a method for manufacturing a semiconductor device where a memory element circuit 3 and a logic element circuit 5 are mounted on a single chip, a sidewall-forming layer 11 is etched back by etching using mixed gas which is composed of of carbon, hydrogen and fluorine, and composed of carbon monoxide and oxygen, and sidewalls 47 are formed on side surfaces of a gate electrode 45. At least the surface layer of a silicon substrate 1 in a region where a source/drain of a transistor 40 of the logic element circuit 5 is formed is removed by using plasma of gas containing halogen, and a cobalt silicide layer 48 is formed on the surface of a source/drain region of the transistor 40 by using salicide technology.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device in which a silicide layer is formed by a silicide resistance reduction technique.

[0002]

2. Description of the Related Art In recent years, a so-called DRAM embedded logic LSI in which a DRAM memory circuit and a logic element circuit are integrated into one chip has been actively developed. This DRAM
The embedded logic LSI is a high value-added LSI that integrates a DRAM memory function and a logic function, and has advantages such as reduction in the number of chips mounted on an electronic product.

In a logic element embedded with a DRAM, in order to obtain a high-speed logic circuit, a silicide layer is formed in a source / drain region of a transistor of the logic circuit in a self-aligned manner. In order to form a silicide layer by the silicide technique, sidewalls (sidewall spacers) of an insulating film made of a silicon nitride film or the like are formed on side surfaces of the gate electrode. The contacts in the source / drain regions are opened directly toward the silicide layer surface. On the other hand, a salicide technique is not applied to a DRAM memory circuit, and a self-aligned contact technique is used for bit line contacts and the like in order to reduce the cell area.

In order to realize a contradictory structure in which the salicide technique is applied to one side and the salicide technique is not applied to the other side, a resist is patterned on a silicon nitride film covering a DRAM memory circuit. The silicon nitride film is etched back in a state where the silicon nitride film in a portion of the logic circuit or the like that requires a sidewall spacer is exposed. As a technique for performing this etch back, a so-called Partial Side Wall Etch Back is used. As a result, the sidewall spacer of the silicon nitride film is formed only in the transistor such as the logic circuit.

[0005] These techniques are disclosed in JP-A-2000-1506.
No. 65, JP-A-11-340437, JP-A-11-220036, JP-A-11-3974, JP-A-11-97649, JP-A-11-16
No. 3,281, JP-A-10-303187, and the like.

Next, an example of the prior art will be described with reference to FIGS.

As shown in FIG. 3, a DRAM substrate 120, a logic transistor 140 and the like are formed on a silicon substrate 101. This silicon substrate 10
1, a silicon nitride film 111 covering the DRAM transistor 120, the logic transistor 140, and the like is formed by a CVD method, and then a resist pattern 112 is patterned by a known lithography technique. The patterning is performed so as to cover a region of the DRAM memory circuit or the like where the formation of the sidewall is unnecessary.

Note that the silicon substrate 101 has an ST
An element isolation region 102 is formed by an I (Shallow Trench Isolation) method.

The DRAM transistor 120 and the logic transistor 140 have a gate oxide film 1
21, 141, polysilicon films 122, 142, tungsten silicide (WSi ₂ ) layers 123, 143, HT
The offset films 124 and 144 formed by O (High Temperature Oxygenation) are stacked,
Gate electrode 12 covered with offset films 124 and 144
5, 145 are formed. The gate electrode 125,
The width of 145 is, for example, 0.15 μm.

Next, trifluoromethane (CHF)_Three)When
Carbon monoxide (CO) and oxygen (O_TwoA gas mixture consisting of
Plasma etching using
Then, the sidewall forming layer 111 is etched back.
Of the gate electrode 145 including the offset film 144
Next, a sidewall spacer 147 is formed. At that time
The etch-back condition is, for example, a two-frequency excitation reactive ion.
On-etching (hereinafter RIE for reactive ion etching)
RIE is an abbreviation for Reactive Ion Etching.
And trifluoromethane (CH
F_Three): 25cm ^Three/ Min, carbon monoxide (CO): 8
0cm^Three/ Min, oxygen (O_Two): 25cm^Three/ Min
And set the pressure of the etching atmosphere to 10 Pa
And the upper electrode power of the etching apparatus is set to 1.00 kW.
(Power density is 3.18 W / cm^Two), Lower electrode power
To 600 W (power density is 1.90 W / cm^Two), Top
The electrode temperature is 60 ° C. and the temperature of the processing chamber wall of the etching apparatus is 5
The temperature of the lower electrode was set at 30 ° C., and the temperature was set at 0 ° C.

Further, the resist pattern 112 covering the DRAM memory circuit region is removed by down-flow ashing (for example, using a down-flow ashing device for ICP discharge) by a known manufacturing method. The ashing conditions include, for example, oxygen (O ₂ ): 3000 cm ³ / min as an ashing gas, an ashing atmosphere pressure of 120 Pa, and an ashing power of 1.0.
0 W, substrate temperature 250 ° C, overashing amount 50
%.

As a result, as shown in FIG. 4, a side wall spacer 147 made of the silicon nitride film 111 is formed on the side wall of the gate electrode 145 (including the offset film 144).
Is formed. This sidewall spacer 147 is
It also has a function as an ion implantation stopper when forming an LDD (Lightly Doped Drain) transistor. On the other hand, the DRAM memory circuit area is covered with the silicon nitride film 111.

The above etch-back condition uses a mixed gas of trifluoromethane (CHF ₃ ), carbon monoxide (CO), and oxygen (O ₂ ) as an etching gas.
In addition, since the flow ratio of carbon monoxide (CO) to the mixed gas is set to an appropriate flow ratio of 100: 61.5, the width of the side wall spacer depends on the density and the bottom of the side wall spacer has a saw blade. Defects in shape are avoided.

As shown in FIG. 5, after etching back the silicon nitride film 111, a metal (for example, cobalt) film for forming silicide and a titanium nitride film for forming a cap layer are formed, and then the first RTA ( Rapid Thermal Anne
aling: rapid heating annealing) to form a metal silicide (for example, cobalt silicide) layer in a source / drain region in a self-aligned manner, and unnecessary portions remaining on an insulating film (silicon nitride film 111, element isolation region 102, etc.). Metals are removed by, for example, sulfuric acid and hydrogen peroxide. After that, a second RTА process is performed to form a metal silicide (for example, cobalt silicide) layer 148.

[0015]

However, when the etch-back for forming the sidewall spacer is performed by the conventional technique as described above, carbon from the mixed gas is implanted into the silicon substrate. Carbon was accelerated and implanted by Vdc due to the power applied to the lower electrode, and the amount of carbon implanted was not regarded as important when setting the etching conditions.

When the resist is removed by oxygen down-flow ashing, a small amount of oxygen ions (O ⁺ ) are bombarded by ions, but the presence of a fluorocarbon (CF) polymer layer existing on the silicon substrate surface As a result, a large amount of oxygen radicals do not enter the silicon substrate. Therefore, it does not react with carbon present inside the silicon substrate, and a carbon contamination layer (hereinafter referred to as a carbon contamination layer) remains.

However, since carbon is present on the silicon substrate as interstitial atoms in the silicon crystal or silicon-carbon bond, it locally inhibits the solid phase reaction at the cobalt-silicon interface. That is, the silicidation reaction does not proceed sufficiently, and the cobalt silicide (CoSi ₂ ) layer becomes locally non-uniform. After the second RT process, an increase in sheet resistance (about 7Ω / □) is brought about. The sheet resistance when the cobalt silicide is formed on the bare silicon substrate without performing plasma processing such as etch-back is 5.2.
Ω / □.

Due to the factors described above, the transistor characteristics of the logic circuit are degraded, causing the performance and quality of the DRAM-embedded logic LSI to deteriorate.

[0019]

SUMMARY OF THE INVENTION The present invention is a method for manufacturing a semiconductor device which has been made to solve the above-mentioned problems.

According to the method of manufacturing a semiconductor device of the present invention, there is provided a method of manufacturing a semiconductor device in which a memory element circuit and a logic element circuit are mounted on one chip, wherein the side wall is formed so as to cover a gate electrode of a transistor of the logic element circuit. After the formation layer is formed, the sidewall formation layer is formed by etching using a gas containing carbon, hydrogen, and fluorine or a gas containing carbon and fluorine, carbon monoxide, and a mixed gas containing oxygen as an etching gas. Forming a sidewall on the side surface of the gate electrode by etching back, and removing a surface layer of the silicon substrate at least in a region where a source / drain of the transistor of the logic element circuit is formed using plasma of a gas containing halogen. And the transformer of the logic element circuit by salicide technology. And a step of forming a cobalt silicide layer on the source and drain regions surface of the register.

In the method of manufacturing a semiconductor device, at least a surface layer of the silicon substrate in a region where a source / drain of a transistor of the logic element circuit is formed is removed using plasma of a gas containing halogen after etching for forming a sidewall. This removes carbon present in the surface layer of the silicon substrate. for that reason,
When forming the cobalt silicide layer, cobalt silicide is formed on the surface of the silicon substrate with a uniform thickness.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a method of manufacturing a semiconductor device according to the present invention will be described with reference to the schematic sectional view of FIG.

As shown in FIG. 1A, an element isolation region 2 is formed on a silicon substrate 1 by STI (Shallow Trench Isolation). A memory element circuit 5 in which a DRAM is formed and a logic element circuit 7 in which a logic element is formed are formed in an element formation region separated from the element isolation region 2. The memory element circuit 5 includes a transistor (DRAM transistor) 20 and the like.
In the logic element circuit 7, a transistor (logic transistor) 40 and the like are formed.

On the silicon substrate 1, a sidewall forming layer 11 made of a silicon nitride film covering the DRAM transistor 20, the logic transistor 40 and the like is formed to a thickness of, for example, 60 nm by a CVD method. The resist pattern 12 is patterned by a known lithography technique. The patterning is performed so as to cover a region of the DRAM memory circuit or the like where the formation of the sidewall is unnecessary.

The DRAM transistor 20 and the logic transistor 40 have a gate oxide film 21,
41, polysilicon films 22 and 42, tungsten silicide (WSi ₂ ) layers 23 and 43, HTO (High Tempera
The offset films 24, 44 formed by ture oxidation (high-temperature oxidation) are stacked, and the offset films 24, 4
4 are formed on the gate electrodes 25 and 45. The width of the gate electrodes 25 and 45 is formed, for example, to 0.15 μm.

Next, as shown in FIG.
Fluoromethane (CHF_Three) And carbon monoxide (CO) and oxygen
(O_Two) Was used as the etching gas.
The above-mentioned sidewalls are formed by plasma etching.
The layer 11 is etched back, and the layer including the offset film 44 is etched.
Side walls (sidewalls)
A spacer 47 is also formed. Etchba at that time
As an example, the locking condition is a two-frequency excitation RIE device.
In addition, trifluoromethane (CH
F_Three): 25cm^Three/ Min, carbon monoxide (CO): 8
0cm^Three/ Min, oxygen (O_Two): 25cm^Three/ Min
Between the flow rate of this mixed gas and the flow rate of carbon monoxide.
The ratio is maintained between 100: 30 and 100: 70.
Further, the pressure of the etching atmosphere was set to 10 Pa,
The upper electrode power of the cutting device is set to 1.00 kW (power
Density is 3.18 W / cm^Two), Lower electrode power 600
W (power density is 1.90 W / cm^Two), Upper electrode temperature
60 ° C., the temperature of the processing chamber wall of the etching apparatus is 50 ° C.
The internal electrode temperature is set to 30 ° C. At that time, the lower electrode
Is, for example, 0.63 W / c.
m^Two1.27 W / cm or more ^TwoSet as follows.

Further, the resist pattern 12 covering the region of the memory element circuit 5 is removed by a known manufacturing method, for example, by downflow ashing (for example, using a downflow ashing device of ICP discharge). The ashing condition is, for example, that the ashing gas contains oxygen (O
₂ ): 3000 cm ³ / min, ashing atmosphere pressure of 120 Pa, ashing power of 1.00
W, substrate temperature 250 ° C, overashing amount 50%
Set to.

Further, using an ashing device (for example, a downflow ashing device for ICP discharge), etching for removing a carbon contamination layer (carbon contamination layer) (not shown) of the silicon substrate 1 is performed. The etching conditions are, for example, oxygen (O ₂ ): 3000 cm ³ / min and tetrafluoromethane (CF ₄ ): 60 cm ³ / min as the etching gas, the pressure of the etching atmosphere is 120 Pa, and the etching power is 1 1.00 W, the substrate temperature was set to 250 ° C., and the etching time was set to 25 seconds so that a damaged layer (not shown) of the silicon substrate 1 could be cut by about 1.9 nm.

In the above etching, oxygen radicals and fluorine radicals are generated in a mixed gas of oxygen (O ₂ ) and tetrafluoromethane (CF ₄ ). CF, CF ₂ , CF ₃ , CF ₄ , which easily releases polymers and residues
Etc. and remove.

Further, the fluorine radicals react with a carbon contaminant layer (not shown) under the surface of the silicon substrate 1 to produce CF, C
It is removed as F ₂ , CF ₃ , CF _4, etc., and the silicon substrate 1 is etched. So-called light etching can be performed on the carbon-contaminated layer of the silicon substrate 1 into which carbon has been implanted, at a depth of 1.9 nm to 5 nm, preferably 1.9 nm to 3.4 nm.

The gas flow rate in the silicon substrate surface is adjusted by the diluted oxygen gas, and the distribution of fluorine radicals is improved, so that the silicon substrate is lightly etched with high precision.

In the etching in which the silicon nitride film 11 is etched back to form the sidewalls 47, a carbon contamination layer (a carbon contamination layer) is formed on the surface of the silicon substrate 1 and in a region having a depth of about 35 to 40 nm from the surface. Has been confirmed. Its carbon peak concentration is about 1 × 10 ¹⁹ / cm ³ or more. Accelerated by Vdc = −500 V due to the power of the lower electrode, carbon adheres to the surface of the silicon substrate 1 and carbon is also implanted inside the silicon substrate 1. However, the carbon concentration on the surface is greatly reduced by the silicon etching for removing the carbon contaminant layer on the surface of the silicon substrate 1 described above. Further, physical damage (disturbance of the silicon lattice) under the surface of the silicon substrate 1 caused by the sidewall etchback is effectively removed by silicon etching.

After etching back the sidewall forming layer 11, a metal film (for example, a cobalt film having a thickness of 10 nm) for forming silicide and a titanium nitride film for forming a cap layer are formed to a thickness of, for example, 30 nm. Then
A first RTA (Rapid Thermal Annealing) process is performed to form a metal silicide (for example, cobalt silicide) layer in the source / drain region in a self-aligned manner. An example of the first RT condition is 50
Perform RT for 30 seconds in a 0 ° C. temperature atmosphere. continue,
Unnecessary metal remaining on the insulating film (silicon nitride film 11, element isolation region 2, etc.) is removed by, for example, sulfuric acid and hydrogen peroxide. Thereafter, a second RT # process is performed to form a metal silicide (for example, cobalt silicide (CoSi ₂ )) layer 48. As an example of the second RT # condition, RT # is performed in an atmosphere at a temperature of 800 属 C for 30 seconds.

The effect of the present embodiment will be described with reference to FIG. 2 showing the relationship between the sheet resistance of the cobalt silicide (CoSi ₂ ) layer and the etching amount of the silicon substrate. In FIG. 2, the ordinate indicates the CoSi sheet resistance value (Ω / □), and the abscissa indicates the Si (silicon) substrate etching amount (nm). In the following description, the reference numerals given to the components are the same as those of the components described in the above embodiment.

When the etching amount of the silicon substrate 1 was 0 nm, the sheet resistance was 6.0Ω / □ on average and 7.0Ω / □ at the maximum. When the etching amount of the silicon substrate 1 was 1.9 nm, the average was 5.6 Ω / □, and the maximum was 5.8 Ω / □. Further, when the etching amount of the silicon substrate 1 was 3.4 nm, the average was 5.5 Ω / □. That is, when the silicon substrate 1 is etched, the sheet resistance of the cobalt silicide layer surely decreases. The etching amount of the silicon substrate 1 is 1.9 nm or more and 3.4 n
m or less, the average is 5.6Ω / □, and the maximum is 5.
A good practical sheet resistance with a small variation of 8 Ω / □ or less and a variation of ± 0.2 Ω / □ can be obtained. Moreover, the film thickness of cobalt silicide (CoSi ₂ ) is 3
It grows to about 5 nm to 40 nm.

Under the present conditions, the surface concentration of carbon is significantly reduced. Due to this reduction effect, the carbon concentration becomes
It is presumed that the range does not affect the solid phase reaction at the silicon interface. In addition, it is considered that by actively performing light etching on a layer in which the silicon lattice is disordered, the crystal consistency at the cobalt-silicon interface is improved, and a uniform solid-phase reaction is promoted.

That is, according to the present embodiment, the DRA
In the salicide (SALICIDE) technology for reducing the resistance of the source / drain region of the transistor 40 of the logic element circuit 5 during the manufacturing process of the M-embedded logic LSI, a side wall for forming a side wall 47 covering the side surface of the gate electrode 45 is formed. After the wall forming film (silicon nitride film) 11 is etched back, the surface of the silicon substrate 1 on which the carbon contaminated layer is generated by the plasma containing halogen has a depth of 1.9 nm or more and 5.0 nm or less, preferably 1.9 nm or more. The metal silicide layer (cobalt silicide (CoSi ₂ ) layer) is removed at a depth of 3.4 nm or less.
48 suppresses a rise in sheet resistance and improves in-plane uniformity of sheet resistance.

The removal depth of the silicon substrate 1 is 1.9 n.
If the depth is smaller than m, the effect of removing the carbon contaminated layer formed on the surface of the silicon substrate 1 is small. That is, silicidation cannot be performed sufficiently due to carbon contamination.
If the silicon substrate 1 is cut deeper than 5 nm, the depth of the diffusion layer constituting the source / drain becomes too shallow, and the metal silicide layer 48 is formed.
And the silicon substrate 1 may be short-circuited.

As described in the above embodiment, DRA
When applied to an M-embedded logic LSI, a high-quality and highly reliable logic element circuit can be obtained.

In the above embodiment, cobalt is used as the salicide metal, but a metal applicable to salicide technology, for example, a high melting point metal such as titanium or nickel may be used.

In the above embodiment, the salicide technique is applied to the source / drain regions. However, the gate electrode may be salicide. In that case, it is necessary to remove the offset film before salicidation, and the gate electrode before salicidation is formed of polysilicon.

Further, in the above embodiment, trifluoromethane (CHF ₃ ), carbon monoxide (CO) and oxygen (O ₂ ) are used as the etching gas for etching back the silicon nitride film.
Was used, but difluoromethane (CH
₂ F ₂ ), a mixed gas of carbon monoxide (CO) and oxygen (O ₂ ), trifluoromethane (CHF ₃ ), tetrafluoromethane (CF ₄ ), carbon monoxide (CO) and oxygen (O ₂ ) And a mixed gas of tetrafluoromethane (CF ₄ ), carbon monoxide (CO), and oxygen (O ₂ ).

In the above embodiment, the etching apparatus for etching back the silicon nitride film is provided with two-frequency excitation R
I used IE equipment, but RIE equipment, magnetron RIE
An apparatus, a high-density plasma etching apparatus, or the like can also be used.

Further, in the above-described embodiment, an ICP (Inductively Coupled Plas) is used for so-called light etching, which cuts the silicon substrate 1 to 1.9 nm or more and 5.0 nm or less.
ma) Although a discharge type ashing device was used, for example, a microwave excited down flow ashing device, a surface wave excited down flow ashing device, an RF discharge type down flow ashing device, or the like can also be used. Further, a two-frequency excitation RIE device, an RIE device, a magnetron RIE device,
A medium-high density plasma etching apparatus can also be used.

[0045]

As described above, according to the method of manufacturing a semiconductor device of the present invention, after forming a sidewall on the side wall of a gate electrode by etch-back and before salicidation, a gas containing halogen is removed. Since the method includes the step of removing at least the surface layer of the silicon substrate in the region where the source / drain of the transistor of the logic element circuit is formed using plasma, the resistance of the source / drain region of the transistor of the logic circuit is reduced. In the salicide technique, a carbon contamination layer of a silicon substrate caused by etch back is reduced to, for example, 1.9 nm or more and 5.0 nm.
Remove to the following depth. Since the carbon contamination layer on the surface of the silicon substrate is removed, a metal silicide layer having a uniform and uniform film thickness can be formed. Therefore, an increase in the sheet resistance of the metal silicide layer is suppressed, and the in-plane uniformity of the sheet resistance is improved. Therefore, according to the method of manufacturing a semiconductor device of the present invention, when a DRAM embedded logic LSI is manufactured, a good logic circuit with high quality and high reliability can be obtained.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention.

FIG. 2 is a diagram showing a relationship between a sheet resistance of a cobalt silicide (CoSi ₂ ) layer and an etching amount of a silicon substrate.

FIG. 3 is a schematic sectional view showing a method of manufacturing a semiconductor device according to a conventional technique.

FIG. 4 is a schematic sectional view showing a method of manufacturing a semiconductor device according to a conventional technique.

FIG. 5 is a schematic sectional view showing a method of manufacturing a semiconductor device according to a conventional technique.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 5 ... Memory element circuit, 7 ... Logic element circuit, 11 ... Side wall formation layer, 20 ... Transistor, 25 ... Gate electrode, 40 ... Transistor, 45
... gate electrode, 47 ... side wall, 48 cobalt silicide layer

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/088 H01L 27/10 681F 27/108 21/8242 (72) Inventor Takahiro Saito Shinagawa-ku, Tokyo 6-7-35 Shinagawa F-term in Sony Corporation (reference) 4M104 AA01 BB01 BB20 BB21 BB25 CC05 DD02 DD04 DD64 DD80 DD84 EE09 EE17 FF13 FF14 GG09 GG16 HH16 HH20 5F004 BB26 CA04 CA09 DA00 DA01 DA15 DB16 DB26 DB01 5F048 AA00 AB01 AB03 BB05 BB08 BB12 BF06 BF16 BG14 DA27 5F083 AD00 GA02 GA27 JA02 JA32 JA35 JA53 NA01 PR03 PR05 PR21 PR34 PR39 ZA12

Claims (5)

[Claims] 1. A method for manufacturing a semiconductor device in which a memory element circuit and a logic element circuit are mounted on one chip, wherein a side wall forming layer is formed so as to cover a gate electrode of a transistor of the logic element circuit, And a gas composed of hydrogen and fluorine or a gas composed of carbon and fluorine, carbon monoxide, and etching using a mixed gas composed of oxygen as an etching gas, thereby etching back the sidewall forming layer to form a gate electrode. Forming a sidewall on a side surface, removing a surface layer of a silicon substrate at least in a region where a source / drain of a transistor of the logic element circuit is formed using a plasma of a gas containing halogen, Table of source / drain regions of transistors in logic element circuits Forming a cobalt silicide layer on a surface of the semiconductor device. 2. The removal amount of the surface layer of the silicon substrate is 1.9.
2. The method for manufacturing a semiconductor device according to claim 1, wherein the thickness is not less than 5 nm and not more than 5 nm. 3. The gas comprising carbon, hydrogen and fluorine is trifluoromethane (CHF ₃ ), difluoromethane (CH ₂ F ₂ ) or trifluoromethane (CHF ₃ ).
_{3. The} method for manufacturing a semiconductor device according to claim 1, comprising a mixed gas of ₃ ) and tetrafluoromethane (CF ₄ ). 4. The gas comprising carbon and fluorine comprises tetrafluoromethane (CF ₄ ). 2. The method for manufacturing a semiconductor device according to claim 1, wherein: 5. The gas containing halogen comprises tetrafluoromethane (CF ₄ ), difluoromethane (CH ₂ F ₂ ) or trifluoromethane (CHF ₃ ). 2. The method for manufacturing a semiconductor device according to claim 1, wherein: