JP2002134552A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP2002134552A
JP2002134552A JP2000330468A JP2000330468A JP2002134552A JP 2002134552 A JP2002134552 A JP 2002134552A JP 2000330468 A JP2000330468 A JP 2000330468A JP 2000330468 A JP2000330468 A JP 2000330468A JP 2002134552 A JP2002134552 A JP 2002134552A
Authority
JP
Japan
Prior art keywords
semiconductor device
case
recognition mark
bonding
concave portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2000330468A
Other languages
Japanese (ja)
Other versions
JP4102541B2 (en
Inventor
Tomohiro Hieda
智宏 稗田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2000330468A priority Critical patent/JP4102541B2/en
Publication of JP2002134552A publication Critical patent/JP2002134552A/en
Application granted granted Critical
Publication of JP4102541B2 publication Critical patent/JP4102541B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/48139Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49175Parallel arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16195Flat cap [not enclosing an internal cavity]

Landscapes

  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To prevent stoppage of a wire bonding machine in the wire bonding process. SOLUTION: A semiconductor device of this invention comprises a semiconductor chip loaded on a board, a package that has a case with electrode terminals formed by insertion and accommodates the board and the semiconductor chip, and bonding wires connecting the semiconductor chip with the electrode terminals. The case has an identification mark so as to decide a connecting position of the bonding wires when the bonding wires are connected.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は半導体装置に関し、
特にモータ制御などのスイッチング素子に使用される半
導体装置に関する。
The present invention relates to a semiconductor device,
In particular, the present invention relates to a semiconductor device used for a switching element for motor control or the like.

【0002】[0002]

【従来の技術】図5は、電極端子2をケース5の金型に
挿入したまま成形する、インサート構造を有する一般的
な半導体装置の平面図である。半導体装置において、半
導体チップ1と電極端子2とをアルミワイヤ3によって
ワイヤボンディングする場合、その接続位置の決定には
高い精度が要求される。従って、ワイヤボンダ装置(不
図示)によって半導体チップ1および接続端子2の位置
を検出した上で、接続位置を決定し、ワイヤボンディン
グを行う。
2. Description of the Related Art FIG. 5 is a plan view of a general semiconductor device having an insert structure in which an electrode terminal 2 is molded while being inserted into a mold of a case 5. FIG. In a semiconductor device, when the semiconductor chip 1 and the electrode terminal 2 are wire-bonded with the aluminum wire 3, a high precision is required for determining the connection position. Therefore, after detecting the positions of the semiconductor chip 1 and the connection terminals 2 by a wire bonder device (not shown), the connection position is determined, and wire bonding is performed.

【0003】従来は、半導体装置のケース5を射出成形
で作製する際に、金型からケース5を出したときに必然
的に形成されてしまう跡形30などを、接続端子2およ
び半導体チップ1の位置を検出するための認識マークと
して使用し、このマークをワイヤボンダ装置に接続され
たカメラによって画像認識し、これに基づいて、アルミ
ワイヤ3の始点および終点の位置を決定していた。
Conventionally, when a case 5 of a semiconductor device is manufactured by injection molding, a trace 30 or the like which is inevitably formed when the case 5 is taken out of a mold is used to form the connection terminal 2 and the semiconductor chip 1. The mark is used as a recognition mark for detecting the position, the mark is image-recognized by a camera connected to the wire bonder, and the positions of the start point and the end point of the aluminum wire 3 are determined based on this.

【0004】[0004]

【発明が解決しようとする課題】しかしながら、上述の
ような射出成形時にケース5に形成される跡形30など
はそのサイズや形状が適切でなく、ケース5上において
濃淡が不明確で識別しにくいために、ワイヤボンダ装置
が認識マークを誤認識し、ワイヤボンダ装置が停止して
しまうという問題があった。
However, the size and shape of the traces 30 and the like formed on the case 5 during the injection molding described above are not appropriate, and the shading on the case 5 is unclear and difficult to distinguish. In addition, there is a problem that the wire bonder device erroneously recognizes the recognition mark and the wire bonder device stops.

【0005】本発明は、上記のような課題を解決するた
めになされたものであり、良好に画像認識可能な認識マ
ークを設けて、ワイヤボンディング工程におけるワイヤ
ボンダ装置の停止を防ぐことを目的とする。
SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and has as its object to provide a recognition mark capable of satisfactorily recognizing an image so as to prevent a wire bonder device from being stopped in a wire bonding step. .

【0006】[0006]

【課題を解決するための手段】本発明の半導体装置は、
基板上に搭載された半導体チップと、電極端子がインサ
ート成形されたケースを有し、基板および半導体チップ
を収容するパッケージと、半導体チップと電極端子とを
接続するボンディングワイヤとを備えた半導体装置であ
って、ケースが、ボンディングワイヤを設ける際に、ボ
ンディングワイヤの接続位置を決定するための認識マー
クを有することを特徴とする。
According to the present invention, there is provided a semiconductor device comprising:
A semiconductor device having a semiconductor chip mounted on a substrate, a case in which electrode terminals are insert-molded, a package accommodating the substrate and the semiconductor chip, and a bonding wire connecting the semiconductor chip and the electrode terminals. The case is characterized in that the case has a recognition mark for determining a connection position of the bonding wire when the bonding wire is provided.

【0007】上記のように認識マークが半導体装置のケ
ースに設けられているので、ボンディングワイヤを設け
る際に、精度良く認識マークを検出することができる。
この検出結果により、ボンディングワイヤの一端に接続
する電極端子の位置と、ボンディングワイヤのもう一端
に接続する半導体チップ上のボンディングパッドの位置
とを正確に算出して、ボンディングワイヤの接続位置を
精度良く決定することができる。従って、認識マークの
誤認識により、ボンディング工程においてワイヤボンダ
装置が停止してしまうことを防止できる。
[0007] Since the recognition mark is provided on the case of the semiconductor device as described above, the recognition mark can be detected with high accuracy when the bonding wire is provided.
Based on this detection result, the position of the electrode terminal connected to one end of the bonding wire and the position of the bonding pad on the semiconductor chip connected to the other end of the bonding wire are accurately calculated, and the connection position of the bonding wire is accurately determined. Can be determined. Therefore, it is possible to prevent the wire bonder device from stopping in the bonding process due to erroneous recognition of the recognition mark.

【0008】上記の半導体装置において、ボンディング
ワイヤの接続位置を決定するための認識マークは、凹部
から形成され得る。認識マークとして凹部を有する半導
体装置(第1の半導体装置とする)によると、半導体装
置に光を照射させると、凹部の内部に入射光の影が形成
されて凹部が暗い領域として認識され、凹部以外の部分
は明るい領域として認識される。従って、ワイヤボンダ
装置は明確な明るさの違いによって認識マークを正確に
認識できるので、ボンディングワイヤの接続位置をより
精度良く決定してワイヤボンディングを行うことができ
る。
In the above-mentioned semiconductor device, the recognition mark for determining the connection position of the bonding wire can be formed from a concave portion. According to a semiconductor device having a concave portion as a recognition mark (referred to as a first semiconductor device), when light is irradiated to the semiconductor device, a shadow of incident light is formed inside the concave portion, and the concave portion is recognized as a dark region. The other parts are recognized as bright areas. Therefore, the wire bonder can accurately recognize the recognition mark based on a clear difference in brightness, so that the wire bonding can be performed by more accurately determining the connection position of the bonding wire.

【0009】上記第1の半導体装置において、認識マー
クとしての凹部の底面は乱反射面であることが好まし
い。凹部の底面が乱反射面であれば、凹部の内部に入射
した光が底面で異なる種々の方向に反射(乱反射)する
ので、観察方向によらず、凹部の内部が影として認識で
きるからである。また、凹部がより暗い領域に認識され
るので、凹部形成部以外の領域との明るさの違いが大き
くなり、認識マークを容易にかつ、より明確に認識する
ことができる。
In the first semiconductor device, it is preferable that the bottom surface of the concave portion serving as the recognition mark is an irregular reflection surface. If the bottom surface of the concave portion is a diffusely reflecting surface, light incident on the inside of the concave portion is reflected (diffusely reflected) in various directions different from the bottom surface, so that the inside of the concave portion can be recognized as a shadow regardless of the observation direction. Further, since the concave portion is recognized as a darker region, the difference in brightness from the region other than the concave portion forming portion becomes large, and the recognition mark can be easily and more clearly recognized.

【0010】凹部の底面を乱反射面とする場合、凹部の
底面を曲面形状にすれば容易に乱反射面を形成すること
ができる。あるいは、凹部の底面をその断面が鋸形状で
あるようにしても、容易に乱反射面を形成することがで
きる。
In the case where the bottom surface of the concave portion is a diffuse reflection surface, the irregular reflection surface can be easily formed by making the bottom surface of the concave portion a curved surface. Alternatively, the irregular reflection surface can be easily formed even when the bottom surface of the concave portion has a saw-shaped cross section.

【0011】本発明の第2の半導体装置は、認識マーク
をケースおよび電極端子と異なる色を有する材料また
は、それらと異なる反射率を有する材料をケースの所定
の場所に付すことによって形成する点において、上記第
1の半導体装置と異なる。このような第2の半導体装置
によっても、上記第1の半導体装置と同様に、ワイヤボ
ンディングの際に認識マークを正確に検出することがで
きるので、電極端子およびボンディングパッドの位置を
正確に算出して、精度良くワイヤボンディングを行うこ
とができる。
The second semiconductor device of the present invention is characterized in that the recognition mark is formed by applying a material having a different color from the case and the electrode terminal or a material having a different reflectance from the case and the electrode terminal to a predetermined place of the case. , Is different from the first semiconductor device. According to such a second semiconductor device, similarly to the first semiconductor device, since the recognition mark can be accurately detected at the time of wire bonding, the positions of the electrode terminals and the bonding pads can be accurately calculated. Thus, wire bonding can be performed with high accuracy.

【0012】本発明の半導体装置において、2以上の認
識マークをケースに設ければ、2以上の認識マークに基
づいて、半導体チップ上のボンディングパッドおよび電
極端子の位置をより正確に算出して、ボンディングワイ
ヤの接続位置をより高い精度で決定し、ワイヤボンディ
ングを行うことができる。
In the semiconductor device of the present invention, if two or more recognition marks are provided on the case, the positions of the bonding pads and the electrode terminals on the semiconductor chip can be calculated more accurately based on the two or more recognition marks. The connection position of the bonding wire can be determined with higher accuracy, and wire bonding can be performed.

【0013】2以上の認識マークが設けられる場合、認
識マークは、互いに対向する基板の第1の辺および第2
の辺側のケースのいずれにも形成され得る。あるいは、
基板の第1の辺に沿ってケース上に複数の認識マークが
形成されてもよい。
When two or more recognition marks are provided, the recognition marks are formed on the first side and the second side of the substrate facing each other.
Can be formed on any of the side cases. Or
A plurality of recognition marks may be formed on the case along the first side of the substrate.

【0014】半導体装置のケースにおいて、電極端子が
高さの異なる第1面および第2面に形成された場合、第
1面および第2面のいずれにも認識マークを設ければ、
高さの異なる位置に設けられた複数の認識マークの位置
の検出結果に基づいて、半導体チップ上のボンディング
パッドおよび電極端子の位置を3次元的に算出できるの
で、ボンディングワイヤの接続位置をより高い精度で決
定し、ワイヤボンディングを行うことができる。
In the case of the semiconductor device, when the electrode terminals are formed on the first surface and the second surface having different heights, if the recognition marks are provided on both the first surface and the second surface,
Since the positions of the bonding pads and the electrode terminals on the semiconductor chip can be calculated three-dimensionally based on the detection results of the positions of the plurality of recognition marks provided at different heights, the connection position of the bonding wire can be set higher. It can be determined with accuracy and wire bonding can be performed.

【0015】[0015]

【発明の実施の形態】実施形態1.図1(a)および図
1(b)を参照しながら本発明の実施形態1の半導体装
置20を説明する。図1(a)は半導体装置20の平面
図であり、図1(b)は図1(a)のA−A‘に対応す
る半導体装置20の断面図である。なお、図1(a)は
ワイヤボンディング後に設けられる蓋17を省略して示
す。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. The semiconductor device 20 according to the first embodiment of the present invention will be described with reference to FIGS. 1A and 1B. FIG. 1A is a plan view of the semiconductor device 20, and FIG. 1B is a cross-sectional view of the semiconductor device 20 corresponding to AA ′ in FIG. FIG. 1A omits a cover 17 provided after wire bonding.

【0016】本実施形態1の半導体装置20は、金属ベ
ース板9と、金属ベース板9の上に搭載された絶縁基板
15と、絶縁基板15の上に形成された回路パターン1
6と、回路パターン16に搭載された半導体チップ1
と、絶縁基板15を囲むように設けられたケース5とを
有する。ケース5は、ねじ14および接着剤を用いてそ
の下端が金属ベース板1に固着されており、上端には蓋
17が設けられる。ケース5と金属ベース板1と蓋17
とを合わせてパッケージと称する。このパッケージの内
部に、絶縁基板8および絶縁基板8上に設けられた各素
子が収容される。
The semiconductor device 20 according to the first embodiment includes a metal base plate 9, an insulating substrate 15 mounted on the metal base plate 9, and a circuit pattern 1 formed on the insulating substrate 15.
6 and the semiconductor chip 1 mounted on the circuit pattern 16
And a case 5 provided so as to surround the insulating substrate 15. The lower end of the case 5 is fixed to the metal base plate 1 using screws 14 and an adhesive, and a lid 17 is provided at the upper end. Case 5, metal base plate 1, and lid 17
Are collectively referred to as a package. Inside the package, the insulating substrate 8 and each element provided on the insulating substrate 8 are accommodated.

【0017】ケース5は、電極端子2をケース5の金型
に挿入したまま成形するインサートケース構造を有す
る。半導体装置20において、半導体チップ1と電極端
子2とは、半導体チップ1上のボンディングパッド13
と電極端子2とをアルミワイヤ3により結線するワイヤ
ボンディングによって接続される。ワイヤボンディング
には、例えば超音波振動を利用したワイヤボンディング
法が使用される。
The case 5 has an insert case structure in which the electrode terminal 2 is molded while being inserted into the mold of the case 5. In the semiconductor device 20, the semiconductor chip 1 and the electrode terminals 2 are connected to the bonding pads 13 on the semiconductor chip 1.
And the electrode terminals 2 are connected by wire bonding for connecting the aluminum wires 3. For the wire bonding, for example, a wire bonding method using ultrasonic vibration is used.

【0018】半導体チップ1と電極端子2とをアルミワ
イヤ3を用いて接続するには、半導体チップ1上のボン
ディングパッド13および接続端子2の正確な位置を検
出する必要がある。本実施形態1においては、半導体装
置のケース5を射出成形する際に、これと同時に電極端
子2近傍のケース5の一部に直径約1mm、深さ約0.
5mmの断面が円形の凹部4を形成する。すなわち、ケ
ース5の金型の所定の場所に凸部を設けておき、この金
型を用いてケースを射出成形することにより、ケースの
射出成形時に凹部4を形成する。
In order to connect the semiconductor chip 1 and the electrode terminals 2 using the aluminum wires 3, it is necessary to detect the exact positions of the bonding pads 13 and the connection terminals 2 on the semiconductor chip 1. In the first embodiment, when the case 5 of the semiconductor device is injection molded, at the same time, a part of the case 5 near the electrode terminal 2 has a diameter of about 1 mm and a depth of about 0.1 mm.
A 5 mm cross section forms a circular recess 4. That is, a convex portion is provided at a predetermined position of a mold of the case 5, and the case is injection-molded using the mold, so that the concave portion 4 is formed at the time of injection molding of the case.

【0019】このように形成された凹部4を、ワイヤボ
ンディングの際に半導体装置20をワイヤボンダ装置に
接続されたカメラで撮像することによって認識し、その
位置を検出する。凹部4の位置を基準とし、凹部4から
所定の距離および方向にあるボンディングパッド13お
よび電極端子2の位置座標をボンディングワイヤの接続
位置として決定する。これにより、ボンディングワイヤ
の一端を電極端子に接続し、ボンディングワイヤのもう
一端をボンディングパッドと接続して、ワイヤボンディ
ングを行う。
The recess 4 thus formed is recognized by imaging the semiconductor device 20 with a camera connected to the wire bonder device during wire bonding, and its position is detected. With reference to the position of the recess 4, the position coordinates of the bonding pad 13 and the electrode terminal 2 at a predetermined distance and direction from the recess 4 are determined as the connection positions of the bonding wires. Thus, one end of the bonding wire is connected to the electrode terminal, and the other end of the bonding wire is connected to the bonding pad, thereby performing wire bonding.

【0020】本実施形態1によると、ケース5の一部に
認識マークとして凹部4を設けることにより、半導体装
置20に光を照射したときに、凹部4の内部に入射光の
影が形成されて凹部4が暗い領域(黒い点)として認識
され、凹部4以外の部分は明るい領域として認識され
る。このように、明確な明るさの違いによって認識マー
クが正確に認識されるので、認識マークの位置に基づい
て、ボンディングパッド13と電極端子2の位置とを精
度良く検出し、ボンディング位置を精度良く決定でき
る。従って、半導体チップ1上のボンディングパッド1
3と電極端子2とを精度良くワイヤボンディングでき
る。また、認識マークの誤認識により、ワイヤボンディ
ング工程においてワイヤボンダ装置が停止してしまうこ
とを防止できる。
According to the first embodiment, by providing the concave portion 4 as a recognition mark on a part of the case 5, when the semiconductor device 20 is irradiated with light, a shadow of the incident light is formed inside the concave portion 4. The concave portion 4 is recognized as a dark region (black point), and the portion other than the concave portion 4 is recognized as a bright region. As described above, the recognition mark is accurately recognized based on a clear difference in brightness. Therefore, based on the position of the recognition mark, the position of the bonding pad 13 and the position of the electrode terminal 2 are accurately detected, and the bonding position is accurately detected. Can decide. Therefore, the bonding pad 1 on the semiconductor chip 1
3 and the electrode terminal 2 can be accurately wire-bonded. Further, it is possible to prevent the wire bonder device from stopping in the wire bonding process due to erroneous recognition of the recognition mark.

【0021】認識マークとしての凹部4は、横断面のサ
イズが直径0.07mm以上1.2mm以下であること
が好ましく、凹部4のサイズが上記の範囲にあれば、非
常に精度良く凹部4が画像認識される。なお上記の説明
において凹部4の横断面とは、凹部4の深さ方向に対し
て垂直な断面をいう。また、凹部の形状は、成形の容易
さを考慮すると横断面が円形であることが好ましい。凹
部の深さは、凹部4の検出に用いられる光源と半導体装
置との間の距離や、半導体装置に対する光源の方向など
によって適宜決定されるが、本発明では0.5mm以上
が好ましい。
The cross section of the recess 4 as a recognition mark preferably has a diameter of 0.07 mm or more and 1.2 mm or less. If the size of the recess 4 is within the above range, the recess 4 can be formed very accurately. The image is recognized. In the above description, the transverse section of the recess 4 refers to a section perpendicular to the depth direction of the recess 4. The shape of the recess is preferably circular in cross section in consideration of ease of molding. The depth of the concave portion is appropriately determined according to the distance between the light source used for detecting the concave portion 4 and the semiconductor device, the direction of the light source with respect to the semiconductor device, and the like. In the present invention, the depth is preferably 0.5 mm or more.

【0022】実施形態2.実施形態2の半導体装置は、
ワイヤボンディング用の認識マークである凹部4の底面
を乱反射面としたことにおいて、上述の実施形態1と異
なる。図2および図3に凹部4の底面形状の例を示す。
図2および図3はいずれもケース5に設けられた認識マ
ークである凹部の断面図である。
Embodiment 2 The semiconductor device according to the second embodiment includes:
The third embodiment differs from the first embodiment in that the bottom surface of the concave portion 4 serving as a recognition mark for wire bonding is an irregular reflection surface. 2 and 3 show examples of the shape of the bottom surface of the recess 4.
FIG. 2 and FIG. 3 are cross-sectional views of a concave portion which is a recognition mark provided on the case 5.

【0023】凹部4aの底面18aは、図2に示される
ように、所定の曲率半径を有するような曲面形状であ
り、凹部4aは、底面18aの中心部分18cがその周
辺部分18rよりも深くなるように形成されている。
As shown in FIG. 2, the bottom surface 18a of the concave portion 4a has a curved surface shape having a predetermined radius of curvature, and the central portion 18c of the concave portion 4a is deeper than its peripheral portion 18r. It is formed as follows.

【0024】また、凹部4bの底面18bは、図3に示
されるように、断面が鋸形状である。底面18bは、例
えば、断面が三角形で一定方向に延びる突起物19を多
数設けることによって形成してもよいし、あるいは、四
角錐状の突起物19を多数設けることによって形成して
もよい。
The bottom surface 18b of the recess 4b has a saw-like cross section as shown in FIG. The bottom surface 18b may be formed, for example, by providing a large number of projections 19 having a triangular cross section and extending in a fixed direction, or by providing a large number of projections 19 having a quadrangular pyramid shape.

【0025】図2の凹部4aおよび図3の凹部4aにお
いて、凹部内部に入射した光の進行方向を矢印6で示
す。凹部4a、4bの内部に入射した光はそれぞれ、底
面18a、18bで異なる種々の方向に反射(乱反射)
する。
In the concave portion 4a in FIG. 2 and the concave portion 4a in FIG. Light incident into the recesses 4a and 4b is reflected (diffuse reflection) in different directions at the bottom surfaces 18a and 18b, respectively.
I do.

【0026】従って、観察方向によらず凹部の暗さが同
程度に認識され、暗い領域として認識される凹部4a、
4bと明るい領域として認識される凹部4a、4b以外
の領域とにおいて、その明暗差が観察方向によらず一定
となるので、認識マークを容易に認識することができ
る。また、凹部4a、4bをより暗い領域として認識で
きるので、凹部形成部以外の部分との明るさの違いが大
きくなり、認識マークを容易にかつ、明確に認識するこ
とができる。
Therefore, regardless of the observation direction, the darkness of the concave portion is recognized to the same extent, and the concave portion 4a, which is recognized as a dark region,
Since the difference in brightness between the region 4b and the region other than the concave portions 4a and 4b recognized as bright regions is constant irrespective of the viewing direction, the recognition mark can be easily recognized. In addition, since the concave portions 4a and 4b can be recognized as darker regions, the difference in brightness from portions other than the concave portion forming portion becomes large, and the recognition mark can be easily and clearly recognized.

【0027】なお、実施形態2において、凹部の底面形
状は図2および図3に示されるものに限定されることは
ない。観察方向によらず凹部の暗さが同程度に認識さ
れ、凹部とそれ以外の領域の明暗差が観察方向によらず
一定となるような乱反射面であれば、様々な底面形状の
凹部を使用することができる。
In the second embodiment, the shape of the bottom surface of the concave portion is not limited to those shown in FIGS. If the irregularity is such that the darkness of the recess is recognized to the same degree regardless of the viewing direction and the difference between the brightness of the recess and the other area is constant regardless of the viewing direction, various recesses with different bottom shapes are used. can do.

【0028】実施形態3.実施形態3の半導体装置は、
認識マークの凹部4がケース5に2以上設けられること
において、上述の実施形態1と異なる。図4(a)〜
(c)を参照しながら本発明の実施形態3の半導体装置
20を説明する。図4(a)は半導体装置20の平面図
であり、図4(b)は図4(a)のB−B‘に対応する
半導体装置20の断面図であり、図4(c)は図4
(a)のC−C‘に対応する半導体装置20の断面図で
ある。なお、図4(a)はワイヤボンディング後に設け
られる蓋17を省略して示す。尚、図1と同様の部材は
同じ参照符号で示しており、その詳細な説明は省略す
る。
Embodiment 3 The semiconductor device according to the third embodiment includes:
Embodiment 2 is different from Embodiment 1 in that two or more recesses 4 of the recognition mark are provided in the case 5. FIG.
The semiconductor device 20 according to the third embodiment of the present invention will be described with reference to FIG. 4A is a plan view of the semiconductor device 20, FIG. 4B is a cross-sectional view of the semiconductor device 20 corresponding to BB ′ of FIG. 4A, and FIG. 4
FIG. 14A is a cross-sectional view of the semiconductor device 20 corresponding to CC ′. FIG. 4A omits a cover 17 provided after wire bonding. Note that the same members as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

【0029】図4(a)に示される実施形態3の半導体
装置20には、凹部4c、4dおよび4eからなる3つ
の認識マークがケース5に設けられている。半導体装置
20のケース5において、絶縁基板15の1つの辺15
b(第1の辺)に沿って凹部4dおよび4eが設けられ
ており、さらに、絶縁基板15の辺15bと対向する辺
15c(第2の辺)側に凹部4cが設けられている。
In the semiconductor device 20 of the third embodiment shown in FIG. 4A, the case 5 is provided with three recognition marks composed of the concave portions 4c, 4d and 4e. In case 5 of semiconductor device 20, one side 15 of insulating substrate 15
The recesses 4d and 4e are provided along b (first side), and further, the recess 4c is provided on the side 15c (second side) of the insulating substrate 15 facing the side 15b.

【0030】図4(b)および(c)に示されるよう
に、凹部4dおよび4eは、半導体装置20において同
じ高さを有するケース5の面に形成されているが、凹部
4cは、凹部4dおよび4eよりも高い面に形成されて
いる。
As shown in FIGS. 4B and 4C, the recesses 4d and 4e are formed on the surface of the case 5 having the same height in the semiconductor device 20, but the recess 4c is formed in the recess 4d. And 4e.

【0031】本実施形態3によると、認識マークを複数
設けることにより、複数の認識マークの位置に基づい
て、ボンディングワイヤの一端と接続する電極端子の位
置と、ボンディングワイヤのもう一端と接続するボンデ
ィングパッドの位置とを算出できるので、より精度良く
ボンディングワイヤの接続位置を決定し、ワイヤボンデ
ィングを行うことができる。
According to the third embodiment, by providing a plurality of recognition marks, the positions of the electrode terminals connected to one end of the bonding wire and the bonding terminals connected to the other end of the bonding wire are determined based on the positions of the plurality of recognition marks. Since the position of the pad can be calculated, the connection position of the bonding wire can be determined with higher accuracy, and wire bonding can be performed.

【0032】また、高さの異なる面に認識マークを設け
ることにより、認識マークの位置に基づいて、ボンディ
ングワイヤの一端と接続する電極端子の位置と、ボンデ
ィングワイヤのもう一端と接続するボンディングパッド
の位置とを3次元で算出できるので、より精度良くボン
ディングワイヤの接続位置を決定し、ワイヤボンディン
グを行うことができる。
Further, by providing the recognition marks on the surfaces having different heights, the positions of the electrode terminals connected to one end of the bonding wire and the bonding pads of the bonding pads connected to the other end of the bonding wire are determined based on the positions of the recognition marks. Since the position and the position can be calculated in three dimensions, the connection position of the bonding wire can be determined more accurately, and the wire bonding can be performed.

【0033】実施形態4.実施形態4の半導体装置は、
認識マークを凹部によって形成するのではなく、ケース
5および電極端子2と異なる色を有する材料をケース5
の所定の位置に付して認識マークとすることにおいて、
上述の実施形態1〜3と異なる。認識マークは、例えば
図1(a)の凹部4、または図4の凹部4c〜4eと同
様の場所に設けられる。
Embodiment 4 FIG. The semiconductor device according to the fourth embodiment includes:
Instead of forming the recognition mark by the concave portion, a material having a color different from that of the case 5 and the electrode terminal 2 may be used.
In attaching to the predetermined position of the above and making it a recognition mark,
This is different from the first to third embodiments. The recognition mark is provided, for example, at the same location as the concave portion 4 in FIG. 1A or the concave portions 4c to 4e in FIG.

【0034】本実施形態4の半導体装置においては、例
えばPPS(ポリフェニレンサルファイド樹脂)を用い
て黒色のケース5を作製し、ケース5および電極端子2
とは異なる色(例えば白色)のPPSやナイロン樹脂を
ケース5の所定の場所に設け、これを認識マークとして
使用する。
In the semiconductor device of the fourth embodiment, a black case 5 is manufactured using, for example, PPS (polyphenylene sulfide resin), and the case 5 and the electrode terminals 2 are formed.
PPS or nylon resin of a different color (for example, white) is provided at a predetermined location of the case 5 and is used as a recognition mark.

【0035】このように本実施形態4によると、周囲の
色とは異なる色を有する材料を付して認識マークとする
ことにより、色の違いから良好に認識マークを検出する
ことができるので、認識マークの誤認識を防止すること
ができる。また、ケースおよび電極端子とは異なる反射
率を有する材料を所定の場所に付すことによっても、良
好に認識マークを検出することができるので、認識マー
クの誤認識を防止することができる。
As described above, according to the fourth embodiment, since the recognition mark is formed by attaching a material having a color different from the surrounding color, the recognition mark can be detected satisfactorily from the difference in color. Erroneous recognition of the recognition mark can be prevented. In addition, by attaching a material having a reflectance different from that of the case and the electrode terminal to a predetermined location, the recognition mark can be detected well, so that erroneous recognition of the recognition mark can be prevented.

【0036】上述の実施形態1〜4においては、電極端
子がインサート成形されたケースが金属ベース板に接着
されたパッケージを有する半導体装置について説明した
が、本発明はこのような半導体装置に限定されず、例え
ばケースとベース板とが一体となったパッケージを有す
る半導体装置など、様々な形態の半導体装置に適用する
ことが可能である。また、実施形態1〜4は、適宜組み
合わせて利用することができる。
In the first to fourth embodiments, the semiconductor device having the package in which the case in which the electrode terminal is insert-molded is adhered to the metal base plate has been described. However, the present invention is limited to such a semiconductor device. Instead, the present invention can be applied to various types of semiconductor devices such as a semiconductor device having a package in which a case and a base plate are integrated. Embodiments 1 to 4 can be used in appropriate combinations.

【0037】[0037]

【発明の効果】上述のように、本発明の半導体装置によ
ると、認識マークが半導体装置のケースに設けられてい
るので、ボンディングワイヤを設ける際に、精度良く認
識マークを検出することができる。この検出結果によ
り、ボンディングワイヤの一端に接続する電極端子の位
置と、ボンディングワイヤのもう一端に接続する半導体
チップ上のボンディングパッドの位置とを正確に算出し
て、ボンディングワイヤの接続位置を精度良く決定する
ことができる。従って、認識マークの誤認識により、ボ
ンディング工程においてワイヤボンダ装置が停止してし
まうことを防止できる。
As described above, according to the semiconductor device of the present invention, since the recognition mark is provided on the case of the semiconductor device, the recognition mark can be accurately detected when the bonding wire is provided. Based on this detection result, the position of the electrode terminal connected to one end of the bonding wire and the position of the bonding pad on the semiconductor chip connected to the other end of the bonding wire are accurately calculated, and the connection position of the bonding wire is accurately determined. Can be determined. Therefore, it is possible to prevent the wire bonder device from stopping in the bonding process due to erroneous recognition of the recognition mark.

【0038】ボンディングワイヤの接続位置を決定する
ための認識マークを、凹部から形成すると、ワイヤボン
ダ装置が明確な明るさの違いによって認識マークを正確
に認識できるので、ボンディングワイヤの接続位置をよ
り精度良く決定してワイヤボンディングを行うことがで
きる。
If the recognition mark for determining the connection position of the bonding wire is formed from the concave portion, the wire bonder can accurately recognize the recognition mark by a clear difference in brightness, so that the connection position of the bonding wire can be more accurately determined. Once determined, wire bonding can be performed.

【0039】上記凹部の底面が乱反射面であれば、観察
方向によらず、凹部を容易にかつ、より明確に認識する
ことができる。
If the bottom surface of the concave portion is a diffusely reflecting surface, the concave portion can be easily and more clearly recognized regardless of the observation direction.

【0040】凹部の底面を乱反射面とする場合、凹部の
底面を曲面形状にすれば容易に乱反射面を形成すること
ができる。あるいは、凹部の底面をその断面が鋸形状で
あるようにしても、容易に乱反射面を形成することがで
きる。
In the case where the bottom surface of the concave portion is an irregular reflection surface, the irregular reflection surface can be easily formed by making the bottom surface of the concave portion a curved surface. Alternatively, the irregular reflection surface can be easily formed even when the bottom surface of the concave portion has a saw-shaped cross section.

【0041】また、認識マークをケースおよび電極端子
と異なる色を有する材料または、それらと異なる反射率
を有する材料をケースの所定の場所に付すことによって
形成しても、ワイヤボンディングの際に認識マークを正
確に検出することができるので、電極端子およびボンデ
ィングパッドの位置を正確に算出して、精度良くワイヤ
ボンディングを行うことができる。
Further, even if the recognition mark is formed by applying a material having a different color from the case and the electrode terminal or a material having a different reflectance from the case and the electrode terminal to a predetermined place of the case, the recognition mark is not formed at the time of wire bonding. Can be detected accurately, so that the positions of the electrode terminals and the bonding pads can be accurately calculated, and the wire bonding can be performed with high accuracy.

【0042】本発明の半導体装置において、2以上の認
識マークをケースに設ければ、2以上の認識マークに基
づいて、半導体チップ上のボンディングパッドおよび電
極端子の位置をより正確に算出して、ボンディングワイ
ヤの接続位置をより高い精度で決定し、ワイヤボンディ
ングを行うことができる。
In the semiconductor device of the present invention, if two or more recognition marks are provided on the case, the positions of the bonding pads and the electrode terminals on the semiconductor chip can be calculated more accurately based on the two or more recognition marks. The connection position of the bonding wire can be determined with higher accuracy, and wire bonding can be performed.

【0043】2以上の認識マークが設けられる場合、認
識マークは、互いに対向する基板の第1の辺および第2
の辺側のケースのいずれにも形成され得る。あるいは、
基板の第1の辺に沿ってケース上に複数の認識マークが
形成されてもよい。
When two or more recognition marks are provided, the recognition marks are formed on the first side and the second side of the substrate facing each other.
Can be formed on any of the side cases. Or
A plurality of recognition marks may be formed on the case along the first side of the substrate.

【0044】半導体装置のケースにおいて、電極端子が
高さの異なる第1面および第2面に形成された場合、第
1面および第2面のいずれにも認識マークを設ければ、
高さの異なる位置に設けられた複数の認識マークの位置
の検出結果に基づいて、半導体チップ上のボンディング
パッドおよび電極端子の位置を3次元的に算出できるの
で、ボンディングワイヤの接続位置をより高い精度で決
定し、ワイヤボンディングを行うことができる。
In the case of the semiconductor device, when the electrode terminals are formed on the first surface and the second surface having different heights, if the recognition marks are provided on both the first surface and the second surface,
Since the positions of the bonding pads and the electrode terminals on the semiconductor chip can be calculated three-dimensionally based on the detection results of the positions of the plurality of recognition marks provided at different heights, the connection position of the bonding wire can be set higher. It can be determined with accuracy and wire bonding can be performed.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 (a)は実施形態1の半導体装置の平面図で
あり、(b)は(a)のA−A‘に対応する半導体装置
の断面図である。
FIG. 1A is a plan view of a semiconductor device according to a first embodiment, and FIG. 1B is a cross-sectional view of the semiconductor device corresponding to AA ′ in FIG.

【図2】 実施形態2の半導体装置における凹部の断面
図である。
FIG. 2 is a sectional view of a concave portion in the semiconductor device according to the second embodiment;

【図3】 実施形態2の半導体装置における凹部の断面
図である。
FIG. 3 is a sectional view of a concave portion in the semiconductor device according to the second embodiment;

【図4】 (a)は実施形態3の半導体装置の平面図で
あり、(b)は(a)のB−B‘に対応する半導体装置
の断面図であり、(c)は(a)のC−C‘に対応する
半導体装置の断面図である。
4A is a plan view of a semiconductor device according to a third embodiment, FIG. 4B is a cross-sectional view of the semiconductor device corresponding to BB ′ in FIG. 4A, and FIG. 13 is a cross-sectional view of the semiconductor device corresponding to line CC ′ of FIG.

【図5】 一般的な半導体装置の平面図である。FIG. 5 is a plan view of a general semiconductor device.

【符号の説明】[Explanation of symbols]

1 半導体チップ、 2 電極端子、 3 アルミワイ
ヤ、 4、4a、4b、4c、4d、4e 凹部、 5
ケース、 6 光の進行方向、 14 ねじ、 15
絶縁基板、 16 回路パターン、 17蓋、18
a、18b 底面、19 突起物、 20 半導体装
置。
Reference Signs List 1 semiconductor chip, 2 electrode terminal, 3 aluminum wire, 4, 4a, 4b, 4c, 4d, 4e recess, 5
Case, 6 light traveling direction, 14 screws, 15
Insulating substrate, 16 circuit patterns, 17 lids, 18
a, 18b bottom surface, 19 protrusion, 20 semiconductor device.

Claims (10)

【特許請求の範囲】[Claims] 【請求項1】 基板上に搭載された半導体チップと、 電極端子がインサート成形されたケースを有し、前記基
板および前記半導体チップを収容するパッケージと、 前記半導体チップと前記電極端子とを接続するボンディ
ングワイヤとを備えた半導体装置において、 前記ケースは、前記ボンディングワイヤを設ける際に、
前記ボンディングワイヤの接続位置を決定するための認
識マークを有することを特徴とする半導体装置。
1. A semiconductor chip mounted on a substrate, a case having electrode terminals insert-molded therein, and a package accommodating the substrate and the semiconductor chip, and connecting the semiconductor chip and the electrode terminals. A semiconductor device comprising: a bonding wire; wherein the case comprises:
A semiconductor device having a recognition mark for determining a connection position of the bonding wire.
【請求項2】 前記認識マークは凹部からなる請求項1
に記載の半導体装置。
2. The recognition mark according to claim 1, wherein the recognition mark comprises a recess.
3. The semiconductor device according to claim 1.
【請求項3】 前記凹部の底面は乱反射面である請求項
2に記載の半導体装置。
3. The semiconductor device according to claim 2, wherein a bottom surface of said concave portion is a diffuse reflection surface.
【請求項4】 前記凹部の前記底面は曲面形状である請
求項3に記載の半導体装置。
4. The semiconductor device according to claim 3, wherein said bottom surface of said concave portion has a curved surface shape.
【請求項5】 前記凹部の前記底面は断面が鋸形状であ
る請求項3に記載の半導体装置。
5. The semiconductor device according to claim 3, wherein the bottom surface of the concave portion has a saw-shaped cross section.
【請求項6】 前記認識マークは、前記ケースおよび前
記電極端子とは異なる色または異なる反射率を有する材
料を前記ケースに付すことにより形成される請求項1に
記載の半導体装置。
6. The semiconductor device according to claim 1, wherein the recognition mark is formed by applying a material having a different color or a different reflectance from the case and the electrode terminal to the case.
【請求項7】 前記ケースは、2以上の認識マークを有
する請求項1から6のいずれかに記載の半導体装置。
7. The semiconductor device according to claim 1, wherein said case has two or more recognition marks.
【請求項8】 前記ケースは前記基板を包囲し、前記基
板は互いに対向する第1の辺および第2の辺を有し、前
記ケースは、前記第1の辺側と前記第2の辺側とに認識
マークを有する請求項7に記載の半導体装置。
8. The case surrounds the substrate, the substrate has a first side and a second side facing each other, and the case includes the first side and the second side. 8. The semiconductor device according to claim 7, further comprising a recognition mark.
【請求項9】 前記ケースは、前記基板の前記第1の辺
に沿って少なくとも2つの認識マークを有する請求項8
に記載の半導体装置。
9. The case has at least two identification marks along the first side of the substrate.
3. The semiconductor device according to claim 1.
【請求項10】 前記ケースにおいて、前記電極端子は
高さの異なる第1面および第2面に形成され、 前記第1面および前記第2面のそれぞれに認識マークが
設けられた請求項7から9のいずれかに記載の半導体装
置。
10. The method according to claim 7, wherein in the case, the electrode terminals are formed on first and second surfaces having different heights, and a recognition mark is provided on each of the first and second surfaces. 10. The semiconductor device according to any one of 9.
JP2000330468A 2000-10-30 2000-10-30 Semiconductor device Expired - Fee Related JP4102541B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000330468A JP4102541B2 (en) 2000-10-30 2000-10-30 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000330468A JP4102541B2 (en) 2000-10-30 2000-10-30 Semiconductor device

Publications (2)

Publication Number Publication Date
JP2002134552A true JP2002134552A (en) 2002-05-10
JP4102541B2 JP4102541B2 (en) 2008-06-18

Family

ID=18806983

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP4102541B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7291928B2 (en) 2002-08-30 2007-11-06 Mitsubishi Denki Kabushiki Kaisha Electric power semiconductor device
JP2015043400A (en) * 2013-07-26 2015-03-05 本田技研工業株式会社 Resin case of semiconductor device and method for manufacturing the same
JP2016086009A (en) * 2014-10-23 2016-05-19 株式会社ケーヒン Electric power conversion system

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7291928B2 (en) 2002-08-30 2007-11-06 Mitsubishi Denki Kabushiki Kaisha Electric power semiconductor device
US7663252B2 (en) 2002-08-30 2010-02-16 Mitsubishi Denki Kabushiki Kaisha Electric power semiconductor device
US7969025B2 (en) 2002-08-30 2011-06-28 Mitsubishi Denki Kabushiki Kaisha Electric power semiconductor device
JP2015043400A (en) * 2013-07-26 2015-03-05 本田技研工業株式会社 Resin case of semiconductor device and method for manufacturing the same
JP2016086009A (en) * 2014-10-23 2016-05-19 株式会社ケーヒン Electric power conversion system

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