JP2002125172A - Video signal magnification reduction circuit and television receiver using it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a video signal magnification reduction circuit that suppresses deterioration in the image quality in the case of outputting a signal with an aspect ratio of 4:3 from a device with an aspect ratio of 16:9. SOLUTION: The video signal magnification reduction circuit is provided with a magnified coefficient/reduced coefficient generating means that takes five states resulting from combinations of cases where a magnification coefficient is decreased, constant or increased and a reduction coefficient is increased, constant or decreased with attendance on a change in a horizontal position of a video signal, a video horizontal reduction means that used the reduction coefficient so as to reduce the input video signal at a reduction rate of 1/(1+reduction coefficient), and a video horizontal magnification means that uses the magnification coefficient to magnify the signal subjected to horizontal reduction at a magnification factor of 1/(1-magnification coefficient).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for scaling a video signal.

[0002]

2. Description of the Related Art With the spread of digital video media, a moving image signal processing system has become necessary to handle various forms of moving images. For example, digital satellite broadcasting using broadcasting satellites is centered on high-definition image (HDTV) broadcasting, and 480I (720 dots × 240 lines / field), 480I
P (720dot × 480line / field), 720P (1280
dot × 720 line / field), 1080I (1920 dot × 5
A moving image format having a plurality of different resolutions such as 40 lines / field) is adopted. Of these, 720P, 1080I
Has an aspect ratio of 16: 9 and 4
For 80I and 480P, the aspect ratio is 16: 9
And 4: 3. Along with this, it is considered that wide-screen display devices having an aspect ratio of 16: 9 will increase in the future, and technology for converting a conventional 4: 3 aspect ratio video to a 16: 9 aspect ratio will be used. Is important. FIG. 16 shows an example in which a video having an aspect ratio of 4: 3 as described above is output to a display device having an aspect ratio of 16: 9. When a video signal having an aspect ratio of 4: 3 as shown in (a) is displayed on a full screen in accordance with a wide screen having an aspect ratio of 16: 9, the video signal is horizontally extended by 4/3 times as shown in (b). It becomes the image which was done.
Also, if you want to keep the image aspect ratio unchanged,
As shown in (c), it is necessary to add a region in which no image is displayed on the left and right. As shown in (d), as a technique that has been actively performed in recent years, there is a technique of increasing the enlargement / reduction magnification toward the left or right end while keeping the horizontal enlargement / reduction magnification at the center of the screen small. By using the present technology, it is possible to display an image on the entire wide screen while keeping the aspect ratio at the center of the image almost the same as that of the original image. Hereinafter, this technique is referred to as side stretch.
Japanese Patent Application Laid-Open No. 9-8396 describes an example of this side stretch.
There is a technique described in Japanese Patent Application Publication No. 0-205. FIG. 17 is an explanatory diagram of a case where a 480I format video signal having an aspect ratio of 4: 3 is converted to a 480I format video signal having an aspect ratio of 16: 9. In order to perform the side stretching, a reduction operation in which the enlargement / reduction ratio is smaller than 1 is performed in the center of the screen, and an enlargement operation in which the enlargement / reduction ratio is larger than 1 is performed in the left and right portions of the screen. JP-A-9-83
The technique described in Japanese Patent Application Publication No. 960 is to perform side stretching by performing horizontal reduction at a fixed magnification on an input video signal and then performing horizontal expansion at a variable magnification. Using the circuit described in this publication, reduction / enlargement of an image of 480I with an aspect ratio of 4: 3 to a display device with a resolution of 480I with an aspect ratio of 16: 9 while maintaining the same number of horizontal pixels. The outline is as shown in FIG.

[0003]

In the above-mentioned prior art, a 480I image having an aspect ratio of 4: 3 is converted to an image having an aspect ratio of 16: 9 while maintaining the same number of horizontal pixels.
When the image is output to a display device having a resolution of 80I, the image is reduced at a constant magnification in the horizontal direction, and then a side stretching operation is performed. In that case, reduction is performed in the left and right portions of the screen to be finally enlarged by the same amount as the central portion. For example, in FIG. 17, first, the entire image is reduced at a reduction ratio of 0.8 at the center, and then the side stretch is enlarged. At this time, at the left and right ends, it is necessary to perform the magnification of 2.5 (2.0 / 0.8) times after performing the reduction of 0.8 times.
Therefore, in the above-described conventional technology, even the area that does not need to be reduced is reduced and then enlarged, and there is a possibility that good image quality may not be obtained. Also, when performing only normal side stretching, the enlargement magnification becomes too large in the left and right portions of the screen, resulting in an unnatural image. This is because the enlargement / reduction ratio is expressed as a fractional function instead of a linear function with respect to the horizontal position. Further, when the output horizontal position in FIG. 17 is around 240 or 480, the inclination of the enlargement / reduction ratio changes abruptly.
The image may become unnatural at the abrupt change point. It is an object of the present invention to (a) perform appropriate reduction or enlargement of a necessary portion in a screen, (b) prevent the enlargement ratio from becoming excessively large, and prevent a sudden change in the inclination of the enlargement / reduction ratio. And a natural image can be obtained. An object of the present invention is to provide a technique capable of solving such a problem.

[0004]

According to the present invention, there is provided a video signal enlargement / reduction circuit for enlarging or reducing a video signal. Decreases, is constant or increases, and the reduction factor increases,
Enlargement coefficient / reduction coefficient generating means for achieving a state of combination with the case where the input image signal is constant or decreasing, and reduction of the input video signal in which the reduction ratio is 1 / (1 + reduction coefficient) using the reduction coefficient Means for performing video horizontal reduction, and a magnification of 1 /
(1—enlargement coefficient). (2) As a video signal enlargement / reduction circuit for enlarging or reducing a video signal, a first state in which an enlargement coefficient decreases and a reduction coefficient increases with a change in the horizontal position according to the range of the horizontal position of the video signal, A second state in which the coefficient is constant and the reduction coefficient increases; a third state in which the expansion coefficient and the reduction coefficient are constant; a fourth state in which the expansion coefficient is constant and the reduction coefficient decreases; Enlargement coefficient / reduction coefficient generation means for causing a fifth state in which the reduction coefficient decreases,
By using the above reduction coefficient, the reduction ratio for the input video signal is 1
/ (1 + reduction coefficient) a video horizontal reduction means for performing reduction, and an image horizontal for performing the expansion using the above expansion coefficient with a magnification of 1 / (1−enlargement coefficient) for the horizontally reduced signal. And enlarging means. (3) As a video signal enlargement / reduction circuit for enlarging or reducing a video signal, a first state in which the enlargement coefficient decreases and the reduction coefficient increases with a change in the horizontal position according to the range of the horizontal position of the video signal; A second state in which the coefficient decreases and the reduction coefficient is constant; a third state in which the expansion coefficient and the reduction coefficient are constant; a fourth state in which the expansion coefficient increases and the reduction coefficient is constant; Enlargement coefficient / reduction coefficient generation means for causing a fifth state in which the reduction coefficient decreases,
By using the above reduction coefficient, the reduction ratio for the input video signal is 1
/ (1 + reduction coefficient) a video horizontal reduction means for performing reduction, and an image horizontal for performing the expansion using the above expansion coefficient with a magnification of 1 / (1−enlargement coefficient) for the horizontally reduced signal. And enlarging means. (4) In the above (2) or (3), the horizontal region of the video signal is divided into five regions, the rightmost region on the display screen is a first region, and the central region is a third region, The left end area is a fifth area, the area between the first area and the third area is a second area, and the third area and the fifth area are the same.
A region between the regions is defined as a fourth region, and the enlargement coefficient / reduction coefficient generation means performs the first state in the first region, the second state in the second region, and the third region. The third in the area of
, The fourth area, the fourth state, and the fifth area, the fifth state, so that the expansion coefficient and the reduction coefficient are generated. (5) As a video signal enlargement / reduction circuit for enlarging or reducing a video signal, means for increasing or decreasing a predetermined coefficient according to a change in the horizontal position of the video signal, and each time the horizontal position of the video signal changes by one pixel A configuration including: an enlargement coefficient generation unit that increases or decreases an enlargement coefficient by the predetermined coefficient, and a video horizontal enlargement unit that enlarges an input video signal by an enlargement factor of 1 / (1−enlargement coefficient). I do. (6) As a video signal enlargement / reduction circuit for enlarging or reducing a video signal, means for increasing or decreasing a predetermined coefficient according to a change in the horizontal position of the video signal, and each time the horizontal position of the video signal changes by one pixel A reduction coefficient generating means for increasing or decreasing the reduction coefficient by the predetermined coefficient, and a video horizontal reduction means for reducing the input video signal by a reduction ratio of 1 / (1 + reduction coefficient). . (7) A television receiver comprising the video signal enlargement / reduction circuit according to any one of the above (1) to (6) and capable of enlarging or reducing the video signal. The above (1) to (4) correspond to the problem (a), and the above (5) to (6) correspond to the problem (b).

[0005]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a first embodiment of the present invention. In FIG. 1, 101 is an input video signal, 10
2 is an input clock enable (clock enable synchronized with an input video signal), 103 is a video signal horizontal reduction circuit, 104 is a reduction coefficient, 105 is a reduction coefficient generation circuit,
06 is the horizontal reduced video signal, 107 is the clock enable of the horizontal reduced video signal, 110 is the horizontal synchronization signal, 111 is the initial value of the reduction coefficient, 112 is the horizontal position of the input video signal,
113 is a coefficient addition stop position, 114 is a coefficient addition restart position, 115 is a slope of a reduction coefficient, 120 is a flip-flop, 121 is a reduction coefficient selector, 122 and 123 are adders, 124 and 125 are comparators, and 126 and 127 are A selector, 130 is a video signal vertical scaling circuit, 141 is a vertical scaling video signal (a video signal expanded or reduced in the vertical direction), 142 is an output clock enable (clock enable synchronized with the output video signal), and 143 is a video Signal horizontal enlargement circuit, 144 is an enlargement coefficient, 145 is an enlargement coefficient generation circuit, 146 is an output video signal, 150 is a horizontal synchronization signal, 151 is an initial value of an enlargement coefficient, 152 is a horizontal position of an output video signal, and 153 is a coefficient addition. A stop position, 154 is a coefficient addition restart position, 155 is a slope of an expansion coefficient, 160 is a flip-flop, The expansion coefficient selector, 162,
63 is an adder, 164 and 165 are comparators, 166 and 16
Reference numeral 7 denotes a selector. Note that the horizontal position 1 of the input video signal
Numeral 12 denotes a numerical value which is reset by the horizontal synchronizing signal 110 and is increased by the clock enable 102, which is the output of the counter. Similarly, the horizontal position 152 of the output video signal is reset by the horizontal synchronization signal 150 and indicates a numerical value which is the output of the counter which is increased by the output clock enable 142. Reference numerals 113, 114, 153, and 154 are fixed numerical values that are set by registers and indicate the respective positions.

First, the overall flow of signals in the circuit shown in FIG. 1 will be described. Video signal horizontal reduction circuit 103
Represents a reduction ratio = 1 / (1+
The image is horizontally reduced by a reduction coefficient 104) and output as a horizontally reduced video signal 106. The video signal vertical enlargement / reduction circuit 130 performs vertical enlargement or reduction processing on the horizontal reduced video signal 106 and outputs the result as a vertical enlarged / reduced video signal 141. The video signal horizontal enlargement circuit 143 performs horizontal enlargement on the vertical enlargement / reduction image signal 141 so that the enlargement ratio = 1 / (1−enlargement coefficient 144), and outputs the output image signal 14.
Output as 6. Next, the operation of the flip-flop with an enable such as the flip-flop 120 used in this embodiment will be described. Flip-flop 120
Are the clock, clock enable (en), input data (d), load timing (L), and load value (L
D) is input, and output data (Q) is output. Here, the symbol shown in parentheses is the flip-flop 1 in FIG.
This is the symbol shown in FIG. When the clock enable is 1 at the rising edge of the clock, the load value (LD) is 1 if the load timing (L) is 1, and the input data (d) is 0 if the load timing (L) is 0.
Are output as output data (Q). If the clock enable is 0 at the rise of the clock, the previous value of the output data (Q) is held.

Hereinafter, the internal operation of the reduction coefficient generating circuit 105 will be described. When the horizontal synchronization signal 110 is input, the flip-flop 120 outputs the initial value 11 of the reduction coefficient.
In other cases, the output from the reduction coefficient selector 121 is delayed by one pixel and output as the reduction coefficient 104. The adder 122 performs addition between the reduction coefficient 104 one pixel before and the gradient 115 of the reduction coefficient, and outputs the result to the input A of the reduction coefficient selector 121. In the adder 123, 1
The reduction coefficient gradient 115 is subtracted from the reduction coefficient 104 before the pixel, and the result is output to the input B of the reduction coefficient selector 121. Next, the internal operation of the reduction coefficient selector 121 will be described. The selector 126 controls the horizontal position 112 of the input video signal.
Is smaller than the coefficient addition stop position 113, the output of the adder 122 is selected. Otherwise, the output of the selector 127 is selected. The selector 127 selects the output of the adder 123 when the horizontal position 112 of the input video signal is larger than the coefficient addition restart position 114, and otherwise selects the reduction coefficient 104 one pixel before. That is, in the reduction coefficient selector 121, according to the horizontal position 112 of the input video signal,
An input A which is an output of the adder 122, an input B which is an output of the adder 123, and an input C which is a reduction coefficient 104 of one pixel before.
Of the flip-flop 12
Output to 0. Next, the internal operation of the expansion coefficient generation circuit 145 will be described. When the horizontal synchronizing signal 150 is input, the flip-flop 160 sets the initial value 15
1 is read and output as the enlargement factor 144. Otherwise, the flip-flop 160 delays the output from the expansion coefficient selector 161 by one pixel and
Output as 4. The adder 162 subtracts the slope 155 of the expansion coefficient from the expansion coefficient 144 one pixel before, and outputs the result to the input A of the expansion coefficient selector 161. In the adder 163, the enlargement coefficient 144 and the inclination 155 of the enlargement coefficient one pixel before the current pixel are calculated.
Between the input B and the input B of the expansion coefficient selector 161.
Output to Next, the internal operation of the expansion coefficient selector 161 will be described. The selector 166 selects the output of the adder 162 when the horizontal position 152 of the output video signal is smaller than the coefficient addition stop position 153, and otherwise selects the output of the selector 167. The selector 167 selects the output of the adder 163 when the horizontal position 152 of the output video signal is larger than the coefficient addition restart position 154, and otherwise selects the enlargement coefficient 144 one pixel before. That is, in the enlargement coefficient selector 161, the horizontal position 1 of the output video signal is
52, the input A which is the output of the adder 162, the input B which is the output of the adder 163, the enlargement coefficient 144 for the previous pixel.
Is selected from the three inputs C and output to the flip-flop 160.

FIG. 2 shows a configuration example of the video signal horizontal reduction circuit 103 shown in FIG. 2, reference numeral 201 denotes an interpolation circuit, 202 denotes a reduction control circuit, 203 denotes an interpolation coefficient, and 20 denotes an interpolation coefficient.
4 is a flip-flop, 210 is an adder, 211 is ca
rry signal (signal indicating carry of adder 210), 2
12, 213 are flip-flops, 214 is a pixel thinning signal, 215 is an inverter circuit, 216 is an AND circuit,
220 is a flip-flop, 221 and 222 are adders,
223 is a multiplier. FIG. 3 shows that the reduction coefficient 104 is 1 /
4 shows a time chart in the case of 4 / 5-times reduction according to the definition (reduction magnification = 1 / (1 + reduction coefficient)). FIG.
(A) is a reduction coefficient 104, (A) is a clock, (C) is an input clock enable 102, (D) is an interpolation coefficient 203, (E) is an output of the adder 210, (F)
Is the input of the flip-flop 213, and (g) is carry
The signal 211, (h) is the pixel thinning signal 214, (h) is the clock enable 107 of the horizontal reduced video signal, (h)
Is the signal A in the interpolation circuit 201, and
The signal B in () is the signal C in the interpolation circuit 201,
(S) is the horizontal reduced video signal 106.

First, the internal operation of the reduction control circuit 202 in FIG. 2 will be described. In the adder 210, the reduction coefficient 1
04 and the interpolation coefficient 203 one pixel before are added. Here, the reduction coefficient 104 and the interpolation coefficient 203 are values of 0 or more and less than 1. The output of the adder 210 has the most significant bit as ca
The flip-flop 212 outputs the rry signal 211 to the flip-flop 212 and the other bits to the flip-flop 213. In the example of FIG. 3, the adder 210 shown in FIG.
Is 1/4, 2/4, 3/4 and 0 or more and less than 1, the value as it is becomes the input of the flip-flop 213 shown in (f), and the carry signal shown in (g) 211 becomes 0. On the other hand, the adder 21 shown in FIG.
When the output of 0 becomes 4/4 and a value of 1 or more, the most significant bit is deleted. That is, 0/4 obtained by subtracting 1 becomes the input of the flip-flop 213 shown in (f), and the carry signal 211 shown in (g) becomes 1. The flip-flop 212 delays the carry signal 211 by one input pixel, and outputs the result as the pixel thinning signal 214 at the timing shown in FIG. In the AND circuit, the inverted signal of the pixel thinning signal 214 and the input clock enable 1
By performing an AND of 02, a clock enable 107 of the horizontal reduced video signal with unnecessary data portions thinned out is obtained. This is the signal shown in FIG. The flip-flop 213 uses the clock enable 107 of the horizontal reduced video signal, delays the output by one pixel, and outputs the result as the interpolation coefficient 203. With the above operation, the interpolation coefficient 20
3 is a value that increases by the reduction coefficient 104 for each output pixel in the range of 0 or more and less than 1 as shown in FIG.
The interpolation circuit 201 outputs the output (A) of the flip-flop 220, the input video signal 101 (B), and the interpolation coefficient 203.
Using (α), C = (1−α) A + αB is output. The flip-flop 204 thins out unnecessary signals by synchronizing the output (C) with the clock enable 107 of the horizontal reduced video signal. That is, in the example shown in FIG. 3C, 0 / 4f + 4 / 4e is thinned out. By operating as described above, a, b, c, d,
From the five pixels e, as shown in FIG.
/ 4c + 3 / 4b, 2 / 4d + 2 / 4c, 3 / 4e + 1
/ 4d are generated. That is, this is 4
This means that a / 5-fold reduction operation has been performed.

FIG. 4 shows a configuration example of the video signal horizontal enlargement circuit 143 shown in FIG. Here, 251 is a memory circuit, 252 is an interpolation circuit, 253 is an AND circuit, 254 is an inverter circuit, 255 is an enlargement control circuit, 256 is an interpolation coefficient, 257 is a pixel supplement signal, 258 is an input clock enable of the enlargement circuit, 260 Are adders, 261, 270
Is a flip-flop, 271 and 272 are adders, 273
Is a multiplier.

FIG. 5 shows that the enlargement coefficient 144 is 1/5, that is, 5/4 according to the definition (enlargement ratio = 1 / (1-enlargement coefficient)).
The time chart in the case of double magnification is shown. (A) is an expansion coefficient 144, (A) is a clock, (C) is an output clock enable 142, (D) is an interpolation coefficient 256, (E) is an output of the adder 260, and (F) is an input of the flip-flop 261. , (G) is a pixel supplement signal 257, (g) is an input clock enable 258 of the enlargement circuit, (g) is the output of the memory circuit 251 (signal D in FIG. 4), and (k) is the output of the flip-flop 270 (FIG. Signals E) and (c) are output 146 (signal F in FIG. 4) of the video signal. First, the internal operation of the enlargement control circuit 255 in FIG. 4 will be described. In the adder 260, the enlargement coefficient 144 and the interpolation coefficient 2
56 is added. In FIG. 5, the addition between (A) and (D) corresponds to this, and is output as (E). Here, the expansion coefficient 144 and the interpolation coefficient 256 are values of 0 or more and less than 1. In the output of the adder 260, the most significant bit becomes carry and becomes the pixel supplement signal 257, and the other bits become the input of the flip-flop 261.
In the example of FIG. 5, when the output of the adder 260 shown in (e) is 1/5, 2/5, 3/5, 4/5 and 0 or more and less than 1, the value as it is is It becomes the input of the flip-flop 261 shown in (f), and the pixel supplement signal 257 shown in (g) becomes 0. On the other hand, the adder 2 shown in FIG.
If the output of 60 becomes 5/5 and a value of 1 or more, the most significant bit is deleted, that is, 0/5 obtained by subtracting 1 is (f).
Becomes the input of the flip-flop 261 shown in FIG.
The pixel replenishment signal 257 indicated by becomes 1. The flip-flop 261 delays one pixel by using the output clock enable 142 and outputs the result as an interpolation coefficient 256. By this operation, the interpolation coefficient 256 is changed as shown in FIG.
As shown in the above, the value increases in steps of the enlargement coefficient 144 for each output pixel in the range of 0 or more and less than 1. The memory circuit 251 stores the vertically enlarged / reduced video signal 141 and outputs it in synchronization with the output clock enable 142. Here, when the pixel supplement signal 257 shown in FIG. 5G is input from the enlargement control circuit 255, FIG.
The same data is output from the memory circuit 251 as shown in FIG. Further, the AND circuit 253 ANDs the output clock enable 142 shown in FIG. 5C and the inversion of the pixel supplement signal 257 shown in FIG. Fig. 5
The input clock enable 258 of the magnifying circuit shown in FIG.
Is obtained. The flip-flop 270 uses the input clock enable 258 of the enlargement circuit, delays the output of the memory circuit 251 shown in FIG. 5K by one pixel, and outputs the result as shown in FIG. Interpolation circuit 252
Performs an operation of F = (1−β) D + βE, and this becomes the output video signal 146 shown in FIG. By operating as described above, four pixels a, b, c, and d are used to obtain a, 1 / 5a + 4, as shown in FIG.
/ 5b, 2 / 5b + 3 / 5c, 3 / 5e + 2 / 5d, 4
Generate five pixels of / 5d + ／ e (4 / 5d +
The pixel of e is used in the calculation of 1 / 5e.
Does not count because it works similarly to a in generating the next five pixels). That is, this means that the enlargement operation of 5/4 has been performed.

In the examples of FIGS. 3 and 5, there has been described an example in which the reduction coefficient 104 and the expansion coefficient 144 do not change, that is, the horizontal expansion / contraction magnification is constant. 6 and 7, the reduction coefficient generation circuit 105 shown in FIG.
A method of changing and using the reduction coefficient 104 and the expansion coefficient 144 in the expansion coefficient generation circuit 145 will be described. FIG. 6 shows an example of the relationship between the reduction coefficient selector 121, the reduction coefficient 104, and the reduction ratio with respect to the horizontal position 112 of the input video signal. FIG. 6A shows the relationship between the horizontal position 112 of the video signal and the reduction coefficient selector 121. In this example, the coefficient addition stop position 113 and the coefficient addition restart position 114 are determined in advance (coefficient addition stop position 113 <the coefficient addition restart position 114), and the values and the horizontal position 1 of the video signal are determined.
12, the reduction coefficient selector 121 is selected. The reduction coefficient selector 121 determines that the horizontal position 112 of the input video signal is the coefficient addition stop position 11 as shown in FIG.
In the area smaller than 3, the input A and the coefficient addition restart position 11
Input B is selected in an area larger than 4, and input C is selected in other areas. Note that A, B, and C in FIG.
Are the inputs A of the reduction coefficient selector 121 in FIG.
It is the same as B and C, and means an input reduction coefficient. FIG. 6B shows the relationship between the horizontal position 112 of the input video signal and the reduction coefficient 104. For the reduction coefficient 104, an initial value 111 is set at the left end of the screen. Thereafter, in an area where the input A is selected in the reduction coefficient selector 121, the value increases by the gradient 115 of the reduction coefficient. In the region where the input C is selected, the constant value k is obtained, and in the region where the input B is selected, the value decreases by the slope 115 of the reduction coefficient. FIG. 6 (c)
Shows the relationship of the reduction ratio (= 1 / (1 + reduction coefficient)) with respect to the horizontal position 112 of the input video signal. When the reduction coefficient changes as shown in FIG.
As shown in FIG. 6C, the reduction ratio is small at both ends, increases as the position approaches the center, and becomes constant at a value of 1 / (1 + k). Such an operation is hereinafter referred to as reduced side stretching.

FIG. 7 shows a horizontal position 152 of the output video signal.
, The expansion coefficient selector 161, the expansion coefficient 144,
And an example of the relationship between the magnification and the magnification. FIG. 7A shows the horizontal position 152 of the output video signal and the enlargement coefficient selector 161.
Shows the relationship. In this example, the coefficient addition stop position 153 and the coefficient addition restart position 154 are determined in advance (coefficient addition stop position 153 <the coefficient addition restart position 154), and the expansion coefficient selector is determined based on the relationship between the values and the horizontal position 152 of the output video signal. 161 is selected. Enlargement coefficient selector 161
Is the horizontal position 152 of the output video signal as shown in FIG.
Is selected in a region smaller than the coefficient addition stop position 153, an input B is selected in a region larger than the coefficient addition restart position 154, and an input C is selected in other regions. FIG.
A, B, and C in (a) are the same as the inputs A and B of the expansion coefficient selector 161 in FIG. 1, and indicate the input expansion coefficients. FIG. 7B shows the relationship between the horizontal position 152 of the output video signal and the enlargement factor 144. As the enlargement factor 144, an initial value 151 is set at the left end of the screen. Thereafter, in a region where the input A is selected in the enlargement coefficient selector 161, the slope of the enlargement coefficient decreases by 155. In the region where the input C is selected, the constant value k is obtained.
Increase by one. FIG. 7C illustrates an enlargement magnification (= 1 / (1−enlargement coefficient)) with respect to the horizontal position 152 of the output video signal.
This shows the relationship. When the enlargement factor 144 changes as shown in FIG. 7B, the enlargement factor is large at both ends, as shown in FIG. 7C, and decreases as the distance from the center increases. It is constant at a value of (1-k). Such an operation is hereinafter referred to as an enlarged side stretch to distinguish it from a reduced side stretch. So far, the general operation of reduction and enlargement has been described. Hereinafter, effects obtained by combining the reduction side stretch and the enlargement side stretch will be described.

FIG. 8 shows that the circuit shown in FIG.
A video signal with an image size of 80 and an aspect ratio of 4: 3 is converted into a video signal with an image size of 720 × 480 and an aspect ratio of 1
The example of the side stretching operation when displaying on the monitor of 6: 9 is shown. Here, the setting on the reduction side is the initial value 1 of the reduction coefficient.
11 is 0, the coefficient addition stop position 113 is 228, the coefficient addition restart position 114 is 492, and the slope 115 of the reduction coefficient is 9 /
As 8192, reduction side stretching is performed. Further, the setting of the enlargement side is performed by setting the initial value 151 of the enlargement coefficient to 1229/256,
Coefficient addition stop position 153 is 200, coefficient addition restart position 1
54 is 520, and the expansion factor slope 155 is 41/1638.
As 4, enlarge the side stretch.

FIG. 9 shows the relationship between the reduction coefficient selector 121, the expansion coefficient selector 161, and the enlargement / reduction ratio with respect to the horizontal position 152 of the output video signal when the operation shown in FIG. 8 is realized. FIGS. 9A and 9B show an input signal selected by the reduction coefficient selector 121 and an input signal selected by the expansion coefficient selector 161 at the horizontal position 152 of the output video signal. FIG. 9C shows the relationship between the horizontal position 152 of the output video signal and the final enlargement / reduction ratio including reduction and enlargement. The switching positions of the input of the expansion coefficient selector 161 are 200 and 520, which are the values of the coefficient addition stop position 153 and the coefficient addition restart position 154. On the other hand, the reduction coefficient selector 12
Since the input switching position of 1 indicates the position after the enlargement and reduction, the coefficient addition stop position 11
3. 228, 492, which is the value of the coefficient addition restart position 114
And different.

Here, the method according to the first embodiment of the present invention will be compared with the method using the conventional technique. First, the relationship between the output horizontal position and the enlargement / reduction ratio is almost the same in both FIG. 9 and FIG. Next, consider the enlargement / reduction operation at the left end of the screen. As shown in FIG. 17, in the related art, after performing a reduction of 0.8 times, an enlargement of 2.5 times is performed, thereby finally obtaining a magnification of 2.0 times. On the other hand, in the first embodiment of the present invention, the initial value of the reduction coefficient is set to 0 at the time of reduction, so that the reduction is performed at 1 time at the left end of the screen, and the expansion is performed at 2.0 times at the time of expansion. . This means that the use of the present method has prevented a reduction in the amount of information of an image due to unnecessary reduction. This effect is the same for the right part of the screen.
This means that the horizontal size after reduction is smaller than that of the prior art as shown in FIG.
As shown in FIG.
In FIG. 8 showing the operation according to the embodiment of FIG.
It is clear from the fact that it has only decreased to zero. Therefore, when performing the side stretching operation as shown in FIGS. 9 and 17, if the reduced side stretching is performed as in the first embodiment of the present invention, a decrease in the amount of information can be suppressed and a clearer image can be obtained. be able to.

Next, a second embodiment will be described. The configuration of the circuit according to the present embodiment is exactly the same as that of the first embodiment, except that the set values by the registers are different.
In the first embodiment shown in FIG.
Is larger than the input switching position of
The setting is such that the switching position of the input 1 is outside the screen. On the other hand, in the second embodiment, the setting is made such that the switching position of the input of the enlargement coefficient selector 161 is inside the screen. FIG. 10 shows the relationship between the reduction coefficient selector 121, the enlargement coefficient selector 161, and the enlargement / reduction ratio with respect to the horizontal position 152 of the output video signal in the second embodiment. FIGS. 10A and 10B show an input signal selected by the reduction coefficient selector 121 and an input signal selected by the expansion coefficient selector 161 at the horizontal position 152 of the output video signal. FIG. 10C shows the relationship between the horizontal position 152 of the output video signal and the final enlargement / reduction ratio including reduction and enlargement. Here, the reduction side setting is such that the initial value 111 of the reduction coefficient is 0, the coefficient addition stop position 113 is 125, and the coefficient addition restart position 114
Is set to 595 and the slope 115 of the reduction coefficient is set to 33/16384 to perform the reduced side stretch. The setting of the enlargement side is set to 1229/256 for the initial value 151 of the enlargement coefficient, 240 for the coefficient addition stop position 153, and 48 for the coefficient addition restart position 154.
0, enlargement side stretching is performed with the inclination 155 of the enlargement coefficient set to 545/262144. Note that, in the first embodiment, the horizontal size after the reduced side stretch is shown in FIG.
Is 620 as shown in FIG.
Becomes The effect of using the second embodiment is that, similarly to the first embodiment, a decrease in the amount of information can be suppressed and a clearer image can be obtained as compared with the conventional technique. First
Similarly to the embodiment, in this example, the left and right edges of the screen are not reduced to 0.8 times and then enlarged to 2.5 times, but are reduced to 1 times and then to 2.times. Perform 0x magnification. By not performing this useless reduction, it is possible to suppress a decrease in the information amount of the image. In this example, the horizontal size after reduction is 600. Since this value is larger than the value of 576 obtained by the conventional technique, it can be confirmed that a decrease in the amount of information was able to be suppressed.

Next, a third embodiment of the present invention will be described. FIG. 11 is a diagram showing a third embodiment of the present invention.
This example is a circuit in which the degree of freedom of setting is increased by making the slope 155 of the expansion coefficient variable in the expansion coefficient generation method of FIG. Here, 300 is the slope 155 of the magnification factor.
, 301 is an external / internal coefficient switching position (a value indicating a horizontal position when changing from an external coefficient to an internal coefficient), and 302 is an internal / external coefficient switching position (a value indicating a horizontal position when changing from an internal coefficient to an external coefficient) , 303 are outer coefficients (= incline coefficient 1)
Reference numeral 304 denotes an inner coefficient (= slope 15 of the expansion coefficient).
5), 310 is a flip-flop, 311 is a coefficient selector, 312, 313, 314, 315 are adders,
320, 321, 322, 323 are comparators, 324, 3
Reference numerals 25, 326, and 327 are selectors, and reference numeral 350 is a circuit for generating a gradient of an expansion coefficient. Here, 300 to 304 are fixed values set by registers.

FIG. 12 shows the operation of the main part of the circuit shown in FIG. 11. Specifically, the enlargement coefficient selector 161, the coefficient selector 311, the inclination 155 of the enlargement coefficient, and the horizontal position 152 of the output video signal are shown. Magnification factor 14
4 and an example of the relationship between the enlargement magnification. This corresponds to (a), (b), (c), (d),
(E). In this example, in addition to the coefficient addition stop position 153 and the coefficient addition restart position 154, an outside / inside coefficient switching position 301 and an inside / outside coefficient switching position 302 are determined in advance. Here, the external / internal coefficient switching position 301 is set from the left end of the screen to the coefficient addition stop position 153, and the internal / external coefficient switching position 302 is set to be between the coefficient addition restart position 154 and the right end of the screen.

Here, the operation of each part in FIG. 11 will be described. The flip-flop 310 outputs the horizontal synchronization signal 15
When 0 is input, the initial value 300 of the gradient of the enlargement factor is read and output as the gradient 155 of the enlargement factor. In other cases, the flip-flop 310 delays the output from the coefficient selector 311 by one pixel and outputs the result as the gradient 155 of the expansion coefficient. The adder 312 performs addition between the slope 155 of the expansion coefficient one pixel before and the outer coefficient 303, and outputs the result to the input A of the coefficient selector 311. The adder 313 subtracts the inner coefficient 304 from the gradient 155 of the expansion coefficient one pixel before, and outputs the result to the input B of the coefficient selector 311. Similarly, the adder 314 subtracts the outer coefficient 303 from the slope 155 of the enlargement coefficient one pixel before and outputs the result to the input C of the coefficient selector 311. The addition is performed with the coefficient 304, and the result is output to the input D of the coefficient selector 311.

Next, the operation in the coefficient selector 311 will be described. When the horizontal position 152 of the output video signal is smaller than the external / internal coefficient switching horizontal position 301, the selector 324 outputs the output of the adder 312, that is, the input A of the coefficient selector 311, and otherwise outputs the output of the selector 325. select. In the selector 325, when the horizontal position 152 of the output video signal is smaller than the coefficient addition stop position 153, the output of the adder 313, that is, the coefficient selector 3
Eleven inputs B, otherwise the output of selector 326 is selected. In the selector 326, the output of the adder 314, that is, the input C of the coefficient selector 311 is used when the horizontal position 152 of the output video signal is larger than the internal / external coefficient switching horizontal position 302;
5 output is selected. In the selector 327, when the horizontal position 152 of the output video signal is larger than the coefficient addition restart position 154, the output of the adder 315, that is, the input D of the coefficient selector 311 is used. Slope 155, ie, input of coefficient selector 311
Select E. That is, as shown in FIG. 12B, the coefficient selector 311, as shown in FIG.
2, the input A is selected in an area smaller than the external / internal coefficient switching position 301, and the input B is selected in an area larger than the external / internal coefficient switching position 301 and smaller than the coefficient addition stop position 153. In a region where the horizontal position 152 of the output video signal is larger than the inner / outer coefficient switching position 302, the input C,
Input D is selected in a region smaller than the inside / outside coefficient switching position 302 and larger than the coefficient addition restart position 154. Otherwise, that is, the horizontal position 152 of the output video signal
From the coefficient addition stop position 153 to the coefficient addition restart position 15
If it is in the area between 4, the input E is selected. FIG.
FIG. 2C shows the relationship between the horizontal position 152 of the output video signal and the slope 155 of the expansion coefficient. Magnification factor slope 15
In the area 5, the initial value 300 is read at the left end of the screen, and in the area where the input of the coefficient selector 311 is A, the outer coefficient 303 is increased by one for each output pixel. Also, the coefficient selector 31
In the region where the input of 1 is B, the inner coefficient 3
It decreases by 04, and becomes constant in a region where the input of the coefficient selector 311 is E. In this example, in a region where the slope 155 of the expansion coefficient is constant, the slope 15
Each parameter is set so that 5 becomes 0. Further, in a region where the input of the coefficient selector 311 is D, the gradient 155 of the expansion coefficient
In the region where the input of the coefficient selector 311 is C, the outer coefficient 303 decreases by one for each output pixel. The enlargement coefficient slope generation circuit 350 includes an enlargement coefficient generation circuit 145.
Then, the slope 155 of the expansion coefficient is output. The expansion coefficient generation circuit 145 performs the same operation as the circuit in FIG. As the inclination 155 of the enlargement coefficient changes as shown in FIG. 12C, the enlargement coefficient 144 output from the enlargement coefficient generation circuit 145 is different from the horizontal position 152 of the output video signal in FIG.
It changes as shown in FIG. By definition, the magnification can be expressed as 1 / (1−magnification coefficient). Therefore, the relationship between the magnification and the horizontal position 152 of the output video signal is as shown in FIG.

Hereinafter, the difference between the first and second embodiments and the third embodiment will be described with reference to FIGS. 7 and 12. FIG. FIG.
Shows the relationship between the horizontal position 152 of the output video signal and the enlargement magnification, the enlargement coefficient 144, and the like in the first and second embodiments. Here, FIG. 7A shows FIG. 12A, and FIG.
12B corresponds to FIG. 12D, and FIG. 7C corresponds to FIG. 12E. In the first and second embodiments,
The slope 155 of the expansion coefficient is the horizontal position 152 of the output video signal.
It is constant regardless of. Therefore, although not shown in FIG. 7, the diagram corresponding to FIG. 12C is a horizontal straight line at a certain value. In FIG. 7 (c), the relationship between the horizontal position 152 of the output video signal and the enlargement ratio is such that the increase ratio of the enlargement ratio increases toward the left and right edges of the screen.
In FIG. 12 (e), the rate of increase of the magnification ratio, that is, the slope, is substantially constant. This has the effect of preventing an extremely large magnification at the left and right ends of the screen, which has been a problem. In FIG. 7C, the coefficient addition stop position 15
3. At the coefficient addition restart position 154, the gradient of the enlargement magnification changed rapidly. On the other hand, in FIG. 12 (e), the change is smooth even at the coefficient addition stop / restart position. By using the third embodiment of the present invention, it is possible to realize a more natural enlarged side stretch. Become.

Next, a fourth embodiment of the present invention will be described. FIG. 13 is a diagram showing a fourth embodiment of the present invention. In the fourth embodiment, the degree of freedom in setting the reduced side stretch is increased by applying the enlargement coefficient slope generation circuit 350 shown in FIG. 13 to a reduction circuit. Here, 400 is the initial value of the gradient 115 of the reduction coefficient, 401 is the external / internal coefficient switching position (a value indicating the horizontal position when changing from the external coefficient to the internal coefficient), and 402 is the internal / external coefficient switching position (the internal coefficient to the external coefficient) 403 is the outer coefficient)
(= Slope of the slope 115 of the reduction coefficient), 404 is the inner coefficient (=
410 is a flip-flop, 411 is a coefficient selector, 412, 413, 41
4, 415 are adders, 420, 421, 422, 423
Is a comparator, 424, 425, 426, and 427 are selectors, and 450 is a reduction coefficient gradient generation circuit. Here, 400 to 404 are fixed values set by registers.

FIG. 14 shows the operation of the main part in the circuit of FIG. 13. More specifically, the reduction coefficient selector 121, the coefficient selector 411, the reduction coefficient slope 115, the reduction coefficient with respect to the horizontal position 112 of the input video signal. Coefficient 104,
4 shows an example of the relationship between the reduction ratio and the reduction ratio. This is
In FIG. 14, (a), (b), (c), (d),
(E). In this example, in addition to the coefficient addition stop position 113 and the coefficient addition restart position 114, an outer / inner coefficient switching position 401 and an inner / outer coefficient switching position 402 are determined in advance. Here, the external / internal coefficient switching position 401 is set to be between the coefficient addition stop position 113 from the left end of the screen, and the internal / external coefficient switching position 402 is set to be between the coefficient addition restart position 114 and the right end of the screen. The operation in the reduction coefficient gradient generation circuit 450 is the same as the operation in the expansion coefficient gradient generation circuit 350 in FIG. Therefore, as shown in FIG. 14C, the slope 1 of the reduction coefficient with respect to the horizontal position 112 of the input video signal.
The relationship of 15 is also the same as the relationship of the slope 155 of the expansion coefficient with respect to the horizontal position 152 of the output video signal shown in FIG. FIG. 14D shows the relationship between the horizontal position 112 of the input video signal and the reduction coefficient 104. Here, the initial value 111 of the reduction coefficient is set to 0. The reduction ratio can be expressed as 1 / (1 + reduction coefficient) by definition. Therefore, the relationship of the reduction ratio with respect to the horizontal position 112 of the input video signal is as shown in FIG. The effect of the fourth embodiment is that the change of the reduction ratio is prevented from becoming extremely steep at the left and right end portions of the screen, and the coefficient addition stop position 113 and the coefficient addition restart position 1
14, the change in the reduction ratio becomes smooth. This is shown in FIG. 5 (c) showing the reduction ratio with respect to the horizontal position 112 of the input video signal in the first embodiment.
And the horizontal position 11 of the input video signal in the fourth embodiment.
This is apparent from a comparison with FIG. Therefore, by using the fourth embodiment of the present invention, it is possible to realize a more natural reduced side stretch.

Next, as a fifth embodiment, an example will be described in which the video signal scaling circuit described in the above four embodiments is applied to a television receiver. FIG. 17 is a block diagram showing the configuration of the fifth embodiment. Here, 501 is a terrestrial antenna, 502 is a BS antenna, and 503 is a cable T
V cable, 504 is a composite output external device, 5
05 is a BS digital antenna, 506 is a component output external device, 511, 512, 513 are analog tuners, 514 is a digital tuner, 521 is a selector, 522 is a decoder, 523 is a selector, 524 is a video signal enlargement / reduction circuit, and 525 is A display control unit 526 is a display unit, and 527 is a television receiver. The analog tuners 511, 512, and 513 are respectively connected to the terrestrial antenna 5
01, BS antenna 502, cable TV cable 5
The analog RF signal input from the input unit 03 is converted into a composite video signal and output to the selector 521. In the selector 521, the analog tuners 511, 512, 5,
The video signal to be used is selected from the composite video signal output from the external video device 13 and the composite video signal input from the composite output external device 504. Decoder 52
2 converts the composite video signal selected by the selector 521 into a baseband component video signal,
Output to selector 523. In addition, digital tuner 5
In 14, the digital broadcast signal from the BS digital antenna 505 or the like is converted into a component video signal and output to the selector 523. The selector 523 includes the decoder 52
2. The component to be used is selected from the component video signals output from the digital tuner 514 and the component output external device 506 and output to the video signal enlargement / reduction circuit 524. The video signal scaling circuit 524 performs the scaling operation of the baseband video signal output from the selector 523 using the means described in the first, second, third, and fourth embodiments. Display unit 52 such as a cathode ray tube and a liquid crystal screen
At 6, the video signal output from the video signal scaling circuit 524 is displayed. At that time, the control is performed by the display control unit 525. As an effect of the fifth embodiment, a television receiver 5 which mainly inputs a signal having an aspect ratio of 4: 3 and outputs the signal to a display section 526 having an aspect ratio of 16: 9.
When configuring the television receiver 27, it is possible to configure the television receiver 527 that performs the side stretching operation while suppressing the deterioration of the image quality as compared with the conventional example.

[0026]

According to the present invention, the image size is the same,
When performing enlargement / reduction operations in which enlarged and reduced parts coexist, such as side stretch between formats with different aspect ratios, obtain a clear output image with little deterioration in image quality by suppressing unnecessary loss of image information. Can be. In addition, by increasing the degree of freedom in setting the enlargement / reduction ratio, a more natural side stretch image can be obtained.

[Brief description of the drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration example of a video signal horizontal reduction circuit;

FIG. 3 is a time chart of a video signal horizontal reduction circuit.

FIG. 4 is a diagram illustrating a configuration example of a video signal horizontal enlargement circuit;

FIG. 5 is a time chart of the video signal horizontal expansion circuit.

FIG. 6 is a diagram illustrating an example of a change in a reduction ratio with respect to a horizontal position of an input video signal.

FIG. 7 is a diagram illustrating an example of a change in an enlargement magnification with respect to a horizontal position of an output video signal.

FIG. 8 is a diagram showing an outline of a horizontal reduction / enlargement operation according to the first embodiment of the present invention.

FIG. 9 is a diagram illustrating a relationship between a horizontal position and a scaling factor in a horizontal scaling operation in the first embodiment.

FIG. 10 is a diagram illustrating a relationship between a horizontal position and a scaling factor in a horizontal scaling operation according to the second embodiment of the present invention.

FIG. 11 is a view showing a third embodiment of the present invention.

FIG. 12 is a diagram illustrating an example of a change in an enlargement magnification with respect to a horizontal position of an output video signal in the third embodiment.

FIG. 13 is a diagram showing a fourth embodiment of the present invention.

FIG. 14 is a diagram illustrating an example of a change in a reduction ratio with respect to a horizontal position of an input video signal in a fourth embodiment.

FIG. 15 is a diagram showing a fifth embodiment of the present invention.

FIG. 16 is a diagram showing a conventional example.

FIG. 17 is a diagram illustrating a relationship between a horizontal position of an output video signal and a scaling factor according to the related art.

FIG. 18 is a diagram showing an outline of a conventional side stretching operation.

[Explanation of symbols]

101: input video signal, 102: input clock enable, 103: video signal horizontal reduction circuit, 104: reduction coefficient, 105: reduction coefficient generation circuit, 106: horizontal reduced video signal, 107: clock enable of horizontal reduced video signal, 110 ... horizontal synchronization signal, 112 ... horizontal position of input video signal, 114 ... coefficient addition restart position, 1
15: slope of reduction coefficient, 120, 160: flip-flop, 121: reduction coefficient selector, 122, 12
3 ... adder, 124, 125 ... comparator, 126,1
27: selector, 130: video signal vertical scaling circuit, 141: vertical scaling video signal, 143: video signal horizontal scaling circuit, 144: scaling factor, 145, scaling factor generating circuit, 146: output video signal, 152 ...
Horizontal position of output video signal, 161... Enlargement coefficient selector.

Continuing from the front page (72) Inventor Koichi Ono 6-16-16 Shinmachi, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (72) Inventor Kenichi Iwata 3-16-6 Shinmachi, Ome-shi, Tokyo Hitachi, Ltd. Device Development Center Co., Ltd. (72) Inventor Yoshiaki Kuroda 3-16, Shinmachi, Ome-shi, Tokyo 3 Stocks, Hitachi Co., Ltd. Device Development Center F-term (reference) 5C025 BA02 CA06 5C068 HB06 HB22 LA11 5C082 AA02 BA41 CA33 CA34 CA38 CA40 CA81 MM10

Claims (7)

[Claims] A video signal enlarging / reducing circuit for enlarging or reducing a video signal, wherein a magnification factor decreases, is constant or increases with a change in a horizontal position of the video signal, and a reduction factor increases, is constant or decreases. Expansion coefficient / reduction coefficient generation means for achieving a state of a combination of
Video horizontal reduction means for performing a reduction of (1 + reduction coefficient), and video horizontal expansion means for performing an expansion of a signal obtained by performing a horizontal reduction by using a expansion coefficient at a magnification ratio of 1 / (1-enlargement coefficient) And a video signal scaling circuit, comprising: 2. A video signal enlarging / reducing circuit for enlarging or reducing an image signal, comprising: a first state in which an expansion coefficient decreases and a reduction coefficient increases with a change in the horizontal position according to a range of a horizontal position of the image signal. A second state in which the enlargement coefficient is constant and the reduction coefficient increases, a third state in which the enlargement coefficient and the reduction coefficient are constant, a fourth state in which the enlargement coefficient is constant and the reduction coefficient decreases, Enlargement coefficient / reduction coefficient generating means for providing a fifth state in which the reduction coefficient increases and the reduction coefficient decreases; and a reduction magnification of 1 for the input video signal using the reduction coefficient.
/ (1 + reduction coefficient) video horizontal reduction means for reducing the image, and using the expansion coefficient, the image horizontal for performing the expansion of 1 / (1−enlargement coefficient) on the horizontal reduced signal. A video signal enlargement / reduction circuit, comprising: enlargement means. 3. A video signal enlarging / reducing circuit for enlarging or reducing an image signal, wherein a first state in which an expansion coefficient decreases and a reduction coefficient increases with a change in the horizontal position according to a range of the horizontal position of the image signal. A second state in which the enlargement coefficient is reduced and the reduction coefficient is constant, a third state in which the enlargement coefficient and the reduction coefficient are constant, a fourth state in which the enlargement coefficient is increased and the reduction coefficient is constant, Enlargement coefficient / reduction coefficient generating means for providing a fifth state in which the reduction coefficient increases and the reduction coefficient decreases; and a reduction magnification of 1 for the input video signal using the reduction coefficient.
/ (1 + reduction coefficient) video horizontal reduction means for reducing the image, and using the expansion coefficient, the image horizontal for performing the expansion of 1 / (1−enlargement coefficient) on the horizontal reduced signal. A video signal enlargement / reduction circuit, comprising: enlargement means. 4. The video signal enlargement / reduction circuit according to claim 2, wherein the horizontal area of the video signal is divided into five areas, a right end area on the display screen is a first area, and Area as a third area, a left end area as a fifth area, an area between the first area and the third area as a second area, and the third area and the fifth area as the fifth area. A region between the regions is defined as a fourth region, and the enlargement coefficient / reduction coefficient generation means performs the first state in the first region, the second state in the second region, and the third region. The third state in the area, the fourth state in the fourth area,
A video signal enlargement / reduction circuit, wherein an enlargement coefficient and a reduction coefficient are generated so that the fifth area is in the fifth state. 5. A video signal enlarging / reducing circuit for enlarging or reducing a video signal, means for increasing or decreasing a predetermined coefficient in accordance with a change in the horizontal position of the video signal, each time the horizontal position of the video signal changes by one pixel A magnification factor generating means for increasing or decreasing the magnification coefficient by the predetermined coefficient, and a video horizontal magnification means for performing magnification of the input video signal with a magnification factor of 1 / (1-magnification factor). A video signal scaling circuit. 6. A video signal enlarging / reducing circuit for enlarging or reducing a video signal, means for increasing or decreasing a predetermined coefficient in accordance with a change in the horizontal position of the video signal, wherein the horizontal position of the video signal changes by one pixel. Reduction factor generation means for increasing or decreasing the reduction coefficient by the predetermined coefficient every time, and video horizontal reduction means for reducing the input video signal by a reduction factor of 1 / (1 + reduction coefficient). A video signal scaling circuit. 7. A television receiver comprising the video signal enlargement / reduction circuit according to claim 1 and capable of enlarging or reducing the video signal.