JP2002076606A - Electronic equipment and semiconductor device - Google Patents

Electronic equipment and semiconductor device

Info

Publication number
JP2002076606A
JP2002076606A JP2001053475A JP2001053475A JP2002076606A JP 2002076606 A JP2002076606 A JP 2002076606A JP 2001053475 A JP2001053475 A JP 2001053475A JP 2001053475 A JP2001053475 A JP 2001053475A JP 2002076606 A JP2002076606 A JP 2002076606A
Authority
JP
Japan
Prior art keywords
solder
mass
impact
chip
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001053475A
Other languages
Japanese (ja)
Inventor
Tasao Soga
太佐男 曽我
Hideyoshi Shimokawa
英恵 下川
Tetsuya Nakatsuka
哲也 中塚
Masato Nakamura
真人 中村
Yuji Fujita
祐治 藤田
Toshiharu Ishida
寿治 石田
Masahide Okamoto
正英 岡本
Koji Serizawa
弘二 芹沢
Toshihiro Hachiya
登志広 八矢
Hideki Mukuno
秀樹 椋野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2001053475A priority Critical patent/JP2002076606A/en
Publication of JP2002076606A publication Critical patent/JP2002076606A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
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    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01019Potassium [K]
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01049Indium [In]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/0132Binary Alloys
    • H01L2924/01322Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/10251Elemental semiconductors, i.e. Group IV
    • H01L2924/10253Silicon [Si]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To improve a drop resistance or impact resistance of an electronic equipment and to improve reliability of a solder connection of a semiconductor device in which an Si chip or the like being weak against a thermal impact in association with a large deformation is die-bonded or a power module in which a large stress is operated. SOLUTION: An electronic equipment comprises a circuit board, an electronic component electrically connected to an electrode of the board. In this case, the electrode of the board is solder connected to the electrode of the component by using a lead-free solder containing Cu of O to 2.0 mass%;, In of 0.1 to 10 mass%; and Sn of the residue.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、電子部品を実装し
た電子機器(特に衝撃強度を求めるモバイル製品)や、
耐熱衝撃性が要求されるCSPパッケージ、半導体モジ
ュールであるMCM(マルチチッフ゜モシ゛ュール)、Siチップ等をダ
イボンドした半導体装置、大面積のパワーモジュールの
接続等に適用する技術に関するものである。
The present invention relates to an electronic device (particularly a mobile product for which impact strength is required) on which electronic components are mounted,
The present invention relates to a technology applied to connection of a CSP package requiring thermal shock resistance, a semiconductor module MCM (multi-chip module), a semiconductor device die-bonded with a Si chip or the like, a large-area power module, and the like.

【0002】[0002]

【従来の技術】現在、環境問題からはんだのPbフリー化
が進行している。接続用のはんだは電子機器を問わず、
従来のSn-Pb共晶系から、継手の高信頼性が期待できるS
n-Ag-Cu系、例えばSn-(2.0〜4.0)Ag-(0.5〜1.5)Cuの高
温系はんだに移行する世界的な潮流がある。このSn-Ag-
Cu系はんだは従来の万能型のSn-Pb共晶系はんだと比
べ、金属の本質的な差から、特に機械的強度特性の異な
りにより、製品用途もしくは使途によってはその接続信
頼性が劣る場合があり注意が必要である。
2. Description of the Related Art Currently, Pb-free solder is being promoted due to environmental problems. Regarding the solder for connection, regardless of the electronic device,
High reliability of joints can be expected from conventional Sn-Pb eutectic S
There is a worldwide trend to move to high-temperature solders of n-Ag-Cu system, for example, Sn- (2.0-4.0) Ag- (0.5-1.5) Cu. This Sn-Ag-
Compared to conventional all-purpose Sn-Pb eutectic solder, Cu-based solder may have lower connection reliability depending on the product application or usage due to the inherent difference in metal, especially due to the difference in mechanical strength characteristics. There is a need to be careful.

【0003】[0003]

【発明が解決しようとする課題】Sn-Ag-Cu系はんだは一
般にSn-Pb共晶に比べ、はんだ自体の強度が強く、剛性
は高く、かつ現状のメタライズに対し接合界面強度も高
く、部品、基板等が強ければ、従来のSn-Pbはんだの実
装品と比べ同等以上の信頼性を確保できる。
SUMMARY OF THE INVENTION Sn-Ag-Cu-based solder generally has higher strength, higher rigidity, and higher joint interface strength than the current metallization, as compared to Sn-Pb eutectic. If the substrate and the like are strong, reliability equal to or higher than that of a conventional Sn-Pb solder mounted product can be secured.

【0004】しかしながら、その反面、部品、基板等が
弱いと、はんだ自体は破壊しないため、接合界面に応力
的なしわ寄せがきて、部品等を破壊する恐れがある。そ
の大きな原因は機械的性質として、特に強度が強い特性
を持つためである。例えば、電子部品を実装した電子機
器(特に携帯電話等の移動型のモバイル製品)に於いて
は、その継手強度等の信頼性は高いが、従来のSn-Pb共
晶と比較した場合、これまでの経験的事実から落下時の
衝撃、熱衝撃等に弱いことが指摘されている。
[0004] On the other hand, if the components, the substrate, and the like are weak, the solder itself will not be destroyed. The major reason is that it has a particularly strong strength as a mechanical property. For example, the reliability of the joint strength etc. is high in electronic devices mounted with electronic components (especially mobile products such as mobile phones), but when compared with the conventional Sn-Pb eutectic, It has been pointed out from the empirical facts up to that it is vulnerable to impact at the time of falling, thermal shock, and the like.

【0005】そこで、本発明は、電子機器における耐落
下もしくは耐衝撃性を向上させることを目的とする。
Accordingly, an object of the present invention is to improve the drop resistance or impact resistance of an electronic device.

【0006】さらには、大変形を伴う熱衝撃が作用する
Siチップ等をダイボンドした半導体装置、BGA、CS
P、WPP、フリップチップ等のバンプ実装、大きな応
力が作用するパワーモジュール等におけるはんだ接続の
信頼性を向上させることを目的とする。
Further, thermal shock accompanied by large deformation acts.
Semiconductor devices with die-bonded Si chips, BGA, CS
It is an object of the present invention to improve the reliability of solder connection in bump mounting of P, WPP, flip chip or the like, or in a power module on which a large stress acts.

【0007】[0007]

【課題を解決するための手段】本発明は、上記目的を達
成するために、特許請求の範囲の通りに構成したもので
ある。
SUMMARY OF THE INVENTION In order to achieve the above-mentioned object, the present invention is constituted as described in the appended claims.

【0008】より具体的には、継手の温度サイクル等の
信頼性を損ねないで、はんだに衝撃的な強い力が作用し
た場合、Sn-Ag-Cu系はんだよりも、変形し易く、伸びに
優れる材料とすることにより、部品の接合界面での応力
的負担をなくし、耐落下、衝撃性を向上させ、かつ大変
形に対して熱衝撃緩和作用を向上させることとした。即
ち、接続部に用いるSnベースのPbフリーはんだとして、
応力が小さく、変形し易い材料とするために、Snもしく
はSn-Cuのマトリクスの中にSnより軟らかいInを固溶さ
せることにより、落下した場合の接合界面にかかる衝撃
を緩和して耐落下、耐衝撃性を向上させることとした。
More specifically, when a strong impact is applied to the solder without impairing the reliability such as the temperature cycle of the joint, the solder is more easily deformed and stretched than the Sn-Ag-Cu solder. By using an excellent material, it is possible to eliminate the stress load at the joint interface of the parts, to improve the drop resistance and impact resistance, and to improve the thermal shock mitigation action against large deformation. In other words, as Sn-based Pb-free solder used for the connection part,
In order to make the material small in stress and easily deformable, In which is softer than Sn in the matrix of Sn or Sn-Cu is dissolved to reduce the impact applied to the joint interface when it falls, The impact resistance has been improved.

【0009】これにより、落下時の衝撃のエネルギーを
はんだ自体が塑性変形することで、接合界面にかかる応
力を低減するので、接合界面には大きな衝撃力が作用せ
ず、耐衝撃性を向上させることが可能となる。
As a result, since the solder itself is plastically deformed by the impact energy at the time of dropping, the stress applied to the joint interface is reduced, so that a large impact force does not act on the joint interface and the impact resistance is improved. It becomes possible.

【0010】また、大変形を伴うはんだ付け時および熱
衝撃加速試験等におけるSiチップ等をダイボンドした半
導体装置、BGA、CSP、WPP(Wafer Process Pac
kage)、フリップチップ実装におけるはんだバンプ接
続、及び大きな応力が作用する大面積のパワーモジュー
ルにおける接続等においても、上記のような強度が小さ
く変形し易い材料とすることにより、界面での応力集中
による破壊を防止し、接続信頼性を向上させることが可
能となる。
In addition, semiconductor devices, such as BGA, CSP and WPP (Wafer Process Pac), which are die-bonded with a Si chip or the like at the time of soldering accompanied by large deformation and in a thermal shock acceleration test, etc.
Kage), solder bump connection in flip chip mounting, and connection in large area power module where large stress acts, etc. Destruction can be prevented and connection reliability can be improved.

【0011】[0011]

【発明の実施の形態】まず、携帯電話などの電子機器を
落下させた場合の衝撃について示す。
DESCRIPTION OF THE PREFERRED EMBODIMENTS First, an impact when an electronic device such as a mobile phone is dropped will be described.

【0012】携帯電話などの電子機器のケースの中には
基板上に部品、LSI(BGA,CSP,TSOP,TQ
FP等のパッケージ)が搭載されている。通常の落下で
は破壊することは少ないが、誤って高いところで落下さ
せたり、落下場所、当たりどころが悪いと耐えられず継
手の接合界面等で破壊する場合が予想される。部品、L
SI自体の重量は軽いので、加速度が増しても耐えられ
ないものではない。問題はケース、基板を介して伝わっ
てくる衝撃力及び衝撃による基板の曲げ変形である。衝
撃力を緩和するものとして、ケース、基板による減衰性
が重要であることは言うまでもない。瞬時の衝撃に対し
て、ケースは曲がりにくいが、ダンパーの役割、機能を
持たすことは可能である。衝撃力はケースを介して基板
に伝わり、基板からはんだ継手に負荷がかかる。基板は
比較的大きく、長手方向には曲がり易く、従って、1/
2波長の基本振動モード等に大きな曲げによる衝撃力が
加わる。このとき、基板周辺を拘束された状態で自由振
動を起こし、減衰していく。基板を伝わる高周波の縦波
と変形による低周波の横波が発生する。縦波は高周波の
弾性波であり、継手にシリーズでストレートに伝わる動
きであるが、本来はケース、基板のサポート部でバンパ
ー的な機能を持たして衝撃緩和が可能である。それで
も、吸収しきれない力が継手にかかる。基板拘束部にダ
ンパーがないとストレートにそこから基板を通して継手
に伝わることになる。他方、基板の変形による横振動は
基板の拘束状態で異なるが、瞬時に大変形し、大きな曲
げ応力を起こし基板の反り等により界面を破壊させる原
因となる。
In the case of an electronic device such as a mobile phone, parts, LSI (BGA, CSP, TSOP, TQ)
Package such as an FP). Although it is unlikely to be broken by a normal drop, it is expected that it will be dropped accidentally at a high place, or that it will not be able to endure if it is dropped at a bad place or a hit point, and will be broken at the joint interface of the joint. Parts, L
Since the SI itself is light in weight, it is not unbearable even if the acceleration increases. The problem is the bending force of the substrate due to the impact force transmitted through the case and the substrate and the impact. It goes without saying that damping by the case and the substrate is important to reduce the impact force. Although the case is hard to bend against an instantaneous impact, it can have a role and function of a damper. The impact force is transmitted to the board via the case, and a load is applied from the board to the solder joint. The substrate is relatively large and easy to bend in the longitudinal direction, so
An impact force due to large bending is applied to a fundamental vibration mode of two wavelengths and the like. At this time, free vibration is generated in a state where the periphery of the substrate is restrained, and the vibration is attenuated. A high-frequency longitudinal wave transmitted through the substrate and a low-frequency transverse wave due to deformation are generated. Longitudinal waves are high-frequency elastic waves, which are motions that are transmitted straight to the joint in series, but originally have a bumper-like function at the support portion of the case and the substrate, and can alleviate the impact. Still, forces that cannot be absorbed are applied to the joint. If there is no damper in the board restraint, it will be transmitted straight from there to the joint through the board. On the other hand, the lateral vibration caused by the deformation of the substrate varies depending on the restrained state of the substrate, but it is instantaneously greatly deformed, causing a large bending stress and causing the interface to be broken due to the warpage of the substrate.

【0013】図1は携帯電話などの電子機器を落下させ
た時にケースの端部4が地面5に当たり、ケースからの
衝撃がコネクター等の拘束部9を介して、基板6に伝達
されたときの基板の固有振動によりLSIパッケージ7
等の継手8に及ぼす衝撃モデル(a)を示した。1自由度
系の減衰のある振動モードで表現すると、図1(b)のよ
うな衝撃の伝達モデルが考えられる。衝撃伝達は地面、
ケース、拘束部、基板、継手、LSIパッケージにシリ
ーズに縦振動、横振動となって伝達される。減衰は地面
とケースの衝突による損失、ケースの材料減衰による損
失、拘束部の材料減衰による損失、拘束部とケースおよ
び基板間の摩擦による損失、基板の材料減衰による損
失、更に、はんだの材料減衰、はんだの変形による損
失、LSIパッケージの材料減衰等が主にシリーズにつ
ながった減衰と仮定できる。地面からLSIパッケージ
までの伝達系を考えると、減衰系としてははんだを含む
材料減衰と摩擦を含む構造減衰系に分けることができ
る。振動伝達系は地面、ケース、拘束部、基板、継手、
LSIパッケージからの伝達により横振動で伝わる場
合、一般に変形し易いモードとして、基板の長手方向に
1/2波長で、中央部が腹となる固有振動モードが考え
られる。このとき、はんだ継手は瞬時に大きな曲げ応力
が作用し、剛性の強いはんだでは、はんだで変形を吸収
できないため、接合界面に大きな力が作用し、耐えられ
ない場合に破壊を起こす。この時にはんだが柔らかい
と、はんだが塑性変形を起こすことにより接合界面にか
かる力を緩和してくれる。なお、携帯電話等に使用され
るLSI等の部品は、一般に小型・軽量のため、衝突に
よるそれ自体の重量からくる衝撃力は小さいと考えられ
る。
FIG. 1 shows a case where the end 4 of the case hits the ground 5 when an electronic device such as a mobile phone is dropped, and the impact from the case is transmitted to the substrate 6 via the restraining portion 9 such as a connector. LSI package 7 due to natural vibration of substrate
The impact model (a) exerted on the joint 8 is shown. When represented by a vibration mode with damping in a one-degree-of-freedom system, a shock transmission model as shown in FIG. Shock transmission on the ground,
The series, longitudinal vibration and lateral vibration are transmitted to the case, restraining part, board, joint, and LSI package in series. Damping is the loss due to the collision between the ground and the case, the loss due to the material damping of the case, the loss due to the material damping of the restraint, the loss due to the friction between the restraint, the case and the board, the loss due to the material damping of the board, and the damping of the solder It can be assumed that the loss due to the deformation of the solder, the material attenuation of the LSI package, and the like are mainly attenuations connected to the series. Considering the transmission system from the ground to the LSI package, the damping system can be divided into a material damping system including solder and a structural damping system including friction. Vibration transmission system is ground, case, restraint, board, joint,
In the case where the vibration is transmitted by the lateral vibration due to the transmission from the LSI package, a natural vibration mode in which the center is an antinode at a half wavelength in the longitudinal direction of the substrate is generally considered as a mode easily deformed. At this time, a large bending stress acts instantaneously on the solder joint, and with a solder having a high rigidity, the deformation cannot be absorbed by the solder. At this time, if the solder is soft, the solder undergoes plastic deformation, thereby reducing the force applied to the joint interface. Note that components such as an LSI used for a mobile phone or the like are generally small and lightweight, and therefore it is considered that an impact force due to a weight of the component itself due to a collision is small.

【0014】そこで、我々は、はんだ付け温度を下げら
れて、かつ、はんだ自体が変形しやすく、そして温度サ
イクル等で高信頼性を確保するために、変形を阻止して
いるSn晶内の改質のため、マトリクス中に固溶し易く、
かつ固溶しても硬くなりにくく、高信頼性を確保できる
Inを添加することについて検討した。
[0014] In view of this, we have reduced the soldering temperature, and the solder itself is liable to be deformed. In order to ensure high reliability by temperature cycling, etc., we have to modify the Sn crystal to prevent deformation. Because of the quality, it is easy to dissolve in the matrix,
And hard to harden even in solid solution, ensuring high reliability
The addition of In was studied.

【0015】特に、Snのマトリクス(結晶)自体が変形性
に富むことが重要であることから、柔らかく伸びに優れ
るSn-Cu共晶系はんだをベースとしてInを添加すること
について検討した。
In particular, since it is important that the Sn matrix (crystal) itself is rich in deformability, it was examined to add In based on a Sn--Cu eutectic solder which is soft and excellent in elongation.

【0016】図2はSn-0.7CuにInを添加した場合の伸び
1、引張強さ2を示す。なお、横軸は対数(Log)を用い
ている。
FIG. 2 shows elongation 1 and tensile strength 2 when In is added to Sn-0.7Cu. The horizontal axis uses logarithm (Log).

【0017】図より、Sn-0.7Cuに約0.2〜7.0mass%のIn
を添加しただけで、その伸びは改善されることが理解で
きる。特に約0.5〜2.0mass%のInの添加においてはSn-0.
7Cuよりも約10%以上の改善が実現できることが理解
できる。一般に結晶粒に金属を微量添加すると、強度は
向上し伸びは低下する。しかし、ここはInがSnより柔ら
かいことから、強度向上もなく伸びも優れる特性を有す
る。強度が低下し、伸びが増せば、界面にかかる応力は
低下するので、耐衝撃性が改善され、強い衝撃を受けた
時に、はんだが変形することで衝撃エネルギーを吸収で
きる。
According to the figure, about 0.2-7.0 mass% of In
It can be understood that the elongation is improved only by adding. In particular, when adding about 0.5 to 2.0 mass% of In, Sn-0.
It can be understood that about 10% or more improvement can be realized compared to 7Cu. Generally, when a small amount of metal is added to crystal grains, the strength increases and the elongation decreases. However, here, since In is softer than Sn, it has a characteristic that strength is not improved and elongation is excellent. When the strength is reduced and the elongation is increased, the stress applied to the interface is reduced, so that the impact resistance is improved, and the impact energy can be absorbed by the deformation of the solder when subjected to a strong impact.

【0018】引張強さはInを約2mass%の添加までは強度
は余り変わらないが、約5mass%以上添加すると、融点は
下がるが、引張強度は大幅に上昇する。引張強度が上昇
すると、強い衝撃が作用したとき変形し難いはんだとな
り耐衝撃性が劣ることとなってしまう。従って、引張強
度の観点からすると、Inは約5mass%以上添加しない方が
好ましいことが理解できる。
The tensile strength does not change much until In is added at about 2 mass%, but when about 5 mass% or more is added, the melting point is lowered, but the tensile strength is greatly increased. When the tensile strength is increased, the solder is hardly deformed when a strong impact is applied, resulting in poor impact resistance. Therefore, from the viewpoint of tensile strength, it is understood that it is preferable not to add In of about 5 mass% or more.

【0019】また、ベースのはんだとして用いたSn-Cu
共晶系は、Sn-Ag-Cu共晶系に比べて融点が約10℃高く、
面実装としては注目されていない状況にあったが、前述
のようにInを入れることにより、融点は下がりSn-Ag-Cu
共晶系並みのはんだ付け温度で接続が可能になると言っ
たメリットもある。ベースとなるSn-Cuの組成として、S
n-0.7Cu共晶にInを入れるので、In量にもよるが、Cuは
共晶より少な目の0.1〜0.7mass%位が望ましい。Inが多
めの場合はCuは少な目が望ましい。一般には、メタライ
ズがCuの場合などはくわれ防止を考慮すると、多めに入
れることが望ましい場合があるので、0〜2.0mass%の範
囲で有効である。
The Sn-Cu used as the base solder
The eutectic has a melting point about 10 ° C higher than the Sn-Ag-Cu eutectic,
Although the situation was not attracting attention as surface mounting, the melting point was lowered by adding In as described above, and Sn-Ag-Cu
There is also an advantage that connection can be performed at a soldering temperature similar to that of a eutectic system. The composition of the base Sn-Cu is S
Since In is added to the n-0.7Cu eutectic, although it depends on the amount of In, Cu is desirably 0.1 to 0.7 mass%, which is smaller than that of the eutectic. If In is large, Cu should be small. In general, when the metallization is made of Cu, etc., it may be desirable to add a large amount in consideration of the prevention of cracking, so that it is effective in the range of 0 to 2.0 mass%.

【0020】表1にSn-Cu-In系の融点(液相線、固相
線)と硬さを示す。昇温速度は2℃/minである。硬さ測
定時の荷重は100gである。これらは、Sn-Cu共晶系にIn
を添加することで、はんだ付け温度を下げ、更に強度を
下げ、伸びを低下させない接続構造となるものである
が、いずれの場合。InがはいってもSnのマトリクスに柔
らかいInが固溶するので、硬さも殆ど変わらない。
Table 1 shows the melting point (liquidus line, solidus line) and hardness of the Sn-Cu-In system. The heating rate is 2 ° C./min. The load at the time of hardness measurement is 100 g. These are added to the Sn-Cu eutectic
Is added to lower the soldering temperature, further reduce the strength, and provide a connection structure that does not lower the elongation. Even though In enters, the hardness hardly changes because soft In forms a solid solution in the Sn matrix.

【0021】[0021]

【表1】 以上のように、柔らかく伸びに優れるSn-Cu共晶系をベ
ースに、このSnマトリクス中に入って硬くさせず、かつ
伸び(変形性)を維持し、はんだ自体がSnより柔らかいIn
を添加することで、界面における応力集中を避けてSn系
でも電子部品の耐衝撃性、耐熱衝撃性を向上させること
ができる。すなわち、Inの添加により、引張強さは余り
変わらず、伸びは増すので、衝撃が加わった場合、はん
だ自体で変形することにより、衝撃エネルギーは吸収さ
れ、接合界面では大きな力が作用しないので、BGA、
CSP、WPP、フリップチップ等のはんだバンプ接続
において、従来の界面での破壊を抑制することが可能と
なる。この現象は単に耐衝撃性だけでなく、温度サイク
ルにおける耐熱衝撃性にも同様な効果がある。
[Table 1] As described above, based on the Sn-Cu eutectic system which is soft and excellent in elongation, it does not harden in this Sn matrix and maintains elongation (deformability), and the solder itself is softer than Sn.
By adding, it is possible to avoid the stress concentration at the interface and improve the impact resistance and thermal shock resistance of the electronic component even in a Sn-based electronic component. In other words, the tensile strength does not change much and the elongation increases with the addition of In, so when an impact is applied, the impact energy is absorbed by the deformation of the solder itself, so that a large force does not act at the joint interface, BGA,
In connection with a solder bump such as a CSP, a WPP, or a flip chip, it is possible to suppress the destruction at the conventional interface. This phenomenon has a similar effect not only on the impact resistance but also on the thermal shock resistance in a temperature cycle.

【0022】ところで、これまでSn-Cu系共晶はんだを
ベースにして説明をしてきたが、Sn-Cu系共晶はんだ自
体が伸びに優れた材料である。
By the way, although the description has been made so far based on the Sn-Cu eutectic solder, the Sn-Cu eutectic solder itself is a material excellent in elongation.

【0023】ベースとなるはんだについては、Sn-Cu系
共晶はんだの他に、Sn-Ag系はんだ、Sn-Sb系はんだにつ
いても検討した。しかし、Sn-Ag系をベースにしたので
は針状のAg3Sn化合物がSn中に分散し強化され、あるい
はSn粒界部にAg3Snがネットワーク状に形成されるの
で、強度が強くなり、衝撃時、熱衝撃時に接合界面に応
力がストレートに伝わるので、弱い部品の界面では破壊
が起こり易くなる。
As for the solder to be used as a base, in addition to the Sn-Cu eutectic solder, Sn-Ag solder and Sn-Sb solder were also examined. However, based on the Sn-Ag system, the needle-like Ag3Sn compound is dispersed and strengthened in Sn, or since Ag3Sn is formed in a network at the Sn grain boundary, the strength becomes strong, Since the stress is transmitted straight to the bonding interface at the time of thermal shock, destruction is likely to occur at the interface of a weak component.

【0024】Sn-Sb系はSbがSn中に固溶するが、固溶し
て強化されるので、Sn-Ag系と同様に硬く強くなり、変
形性に劣るので適さないことからSn-Cu系はんだをベー
スとすることとした。
In the Sn-Sb system, Sb forms a solid solution in Sn, but since it is dissolved and strengthened, it becomes hard and strong similarly to the Sn-Ag system, and has poor deformability. We decided to use a base solder.

【0025】また、Sn-Ag-Cu系はんだについても検討し
た。図3はSn-0.7Cu共晶(228℃)にAgを添加した場合の
伸び1、引張強さ2の関係を示す。
Further, Sn-Ag-Cu based solder was also studied. FIG. 3 shows the relationship between elongation 1 and tensile strength 2 when Ag is added to Sn-0.7Cu eutectic (228 ° C.).

【0026】図からAgは少ないほど伸びは増し、逆に引
張強さは低くなることが理解できる。即ち、Sn-0.7Cuの
伸びが最大で、引張強さは最小になることから、Agの添
加による変形性の改善、はんだの接続部品への応力的負
担を軽減する改善は期待できないことが理解できる。
From the figure, it can be understood that the smaller the amount of Ag, the higher the elongation and the lower the tensile strength. In other words, since the elongation of Sn-0.7Cu is the maximum and the tensile strength is the minimum, it is understood that the improvement of the deformability by the addition of Ag and the improvement of reducing the stress on the connection parts of the solder cannot be expected. it can.

【0027】また、この結果からも、Snマトリクス中に
針状のAg3Sn の分散が少ない程、伸びに優れ、強度が下
がることが推定でき、すなわちAgが無いほど優れた耐衝
撃性は向上することが推定できる。従って、Sn-Ag-Cu系
はんだに限らず、Sn-Ag系はんだであってもAg3Snの同一
作用が考えられるので、十分な衝撃力緩和作用は得られ
ないことが推定できる。
From this result, it can be inferred that the smaller the dispersion of acicular Ag3Sn in the Sn matrix, the better the elongation and the lower the strength. In other words, the better the impact resistance is improved without Ag. Can be estimated. Therefore, not only Sn-Ag-Cu solder, but also Sn-Ag solder can have the same effect of Ag3Sn, so it can be presumed that sufficient impact force relaxation action cannot be obtained.

【0028】一方、Sn-0.7Cu共晶はんだはSnマトリクス
中にCu6Sn5が分散している状態であるが、Sn-3.5Ag共晶
はんだと比べると分散量も少なく、かつCu6Sn5がAg3Sn
程には針状晶ではない。従って、Sn-0.7Cu共晶はんだに
おいては、その粒内変形に対してCu6Sn5が悪影響は及ぼ
すものではない。
On the other hand, the Sn-0.7Cu eutectic solder has a state in which Cu6Sn5 is dispersed in the Sn matrix, but the dispersion amount is smaller than that of the Sn-3.5Ag eutectic solder, and Cu6Sn5 is Ag3Sn3.
Not as acicular. Therefore, in the Sn-0.7Cu eutectic solder, Cu6Sn5 does not adversely affect the intragranular deformation.

【0029】例えば、Sn-3Ag-0.7CuとSn-0.7Cuの2つの
スルーホール継手の温度サイクル試験では、Sn-3Ag-0.7
Cu はんだのデンドライト(樹枝状晶)は直線的に成長す
る傾向を示し、温度サイクル試験後の応力がかかる位置
での塑性変形は外観上観察しにくく、直線的なクラック
が観察される。Sn-0.7Cuはんだのデンドライトの成長は
余り直線的ではなく、温度サイクル試験後の応力がかか
る位置で外観上明確に塑性変形を示す。
For example, in a temperature cycle test of two through-hole joints of Sn-3Ag-0.7Cu and Sn-0.7Cu, Sn-3Ag-0.7Cu
Dendrites (dendrites) of Cu solder show a tendency to grow linearly, and plastic deformation at the position where stress is applied after a temperature cycle test is hardly observed in appearance, and linear cracks are observed. The dendrite growth of the Sn-0.7Cu solder is not very linear, and the plastic deformation is apparently apparent at the position where the stress is applied after the temperature cycle test.

【0030】以上のことから、Sn-Cu系はんだは、Sn-Ag
系はんだやSn-Ag-Cu系はんだよりも継手の状態で、熱衝
撃に優れることが分かり、Sn-Cu系はんだをベースはん
だとして選定した。
From the above, Sn-Cu based solder is Sn-Ag
It was found that the joint was better in thermal shock in the joint state than the system solder or the Sn-Ag-Cu solder, and the Sn-Cu solder was selected as the base solder.

【0031】図4は落下衝撃により、LSIパッケージに
張り付けた加速度センサーにより、継手から伝わる衝撃
力の経時変化を示す。高周波10は縦弾性波を示す。図
4(a)は縦軸に衝撃力をとり、横軸に時間をとり、時間
とともに減衰していく状況を示したものである。このと
き、横振動も時間のズレはあっても最大になることが考
えられる。はんだは(1)従来のSn-Pb共晶はんだ、(2)従
来のSn-3.5Ag-0.7Cuはんだ、(3)Sn-0.5Cu-3Inはんだの
減衰曲線を示す。このとき、継手に入る衝撃入力は同一
とした。大きな衝撃力の時、従来のSn-Pb共晶はんだ
は、はんだ自体が変形し易い(Sn、Pbが微細粒であるた
め、表面積が大で、粒界滑りによる変形で容易に動き易
い)ので、継手のはんだの変形により衝撃エネルギーを
はんだが吸収するため、減衰性が顕著になる。但し、温
度依存、ひずみ速度依存性が大であるが、室温における
衝撃では良い性質がでていると思われる。他方、(2)Sn-
Ag-Cu系の代表であるSn-3.5Ag-0.7Cuはんだは強度は大
で、変形し難いため、接合界面に衝撃力をストレートに
伝えることになり、接合界面が弱い場合、界面で破壊を
起こすことになる。
FIG. 4 shows the change over time of the impact force transmitted from the joint by the acceleration sensor attached to the LSI package due to the drop impact. The high frequency 10 indicates a longitudinal elastic wave. FIG. 4 (a) shows a situation where the vertical axis indicates the impact force, the horizontal axis indicates the time, and the time decreases with time. At this time, it is conceivable that the lateral vibration also becomes maximum even if there is a time lag. The solder shows the decay curves of (1) conventional Sn-Pb eutectic solder, (2) conventional Sn-3.5Ag-0.7Cu solder, and (3) Sn-0.5Cu-3In solder. At this time, the shock input entering the joint was the same. At the time of a large impact force, the conventional Sn-Pb eutectic solder is easy to deform itself (Sn and Pb are fine particles, so the surface area is large and it is easy to move due to deformation due to grain boundary sliding) The shock energy is absorbed by the solder due to the deformation of the solder of the joint, so that the damping property becomes remarkable. However, although the temperature dependency and the strain rate dependency are large, it is considered that good properties are obtained by impact at room temperature. On the other hand, (2) Sn-
Sn-3.5Ag-0.7Cu solder, which is a representative of the Ag-Cu series, has high strength and is difficult to deform, so it transfers the impact force straight to the joint interface.If the joint interface is weak, it will break at the interface. Will wake up.

【0032】衝撃シャルピ試験によると、Sn-Ag系(Sn-4
Ag)はSn-Pb共晶(Sn-40Pb)よりも衝撃試験による吸収エ
ネルギーが高いことが知られている(例えば、「表面実
装形LSIパッケージの実装技術とその信頼性向上」、応
用技術出版(株)、p368、1988-11-16発行)。これによ
ると、室温での衝撃強さはSn-40Pb:24(ft-lb)、Sn-4Ag:
38(ft-lb)、Pb-10Sn:8(ft-lb)である。また、Sn-AgにBi
を添加すると吸収エネルギーが低下することも知られて
いる(例えば、第12回環境対応実装技術フォーラム、p4-
1、2000-11-28)。Biが入ると脆くなるので、衝撃値が下
がるのは当然の結果と予想される。他方、柔らかい高Pb
はんだ(Pb-10Sn)の衝撃値が更に低いことも理解でき
る。
According to the impact Charpy test, the Sn-Ag type (Sn-4
Ag) is known to have higher absorbed energy in impact tests than Sn-Pb eutectic (Sn-40Pb) (e.g., `` Mounting technology for surface-mount LSI packages and improving their reliability '', Applied Technology Publishing Co., Ltd., p368, 1988-11-16). According to this, the impact strength at room temperature is Sn-40Pb: 24 (ft-lb), Sn-4Ag:
38 (ft-lb) and Pb-10Sn: 8 (ft-lb). Bi is added to Sn-Ag.
It is also known that the absorption energy decreases with the addition of (e.g., the 12th Environmentally Friendly Mounting Technology Forum, p4-
1, 2000-11-28). Since Bi becomes brittle, the impact value is expected to decrease as a natural result. On the other hand, soft high Pb
It can be understood that the impact value of the solder (Pb-10Sn) is even lower.

【0033】衝撃時のひずみ速度は当然ながら高く、Sn
-Pb共晶系はひずみ速度依存性、温度依存性が顕著であ
る欠点をもっている。現状のSn-Pb共晶はんだを用いた
携帯電話等の落下で、問題が起きていない事実を考慮す
ると、室温の条件での落下に対しては、この欠点が現れ
ないことを意味していると考える。この点では、高Pb系
はんだは温度依存、ひずみ依存が少なく、かつ安定して
いる優れものである。高Sn系はんだは、低温下(-55℃)
で急激に衝撃値が下がるが、これは脆くなることに起因
する。しかし、伸びと強度は確保しているので通常で問
題になることはない。これらのデータから、以下に現象
との関係を考察する。これまでも、Sn-Ag-Cu系はんだの
場合、温度サイクルで厳しい継手構造の場合、はんだ自
体は変形し難いため、部品によっては接合界面が破壊す
る確率が高くなる場合がある。落下時の衝撃も、それに
近い挙動と思われる。はんだが柔らかければ(応力が小
さくて、伸びに優れれば)、はんだが変形してくれて、
接合界面には大きな応力が作用しない。本来、はんだの
機能はここにある。Sn-Pb共晶はこのような優れた機能
を有している。高Pbはんだ(Sn-10Pb)も同様に柔らか
く、同様な機能を有している。高Pbはんだのメカニズム
は素地が柔らかいPbにSnが固溶した組織であり、Sn-Pb
共晶(微細結晶の集まり)とは金属組織的な違いはある
が、接合界面に応力がかからない点で同じ効果がある。
The strain rate at impact is naturally high,
The -Pb eutectic has the drawback that the strain rate dependency and the temperature dependency are remarkable. Considering the fact that there is no problem with falling of mobile phones etc. using the current Sn-Pb eutectic solder, it means that this defect does not appear for drops at room temperature conditions Think. In this respect, the high Pb-based solder is excellent because it is less dependent on temperature and strain and is stable. High Sn based solder is used at low temperature (-55 ℃)
, The impact value drops sharply, but this is due to the brittleness. However, since elongation and strength are secured, there is usually no problem. From these data, the relationship with the phenomenon will be discussed below. Until now, in the case of Sn-Ag-Cu solder, in the case of a joint structure that is severe in temperature cycling, the solder itself is unlikely to be deformed, so that the bonding interface may be more likely to be broken depending on the component. The impact at the time of the fall seems to be similar behavior. If the solder is soft (small stress and excellent elongation), the solder will be deformed,
No large stress acts on the bonding interface. Originally, the function of solder is here. Sn-Pb eutectic has such an excellent function. High Pb solder (Sn-10Pb) is similarly soft and has a similar function. The mechanism of high Pb solder is a structure in which Sn is dissolved in Pb, whose base material is soft, and Sn-Pb
Although there is a difference in metallographic structure from eutectic (a collection of fine crystals), the same effect is obtained in that no stress is applied to the joint interface.

【0034】シャルピ試験による衝撃値の高いSn-Ag-Cu
系はんだ継手が、落下の衝撃等に対して好ましくない理
由は、強度が強いことにある。この原因は図3からも想
像できるように、Sn晶の中に針状のAg3Snが分散するこ
とによる強化複合材になっていることに起因すると考え
られる。このことは、Ag含有量を少なくする程、強度が
下がり、伸びが増してくる望ましい状況になることから
推測できる。なお、Sn-0.75Cu共晶(Sn晶の中にCu6Sn5が
分散した状態)は、Sn晶の中のCu量は少なく、Ag3Snのよ
うな針状晶にはならず、融点を232℃から227℃に下げら
れる。そこで、更に衝撃緩和性能アップのため、はんだ
の強度を下げて、伸びを増して、変形し易くする必要が
ある。このためには、Sn晶の中に固溶し易く、Snより柔
らかいInを含ませることが有効となる。これによって、
融点も下げることができる。
Sn-Ag-Cu with high impact value by Charpy test
The reason why the system solder joint is not preferable against a drop impact or the like is that the strength is high. As can be imagined from FIG. 3, it is considered that this is due to the fact that the needle-like Ag3Sn is dispersed in the Sn crystal to form a reinforced composite material. This can be inferred from the fact that the lower the Ag content, the more desirable the situation is that the strength decreases and the elongation increases. In addition, Sn-0.75Cu eutectic (in a state in which Cu6Sn5 is dispersed in Sn crystal) has a small amount of Cu in Sn crystal, does not become acicular crystal like Ag3Sn, and has a melting point of 232 ° C to 227 ° C. ℃. Therefore, in order to further improve the impact relaxation performance, it is necessary to reduce the strength of the solder, increase the elongation, and easily deform. To this end, it is effective to include In, which is easily dissolved in Sn crystals and is softer than Sn. by this,
The melting point can also be lowered.

【0035】本案の代表組成の一例である(3)Sn-0.5Cu-
3Inはんだは、Sn-Pb共晶までは衝撃エネルギーを吸収し
てくれないが、Snマトリクス中のIn添加による変形効果
により、良好な衝撃緩和特性を示す。この変形特性はSn
素地の柔らかさに基づく粒内変形に起因する。Inは多く
するほど融点が下がり、かつ、強度の絶対値が上がらな
い限り、衝撃力緩和の効果は有る。これらのことから
も、Sn-Cu-In系はんだを用いることにより部品継手の耐
衝撃性、耐熱衝撃性が改善されていることが理解でき
る。
(3) Sn-0.5Cu- is an example of a typical composition of the present invention.
The 3In solder does not absorb impact energy up to the Sn-Pb eutectic, but exhibits good impact relaxation characteristics due to the deformation effect due to the addition of In in the Sn matrix. This deformation characteristic is Sn
This is due to intragranular deformation based on the softness of the substrate. As long as In is increased, the melting point decreases and the effect of reducing the impact force is provided as long as the absolute value of the strength does not increase. From these facts, it can be understood that the impact resistance and the thermal shock resistance of the component joint are improved by using the Sn-Cu-In solder.

【0036】次に、Siチップ等をダイボンドした半導体
装置や、大きな応力が作用する大面積のパワーモジュー
ルにおける接続に適用してその接続信頼性を向上させた
例について説明する。
Next, a description will be given of an example in which the present invention is applied to connection in a semiconductor device in which a Si chip or the like is die-bonded or in a large-area power module on which a large stress acts to improve the connection reliability.

【0037】図5(a)はSiチップ11裏面にメタライズを
施し、Ni/AuめっきしたFe-Ni合金(ベース)12にダイボン
ドしたLSI樹脂パッケージ13構造の断面モデルを示す。
チップ上の端子からボンデイングワイヤ14を介してリー
ド15に電気的に接続されている。はんだ16付けは約150
μm厚のはんだ箔を用いて、窒素もしくは水素雰囲気で
フラックスレスで行った。後工程で洗浄が可能であれ
ば、はんだペーストの使用も可能である。この場合は大
気中でのリフロー接続が可能である。Siチップとベース
間の熱膨張係数の差が大きい場合、あるいは大型のチッ
プを接続する場合、はんだの強度が強く、剛性が高い従
来のSn-Ag-Cu系はんだでは、はんだ付け時、温度サイク
ル試験時に厳しい使い方ではSiチップを割る恐れがあ
る。前述のSn-Cu-In系はんだを使用することにより、比
較的低い応力ではんだが変形してくれるのでSiチップで
の割れを防止できる。特に、高融点のはんだが必要な場
合、Sn-0.1In、Sn-2In、Sn-(0.3〜0.7)Cu-1InもしくはS
n-(0.3〜0.7)Cu-2Inなどが好ましい。
FIG. 5A shows a cross-sectional model of the structure of an LSI resin package 13 in which the back surface of a Si chip 11 is metallized and Ni / Au plating is applied to a Fe-Ni alloy (base) 12 by die bonding.
Terminals on the chip are electrically connected to leads 15 via bonding wires 14. Approx. 150 for soldering 16
Using a solder foil having a thickness of μm, a fluxless process was performed in a nitrogen or hydrogen atmosphere. If cleaning can be performed in a later step, a solder paste can be used. In this case, reflow connection in the atmosphere is possible. When the difference in the coefficient of thermal expansion between the Si chip and the base is large, or when connecting a large chip, the strength of the solder and the rigidity of the conventional Sn-Ag-Cu-based solder, when soldering, temperature cycle Strict use during testing can break the Si chip. By using the above-mentioned Sn-Cu-In solder, the solder is deformed by relatively low stress, so that cracking in the Si chip can be prevented. Especially when high melting point solder is required, Sn-0.1In, Sn-2In, Sn- (0.3-0.7) Cu-1In or S
n- (0.3 to 0.7) Cu-2In or the like is preferable.

【0038】図5(b)はベアチップもしくはCSPもし
くはBGAを基板17に接続した一例を示す。外部接続端
子用はんだはCSP、BGAなどのチップキャリア基板
21にボールで供給する方法、もしくは基板の有する電極
にはんだペーストで供給する方法がある。パッケージ用
はんだ18としては樹脂19で補強するので、変形性は余り
関係しないので、温度階層を重視するならばチップ20と
チップキャリア基板21との間のバンプ接続はSn-5Sbもし
くは導電性樹脂でも良い。すなわち、はんだ22バンプ
の融点よりも高温の接続構造であれば良い。一方、基板
17と接続するところは耐衝撃性を確保する必要性から、
Sn-0.5Cu-3Inはんだ22を使用した。Sn-Cu-In系はんだで
あれば、基板の反りに対し、熱衝撃に対し、あるいは衝
撃に対して、Sn-Ag-Cu系はんだに比べ20%から50%強いこ
とが分かった。また、本例では、チップキャリア基板2
1の端子電極上にSn-Cu-In系はんだボールを供給し、プ
リント基板にペーストで供給されたはんだで実装され
る。この場合もチップキャリア基板上の電極にSn-Cu-In
系はんだを供給することにより応力集中個所で衝撃を吸
収することができる。一般にはバンプのチップキャリア
側がはんだとの熱膨張差がつきやすい材料が使われて、
端子面積も小さい場合が多いので応力集中で破壊する場
合多い。しかし、構造、材料等によっては、プリント基
板側界面が弱い場合があり、その場合はプリント基板側
に予めSn-InもしくはInめっきの表面処理を施すことでI
nによる効果がある。即ち、チップキャリア側のSn-3Ag-
0.5Cuボール、もしくはこれにSn-3Ag-0.5Cuペーストを
介してリフロー接続する場合、均一に混ざったとして
も、Agの濃度は現象し、Inが入ってくるので全体的に柔
らかくなる。プロセスによってはプリント基板側界面近
傍で、よりInに富んだSn-Ag-Cu 系(Ag濃度は0にはでき
ないが減少する)はんだが形成されるので、柔らかく伸
びが増すことから耐衝撃性に優れる効果が期待できる。
FIG. 5B shows an example in which a bare chip, CSP or BGA is connected to the substrate 17. Solder for external connection terminal is chip carrier board such as CSP, BGA
There is a method of supplying the substrate 21 with a ball or a method of supplying the electrode of the substrate with a solder paste. As the package solder 18 is reinforced with resin 19, the deformability is not so important, so if the temperature hierarchy is important, the bump connection between the chip 20 and the chip carrier substrate 21 can be made of Sn-5Sb or conductive resin. good. That is, a connection structure having a temperature higher than the melting point of the solder 22 bumps may be used. Meanwhile, the substrate
Where to connect with 17, from the need to ensure impact resistance,
Sn-0.5Cu-3In solder 22 was used. It was found that the Sn-Cu-In solder is 20% to 50% stronger than the Sn-Ag-Cu solder against the substrate warpage, the thermal shock, or the shock. In this example, the chip carrier substrate 2
A Sn-Cu-In-based solder ball is supplied on the terminal electrode of No. 1 and mounted on a printed circuit board with solder supplied in paste. Also in this case, Sn-Cu-In is applied to the electrodes on the chip carrier substrate.
By supplying the system solder, it is possible to absorb an impact at a stress concentration location. In general, a material is used in which the chip carrier side of the bump tends to have a difference in thermal expansion with solder,
Since the terminal area is often small, it is often broken by stress concentration. However, depending on the structure, material, etc., the interface on the printed circuit board side may be weak. In such a case, the surface of the printed circuit board is preliminarily treated with Sn-In or In plating so that
There is an effect by n. That is, Sn-3Ag- on the chip carrier side
In the case of reflow connection via a 0.5Cu ball or Sn-3Ag-0.5Cu paste, even if mixed uniformly, the concentration of Ag occurs and In enters, so that the whole becomes soft. Depending on the process, a Sn-Ag-Cu-based solder (Ag concentration cannot be reduced to 0, but decreases) is formed near the interface on the printed circuit board side. Excellent effect can be expected.

【0039】図6は大型のパワーモジュールに適用した
例である。Siチップ23は径20mmで、メタライズ24はAl
/Ti/Ni/Auで、応力緩衝材のモリブデン板25にはNiめっ
き26が施され、Al2O3絶縁基板27はW焼結-Niめっき28が
施され、更にCu板29にはNiめっき30が施されている。こ
れらのはんだは約150μm厚のはんだ箔を使用し、窒素も
しくは水素雰囲気でリフローして接続するので、無洗浄
で可能である。洗浄可能ならばはんだペーストで大気リ
フローでの接続も可能である。はんだ31組成としてSn-
0.7Cu-1In、 Sn-0.5Cu-4In、 Sn-1.5Cu-5Inを用いた
が、いずれもSiチップの破壊を防止でき、温度サイクル
試験で-55〜125℃の条件で1000サイクルの高信頼性をク
リアできた。
FIG. 6 shows an example applied to a large power module. The Si chip 23 has a diameter of 20 mm and the metallized 24 is Al
/ Ti / Ni / Au, Ni plating 26 is applied to the molybdenum plate 25 of the stress buffer material, W sintered-Ni plating 28 is applied to the Al2O3 insulating substrate 27, and Ni plating 30 is applied to the Cu plate 29. It has been subjected. These solders use a solder foil having a thickness of about 150 μm and are connected by reflowing in a nitrogen or hydrogen atmosphere, so that they can be performed without cleaning. If cleaning is possible, connection by air reflow with solder paste is also possible. Sn- as solder 31 composition
Although 0.7Cu-1In, Sn-0.5Cu-4In, and Sn-1.5Cu-5In were used, all of them can prevent the destruction of the Si chip and have a high reliability of 1000 cycles in the temperature cycle test at -55 to 125 ° C. I was able to clear the sex.

【0040】なお、Sn-Cu-Inのはんだは厳しい継手のリ
ード部品、チップ及びチップのメタライズ強度等が十分
確保されていないものに対しても、耐熱衝撃の面でも優
れている。リード部品の場合、Fe-Ni系、Cu系リード等
に対し、Sn-(1〜10)BiめっきもしくはSn-(0.2〜2)Cuめ
っきを施したもの、従来のSn-10Pbめっきに対しても、
耐衝撃性、耐熱衝撃性は優れており、継手として高信頼
性を十分確保している。
It should be noted that Sn-Cu-In solder is excellent in terms of thermal shock resistance even for lead components of severe joints, chips and those for which the metallization strength of the chips is not sufficiently ensured. In the case of lead parts, Sn- (1-10) Bi plating or Sn- (0.2-2) Cu plating is applied to Fe-Ni-based, Cu-based leads, etc., compared to conventional Sn-10Pb plating. Also,
It has excellent impact resistance and thermal shock resistance, and ensures high reliability as a joint.

【0041】以上説明したように、面付け実装で弱い部
品を搭載する場合、はんだ付け時に継手部に大きな応力
が作用するが、Sn-Cu-In系はんだを使用することによ
り、破壊強度の小さい弱い部品を破壊させずに、Pbフリ
ーはんだで接合することを可能にした。融点が高いもの
が必要な場合は、Sn-0.7CuもしくはSn-0.7Cu-0.1In、融
点が低いものが必要な場合はSn-0.5Cu-5InもしくはSn-
0.5Cu-7Inなどを用いることにより、広い範囲での使用
が可能である。また、部品の強度をある程度確保してい
る場合は、継手として高強度を確保できるSn-0.8Ag-0.5
Cu-3In等の使用も可能である。
As described above, when mounting a weak component by surface mounting, a large stress acts on the joint portion during soldering. However, the use of Sn-Cu-In solder reduces the breaking strength. We have made it possible to join with Pb-free solder without destroying weak components. If high melting point is required, Sn-0.7Cu or Sn-0.7Cu-0.1In, if low melting point is required, Sn-0.5Cu-5In or Sn-
By using 0.5Cu-7In or the like, it can be used in a wide range. Also, if the strength of parts is secured to some extent, Sn-0.8Ag-0.5 can secure high strength as a joint.
Use of Cu-3In or the like is also possible.

【0042】このようにSnベースのPbフリーはんだで、
変形し易く、伸びに優れる材料とするには、Snのマトリ
クスの中にSnより軟らかいInを固溶させることにより、
落下した場合の衝撃を緩和してくれる作用が期待でき
る。即ち、落下時の衝撃のエネルギーをはんだ自体が塑
性変形することで、継手にかかる応力を自らの変形で吸
収し、接合界面には大きな衝撃力が作用しなく、耐衝撃
性で優れる結果となる。衝突時に変形し難いはんだで
は、衝突時の運動エネルギーが接合界面に直接に作用
し、界面破壊を起こしやすい。
Thus, with Sn-based Pb-free solder,
In order to make the material easily deformable and excellent in elongation, by dissolving In softer than Sn in the Sn matrix,
It can be expected to have the effect of reducing the impact when dropped. That is, the solder itself plastically deforms the energy of the impact at the time of the drop, thereby absorbing the stress applied to the joint by its own deformation, and a large impact force does not act on the joint interface, resulting in excellent impact resistance. . In the case of solder that is not easily deformed at the time of collision, the kinetic energy at the time of collision directly acts on the bonding interface, and the interface is likely to be broken.

【0043】また、破壊し易い部品である大型のSiチッ
プ等のダイボンド、 BGA、CSP、WPP、フリッ
プチップ等のはんだバンプ接続、大きな応力が作用する
大面積のパワーモジュール等においても接続信頼性を向
上させることができる。
The connection reliability is also improved in die bonding of large Si chips, which are easily broken parts, solder bump connection of BGA, CSP, WPP, flip chip, etc., and large area power modules on which large stress acts. Can be improved.

【0044】さらに、Agを成分として含まない場合、Ag
による針状結晶の発生がないので、マイグレーション、
ショートなどの心配が無く、その接続信頼性は高い。従
って、前述の組成を用いれば、モバイル製品の耐落下、
衝撃性の向上だけでなく、BGA、CSP、ベアチップ
等の面実装における耐基板曲げ性、耐プロービング検査
性(反り性)等にも優れることとなる。また、大変形を伴
う熱衝撃に弱いSiチップ等をダイボンドした部品や、大
型チップのパワーモジュール実装においても対応でき
る。また、Sn-CuにInを添加することで、はんだ付け温
度はSn-Ag-Cu並みで可能である。なお、Sn-Cu-In系で強
度の絶対値が要求される場合は、Agを1mass%以下入れ
ることで、伸びの低下をある程度押さえた使い方も可能
である。
Further, when Ag is not contained as a component,
Migration,
There is no need to worry about short circuits and the connection reliability is high. Therefore, if the above composition is used, the drop resistance of the mobile product,
In addition to the improvement of the impact resistance, the substrate bending resistance and the probing inspection resistance (warpage resistance) in the surface mounting of BGA, CSP, bare chip, etc. are also excellent. In addition, it can be applied to a die-bonded component such as a Si chip or the like that is susceptible to thermal shock accompanied by large deformation, and to a power module mounting of a large chip. In addition, by adding In to Sn-Cu, the soldering temperature can be set to the same level as Sn-Ag-Cu. When an absolute value of strength is required in the Sn-Cu-In system, it is possible to use Ag in an amount of 1 mass% or less to suppress a decrease in elongation to some extent.

【0045】更には、Sn-Cu-In系にBiを1mass%以下入れ
ることで、寿命低下を押さえ、かつ、はんだの流動性が
良くなることにより、高密度実装に必要なブリッジ防
止、チップ立ち防止の効果が期待できる。
Furthermore, by adding Bi to the Sn-Cu-In system at 1 mass% or less, the life is suppressed and the flowability of the solder is improved, thereby preventing bridges required for high-density mounting and chip standing. The effect of prevention can be expected.

【0046】図7(a)はワイヤボンドのBGA、CSP
で、Siチップ20下を導電樹脂48で接着したものである。
この場合の端子部はチップ側49も基板側50も表面が酸化
し難い安定なAu、Ni/Au等が望ましく(メタライズレスも
ある)、250℃のリフローに耐えられる接着である。ま
た、このワイヤボンド方式でパワーものに適用する場
合、CuとSnを混ぜた複合はんだ箔を用いて、Cu-Sn金属
間化合物で連結させて、リフローに耐える強度を有する
パッケージとすることも可能である。この組合せとして
可能な化合物構成は、Cu-Sn以外にNi-Sn、Au-Sn、Ag-S
n、Pt-Sn等がある。図7(b)はフリップチップ構造で導
電樹脂47のバンプであり、この場合の端子部はチップ側
も基板側も表面が酸化し難いAu、Ni/Au46等であり、250
℃のリフローに耐えられる接続である。更に機械的強度
確保、寿命向上のためヤング率:5〜1500kgf/mm2、熱膨
張係数:10〜60×10-6/℃の樹脂35を充填する。
FIG. 7A shows BGA and CSP of wire bond.
Thus, the lower portion of the Si chip 20 is bonded with a conductive resin 48.
In this case, the terminal section is preferably made of Au, Ni / Au, or the like that is hardly oxidized on both the chip side 49 and the substrate side 50 (there is also no metallization), and is an adhesive that can withstand reflow at 250 ° C. In addition, when using this wire bond method for power products, it is possible to use a composite solder foil mixed with Cu and Sn and connect it with a Cu-Sn intermetallic compound to make a package that has the strength to withstand reflow It is. Possible compound configurations as this combination include Ni-Sn, Au-Sn, Ag-S
n and Pt-Sn. FIG. 7 (b) shows a bump of a conductive resin 47 having a flip chip structure, and the terminal portion in this case is made of Au, Ni / Au46 or the like whose surface is hardly oxidized on both the chip side and the substrate side.
This connection can withstand reflow at ℃. Further, resin 35 having a Young's modulus of 5 to 1500 kgf / mm 2 and a coefficient of thermal expansion of 10 to 60 × 10 −6 / ° C. is filled in order to secure mechanical strength and improve life.

【0047】なお、中継基板側の端子上にSnめっき等を
施しておき、該端子部を含めチップ接着部全体に先に樹
脂を塗布し、予めAu等のバンプを形成してなる該チップ
をパルスヒータ加熱のキャピラリーに吸着させ、該Auバ
ンプを該中継基板の端子に位置決め後、加圧して該Auバ
ンプがSnめっきに接触させた後、加熱溶融させる構造も
可能である。この場合のチップと中継基板とのギャップ
は50μm以下でも可能であり、比較的高温で作業するリ
ペア可能な熱可塑性樹脂(石英フィラーを入れて低膨張
化が可能)を用いることも可能である。なお、チップ端
子、中継基板の端子構成は上記構成に限定されるもので
はない。
The chip formed by applying Sn plating or the like to the terminals on the relay substrate side, applying a resin first to the entire chip bonding portion including the terminal portions, and forming bumps of Au or the like in advance. A structure in which the Au bump is adsorbed on a capillary heated by a pulse heater, the Au bump is positioned on the terminal of the relay board, and then the Au bump is brought into contact with Sn plating and then heated and melted is also possible. In this case, the gap between the chip and the relay substrate can be 50 μm or less, and a repairable thermoplastic resin (which can be reduced in expansion by inserting a quartz filler) that operates at a relatively high temperature can also be used. Note that the terminal configurations of the chip terminals and the relay board are not limited to the above configurations.

【0048】上記各種BGA,CSPの外部接続電極端
子には、耐衝撃性を緩和させるはんだ組成としてSn-0.3
Cu-3In、Sn-0.7Cu-2In、Sn-0.7Cu-0.2In、Sn-0.7Cu-5In
等を用いる。このようなSn-Cu共晶系にAgが入ると針状
のAg3SnがSnマトリクス中に分散固溶することで、はん
だ自体の強度が強くなり過ぎ、はんだが変形し難い状態
になり、その分、接合界面に大きな応力が作用する。Sn
-Ag-Cu系Pbフリーはんだの課題はまさにここにある。通
常の継手では問題なくても、設計マージンが少ないため
構造によっては弱点が現れる場合がある。この弱点を修
正したのがSn-Cu-In系はんだである。Sn-CuはCu6Sn5の
分散型共晶であるが、Ag3Snのような針状にはならず、
従って、強度は低く、伸びが向上する性質を持つ。即
ち、変形し易く、応力集中は起こりにくい組成である。
Sn-0.75Cu共晶では融点が228℃と高いので、Inを添加す
ることで、融点を下げ、かつ軟らかいInをSnのマトリク
ス中に固溶させて、より変形し易いシステムとした。こ
れより柔軟性を求める耐衝撃性を重要視する場合、部品
の耐熱性をも考慮する場合、接合強度をも考慮する場合
等で組成を多少選択することができる。はんだバンプは
中継基板端子上にボールで供給する場合、印刷で供給す
る場合、電気めっきで供給する場合、浸漬めっきで供給
する場合等がある。
The external connection electrode terminals of the above-mentioned various BGAs and CSPs have a solder composition of Sn-0.3 to reduce the impact resistance.
Cu-3In, Sn-0.7Cu-2In, Sn-0.7Cu-0.2In, Sn-0.7Cu-5In
And so on. When Ag enters such a Sn-Cu eutectic system, the needle-like Ag3Sn disperses and forms a solid solution in the Sn matrix, so that the strength of the solder itself becomes too strong and the solder is hardly deformed. A large stress acts on the joint interface. Sn
This is exactly where the issues of -Ag-Cu based Pb-free soldering are. Even if there is no problem with a normal joint, a weak point may appear depending on the structure due to a small design margin. The Sn-Cu-In based solder has corrected this weakness. Sn-Cu is a dispersed eutectic of Cu6Sn5, but it does not become acicular like Ag3Sn,
Therefore, it has low strength and improved elongation. That is, the composition is easily deformed and hardly causes stress concentration.
Since the melting point of Sn-0.75Cu eutectic is as high as 228 ° C, by adding In, the melting point was lowered and soft In was dissolved in the Sn matrix to make the system more deformable. The composition can be selected to some extent when importance is placed on the impact resistance for which flexibility is required, when the heat resistance of parts is considered, and when the joining strength is also considered. The solder bump may be supplied on the relay board terminal by a ball, supplied by printing, supplied by electroplating, supplied by immersion plating, or the like.

【0049】図8は携帯電話用有機基板54に上記BGA
32、CSP33、TSOP56,チップ部品51、機能素子
(例えば携帯電話等に使用される信号処理用に使われる
高周波用RFモジュール34)等を搭載した例である。リ
フローの最高温度はSn-0.7Cu-5In(融点:222.7〜215.4
℃)の場合、Sn-3Ag-0.5Cu(融点:221〜217℃)並みのmax
235℃で可能である。RFモジュールは、GaAsもしくはS
iチップ及び受動素子のチップ部品を熱伝導性、機械的
特性に優れるAl2O3基板27に搭載したものであり、MC
M(マルチチッフ゜モシ゛ュール)の1種類である。数個の約□2mmチ
ップ20及びチップ部品51は小型であり、これらを実装し
たモジュール基板(この場合はAl2O3基板)寸法も□10mm
レベルであることから、プリント基板に対し、接続の信
頼性を十分確保している。特にワイヤボンドされたチッ
プに関しては、プリント基板のリフロー時に再溶融する
と特性に影響を及ぼす恐れがある。そこで、チップ裏側
はAu電極とし、Al2O3基板27側をNi/Snめっき電極とし
て、タ゛イホ゛ント゛で接合する。このAu-Sn金属間化合物は260
℃のリフローでは溶けない。なお、チップ部品は1005レ
ベルであるため、Sn-3Ag-0.5Cuはんだを用いても、例え
プリント基板のリフロー時に再溶融しても表面張力の作
用で固定され、かつ特性への影響もない。RFモジュー
ルの外部接続端子部36はNi/Auめっきである。TSOP
パッケージ56のリードは42アロイリード55にSn/Biめっ
き(約7μm厚)されている。リフロー接続は始めにSn-0.7
Cu-5In等で軽量パッケージの下面を行い、次に、上面を
同様にSn-0.7Cu-5In等でリフロー接続37する。既に接続
された軽量部品は上面部品リフロー時に、下側になって
いても軽いため落下することはなく、また特性への影響
もない。これらのSn-Cu-In系の組成選択は、前述したよ
うに部品の耐熱性、耐衝撃性、接合強度を考慮して決め
る必要がある。
FIG. 8 shows that the above-mentioned BGA
32, CSP33, TSOP56, chip component 51, functional element
(For example, a high-frequency RF module 34 used for signal processing used in a mobile phone or the like) and the like. The maximum reflow temperature is Sn-0.7Cu-5In (melting point: 222.7-215.4)
° C), the same as Sn-3Ag-0.5Cu (melting point: 221-217 ° C)
Possible at 235 ° C. RF module is GaAs or S
i-chip and passive components are mounted on an Al2O3 substrate 27 with excellent thermal conductivity and mechanical properties.
M (multi-chip module). Several □ 2mm chips 20 and chip parts 51 are small, and the size of the module board (Al2O3 board in this case) on which they are mounted is □ 10mm
Because of this level, the reliability of connection to the printed circuit board is sufficiently ensured. In particular, for a wire-bonded chip, remelting during reflow of the printed circuit board may affect the characteristics. Therefore, the back side of the chip is an Au electrode, and the Al2O3 substrate 27 side is a Ni / Sn plated electrode, which is joined by a diode. This Au-Sn intermetallic compound is 260
Does not melt in reflow at ℃. Since the chip component is at the 1005 level, even if the Sn-3Ag-0.5Cu solder is used, even if it is re-melted at the time of reflow of the printed circuit board, it is fixed by the action of the surface tension and has no effect on the characteristics. The external connection terminals 36 of the RF module are plated with Ni / Au. TSOP
The lead of the package 56 is Sn / Bi plated (about 7 μm thick) on the 42 alloy lead 55. Reflow connection is Sn-0.7 first
The lower surface of the lightweight package is made with Cu-5In or the like, and then the upper surface is similarly reflow-connected 37 with Sn-0.7Cu-5In or the like. The already connected light parts do not fall down during reflow of the upper parts because they are light even if they are on the lower side, and there is no influence on the characteristics. As described above, it is necessary to determine the composition of the Sn-Cu-In-based composition in consideration of the heat resistance, impact resistance, and bonding strength of the component.

【0050】図9はCSPパッケージを代表例にした、
接合前(a)、接合した後の拡大(b)を示す。パッケージ58
の中継基板端子へのはんだ供給はボール、もしくはペー
スト等でCuパッド38上もしくはCu/Ni/Auめっき上にSn-
0.3Cu-5Inはんだ37を供給した。有機基板54(プリント基
板)上の端子38には、予めSn-3Ag-0.5Cuはんだ59を印刷
で供給しておく。そして、このパッケージを他のLSI
パッケージ、部品等と同時にプリント基板上に搭載し
て、基板内温度分布が均一になりやすい強制循環型のエ
アリフロー炉を用い、大気中でmax240℃、1m/minのコ
ンベア速度で行った。接合したバンプのパッケージ側は
混ざってもSn-Cu-Inが主である。
FIG. 9 shows a CSP package as a representative example.
The figures before (a) and after expansion (b) are shown. Package 58
The solder is supplied to the relay board terminals on the Cu pad 38 or Cu / Ni / Au plating with a ball or paste.
0.3Cu-5In solder 37 was supplied. The terminals 38 on the organic substrate 54 (printed substrate) are supplied with Sn-3Ag-0.5Cu solder 59 in advance by printing. Then, this package is transferred to another LSI
The package was mounted on a printed circuit board at the same time as components, etc., and the temperature was controlled at a maximum of 240 ° C. and a conveyor speed of 1 m / min in the air using a forced circulation air reflow furnace in which the temperature distribution in the substrate was easy to be uniform. The package side of the bonded bumps is mainly Sn-Cu-In even if mixed.

【0051】単にSn-3Ag-0.5Cuのボール、Sn-3Ag-0.5Cu
ペーストで接合したものは、例えば-55〜125℃の温度サ
イクル試験にかけると、パッケージ側に近い接合界面近
傍の応力集中し易いはんだ部(A部)60で破壊する。Sn
-Cu-In系はんだの場合、柔らかく、伸びがあり、強度が
小さいため、この応力集中をはんだが変形してくれるこ
とで緩和することができるので寿命向上にも繋がる。他
方、落下等の衝撃に対しても、同様な効果が期待でき
る。即ち、応力集中個所は同じ個所(A部)であり、落
下時の衝撃で、Sn-3Ag-0.5Cuならば応力集中で接合界面
に作用し、持ちこたえることができず、接合界面近傍の
はんだ部、もしくは接合界面になる。はんだによる接合
強度は高くても、応力集中があると一点に集中し、通常
は問題がなくても、そこが起点になって破壊する。
Simply Sn-3Ag-0.5Cu ball, Sn-3Ag-0.5Cu
When bonded by a paste, for example, when subjected to a temperature cycle test at −55 to 125 ° C., the solder portion (A portion) 60 where stress tends to concentrate near the bonding interface near the package side is broken. Sn
In the case of -Cu-In based solder, since the solder is soft, stretched and has low strength, the stress concentration can be mitigated by the deformation of the solder, which leads to an improvement in the service life. On the other hand, a similar effect can be expected for an impact such as a fall. In other words, the stress concentration location is the same location (part A), and the impact at the time of dropping, if Sn-3Ag-0.5Cu, acts on the bonding interface due to the stress concentration and cannot withstand, the solder near the bonding interface Part or bonding interface. Even if the bonding strength by solder is high, stress concentration concentrates at one point, and even if there is no problem, it breaks at the starting point.

【0052】従って、現象的には応力集中部で、はんだ
が柔らかく、変形し易い構造にすることが重要である。
はんだの材料特性として、引張強度が小さいこと、伸び
に優れること、ヤング率が小さいこと等がポイントにな
る。このためには、金属組織上では、応力集中部のSn晶
の中にAg3Snが分散しない構成であること、Sn晶を柔ら
かくするため柔らかいInを固溶させた組織であり、Cuは
共晶(0.75%)より少な目に入れてInで低融点化する構成
とするのが望ましい。
Therefore, phenomenologically, it is important to provide a structure in which the solder is soft and easily deformed at the stress concentration portion.
The material properties of the solder include low tensile strength, excellent elongation, and low Young's modulus. For this purpose, on the metallographic structure, Ag3Sn is not dispersed in the Sn crystal at the stress concentration part, and the soft In is dissolved in order to soften the Sn crystal, and Cu is eutectic ( It is desirable to adopt a configuration in which the melting point is reduced by In with a smaller amount than 0.75%).

【0053】他の応用例として、BGAのバンプをSn-C
u-In系とし、リペアを重要視することから、基板の耐熱
性の制約から低温系のSn-1Ag-(40〜57Bi)(固相線温度;
137℃)ペーストで接合することも可能である。数回リペ
アしても高温系のSn-Cu-Inはんだ形状はくずれず、基板
側のはんだを200℃近傍でレベリング、供給することで
可能である。
As another application example, a BGA bump is formed of Sn-C
Because of the importance of repair, the low-temperature system Sn-1Ag- (40-57Bi) (solidus temperature;
(137 ° C) It is also possible to join with paste. Even after several repairs, the shape of the high-temperature Sn-Cu-In solder does not change, and the solder on the substrate side can be leveled and supplied at around 200 ° C.

【0054】[0054]

【発明の効果】本発明によれば、電子機器における耐落
下もしくは衝撃性を向上させることができる。また、大
変形を伴う熱衝撃に弱いSiチップ等をダイボンドした半
導体装置やプリント基板へのBGA、CSPの接続にお
いても、Sn-Ag-CuのPbフリーはんだでは界面破壊が起こ
る場合があるが、本発明ではそれを抑制することができ
る。また、大きな応力が作用するパワーモジュールにお
けるはんだ接続の信頼性を向上させることができる。
According to the present invention, drop resistance or impact resistance of an electronic device can be improved. Also, in the connection of BGA and CSP to semiconductor devices and printed circuit boards that are die-bonded to Si chips and the like that are weak to thermal shock accompanied by large deformation, Sn-Ag-Cu Pb-free solder may cause interface breakdown, In the present invention, this can be suppressed. Further, the reliability of the solder connection in the power module to which a large stress acts can be improved.

【0055】また、Snは低温になるとβ-Sn(体心正方
晶)からα-Sn(立方晶)に変態すること(pest)が知られ
ている(表面実装形LSIパッケージの実装技術とその信頼
性向上、応用技術出版株式会社、p357,368)。そして、S
n-CuはSnの変態が起き易いと言われている。特に急冷凝
固したサンプルを長時間低温放置すると、特に応力的な
影響よるためかpestの発生する確率が高くなることが予
想される。Snにとけ込み易く、柔らかいInを添加するこ
とで、特に粒界等での応力低下をもたらし、Pb同様、pe
stの発生を遅延させる効果が期待できる。
It is known that Sn changes (pest) from β-Sn (body-centered tetragonal) to α-Sn (cubic) at low temperatures (the mounting technology of surface-mount type LSI package and its transformation). Reliability Improvement, Applied Technology Publishing Co., Ltd., p357,368). And S
It is said that n-Cu easily undergoes Sn transformation. In particular, when a rapidly solidified sample is left at a low temperature for a long time, it is expected that the probability of occurrence of pest is increased, possibly due to the influence of stress. Addition of soft In, which is easy to melt into Sn, causes a decrease in stress especially at grain boundaries and the like.
The effect of delaying the generation of st can be expected.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 携帯電話を落下させたときの衝撃伝達モデル
を示す図。
FIG. 1 is a diagram showing an impact transmission model when a mobile phone is dropped.

【図2】 Sn-0.5CuへのInの添加量と伸び、引張強さ、
硬さを示す図。
Fig. 2 Addition amount of In to Sn-0.5Cu and elongation, tensile strength,
The figure which shows hardness.

【図3】 Sn-0.7CuへのAgの添加量と伸び、引張強さを
示す図。
FIG. 3 is a graph showing the amount of Ag added to Sn-0.7Cu, elongation, and tensile strength.

【図4】落下衝撃による衝撃力の経時変化を示す図。FIG. 4 is a diagram showing a temporal change of an impact force due to a drop impact.

【図5】パッケージ断面を示す図。FIG. 5 is a diagram showing a cross section of a package.

【図6】パワーモジュール断面を示す図。FIG. 6 is a diagram showing a cross section of a power module.

【図7】BGA,CSPの断面モデル図FIG. 7 is a cross-sectional model diagram of BGA and CSP.

【図8】BGA、CSP、モジュール、チップ部品等を
搭載したプリント基板の断面モデル
FIG. 8 is a cross-sectional model of a printed circuit board on which BGAs, CSPs, modules, chip components, etc. are mounted.

【図9】パッケージを有機基板に接合する断面モデルFIG. 9 is a cross-sectional model for bonding a package to an organic substrate.

【符号の説明】[Explanation of symbols]

1. 伸び 17. 基板 2. 引張強さ 18. はんだ 3. 携帯電話 19. 樹脂 4. 端部 20. チップ 5. 地面 21. チップキャ
リア基板 6. 基板 22. はんだ 7. LSIパッケージ 23. Siチップ 8. 継手 24. メタライズ 9. 拘束部 25. モリブデン
板 10. 高周波 26. Niめっき 11. Siチップ 27. Al2O3絶縁基
板 12. ベース 28. W焼結-Niめ
っき 13. 樹脂パッケージ 29. Cu板 14. ボンデイングワイヤ 30. Niめっき 15. リード 31. はんだ 16. はんだ 32.BGA 33.CSP 34.RFモジュー
ル 35.樹脂 36.外部接続端子 37.Sn-Cu-In系は
んだ 38.Cuパッド 46.Au、Ni/Au等 47.導電樹脂バンプ 48.導電樹脂もし
くは複合はんだ 51.チップ部品 53.Alフィン 54.有機基板 55.42アロイリー
ド 56.TSOPパッケージ 58. CSPパッケ
ージ 59. Sn-3Ag-0.5Cuペースト 60. 応力集中部
1. Elongation 17. Substrate 2. Tensile strength 18. Solder 3. Cell phone 19. Resin 4. Edge 20. Chip 5. Ground 21. Chip carrier substrate 6. Substrate 22. Solder 7. LSI package 23. Si chip 8. Joint 24. Metallization 9. Restraint part 25. Molybdenum plate 10. High frequency 26. Ni plating 11. Si chip 27. Al2O3 insulating substrate 12. Base 28. W sintered-Ni plating 13. Resin package 29. Cu plate 14 Bonding wire 30. Ni plating 15. Lead 31. Solder 16. Solder 32. BGA 33. CSP 34. RF module 35. Resin 36. External connection terminal 37. Sn-Cu-In solder 38. Cu pad 46. Au, Ni / Au, etc. 47. Conductive resin bump 48. Conductive resin or composite solder 51. Chip parts 53. Al fin 54. Organic substrate 55.42 Alloy lead 56. TSOP package 58. CSP package 59. Sn-3Ag-0.5Cu paste 60. Stress concentration area

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 FI テーマコート゛(参考) H01L 21/60 H01L 23/12 501Z 23/12 501 21/92 603B (72)発明者 中塚 哲也 神奈川県横浜市戸塚区吉田町292番地 株 式会社日立製作所生産技術研究所内 (72)発明者 中村 真人 神奈川県横浜市戸塚区吉田町292番地 株 式会社日立製作所生産技術研究所内 (72)発明者 藤田 祐治 神奈川県横浜市戸塚区吉田町292番地 株 式会社日立製作所生産技術研究所内 (72)発明者 石田 寿治 神奈川県横浜市戸塚区吉田町292番地 株 式会社日立製作所生産技術研究所内 (72)発明者 岡本 正英 神奈川県横浜市戸塚区吉田町292番地 株 式会社日立製作所生産技術研究所内 (72)発明者 芹沢 弘二 神奈川県横浜市戸塚区吉田町292番地 株 式会社日立製作所生産技術研究所内 (72)発明者 八矢 登志広 茨城県ひたちなか市稲田1410番地 株式会 社日立製作所デジタルメディア製品事業部 内 (72)発明者 椋野 秀樹 茨城県ひたちなか市大字高場2520番地 株 式会社日立製作所自動車機器グループ内 Fターム(参考) 5E319 AA03 AB01 AB05 AC02 BB04 BB05 BB10 CC33 CD27 CD28 CD29 GG20 5F044 KK02 LL01 QQ03 5F047 AA11 BA06 BA14 BA17 BA19 BB04 BB11 BB16 ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H01L 21/60 H01L 23/12 501Z 23/12 501 21/92 603B (72) Inventor Tetsuya Nakatsuka Yokohama, Kanagawa 292, Yoshida-cho, Totsuka-ku, Ichitoshi, Ltd.Production Technology Research Laboratory, Hitachi, Ltd. (72) Inventor Masato Nakamura 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture, Ltd.Production Technology Research Laboratory, Hitachi, Ltd. (72) Inventor Yuji Fujita, Kanagawa 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Japan Inside Hitachi, Ltd.Production Technology Research Laboratories (72) Inventor Toshiharu Ishida 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Hitachi, Ltd. Production Technology Research Laboratories (72) Inventor Okamoto Masahide 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside Hitachi, Ltd. Production Technology Laboratory (72) Person Koji Serizawa 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Hitachi, Ltd.Production Technology Research Institute (72) Inventor Toshihiro Haya 1410 Inada, Hitachinaka-shi, Ibaraki Digital Media Product Division, Hitachi, Ltd. 72) Inventor Hideki Mukuno 2520 Takada, Hitachinaka-shi, Ibaraki F-term (reference) 5E319 AA03 AB01 AB05 AC02 BB04 BB05 BB10 CC33 CD27 CD28 CD29 GG20 5F044 KK02 LL01 QQ03 5F047 AA11 BA17 BA19 BB04 BB11 BB16

Claims (12)

【特許請求の範囲】[Claims] 【請求項1】回路基板と、該回路基板の有する電極と電
気的に接続する電子部品とを備え、該回路基板の有する
電極と該電子部品の有する電極とをCu:0〜2.0mass%、I
n:0.1〜7.0mass%、残りSnからなる鉛フリーはんだを用
いてはんだ接続したことを特徴とする電子機器。
1. A circuit board, comprising: an electronic component electrically connected to an electrode of the circuit board, wherein the electrode of the circuit board and the electrode of the electronic component are Cu: 0 to 2.0 mass%, I
Electronic equipment characterized by being connected by soldering using a lead-free solder consisting of n: 0.1 to 7.0 mass% and the remaining Sn.
【請求項2】前記鉛フリーはんだがCu:0.1〜1.5mass%、
In:0.5〜2.0mass%、残りSnからなることを特徴とする請
求項1記載の電子機器。
2. The method according to claim 1, wherein the lead-free solder has a Cu content of 0.1 to 1.5 mass%.
2. The electronic device according to claim 1, wherein In: 0.5 to 2.0 mass%, and the balance is Sn.
【請求項3】前記鉛フリーはんだがCu:0.1〜1.5mass%、
In:0.5〜7.0mass%、Ag:0〜1.0mass%、残りSnからなるこ
とを特徴とする請求項1記載の電子機器。
3. The lead-free solder has a Cu content of 0.1 to 1.5 mass%,
2. The electronic device according to claim 1, wherein In: 0.5 to 7.0 mass%, Ag: 0 to 1.0 mass%, and the remaining Sn.
【請求項4】前記鉛フリーはんだがCu:0.1〜1.5mass%、
In:0.5〜7.0mass%、Bi:0〜1.0mass%、残りSnからなる
ことを特徴とする請求項1記載の電子機器。
4. The method according to claim 1, wherein the lead-free solder comprises Cu: 0.1 to 1.5 mass%,
2. The electronic device according to claim 1, wherein In: 0.5 to 7.0 mass%, Bi: 0 to 1.0 mass%, and the remaining Sn.
【請求項5】前記電子部品の有する電極が前記鉛フリー
はんだで形成されたはんだバンプであることを特徴とす
る請求項1〜4記載の電子機器。
5. The electronic device according to claim 1, wherein the electrode of the electronic component is a solder bump formed of the lead-free solder.
【請求項6】前記電子部品の有する電極にSn-(1〜10)
mass% Biのめっき層を形成してはんだ接続したことを特
徴とする請求項1〜4のいずれかに記載の電子機器。
6. An electrode of said electronic component is provided with Sn- (1-10).
The electronic device according to any one of claims 1 to 4, wherein a plating layer of mass% Bi is formed and connected by soldering.
【請求項7】前記電子部品の有する電極にSn-(0.2〜
2)mass% Cuのめっき層を形成してはんだ接続したこと
を特徴とする請求項1〜4のいずれかに記載の電子機
器。
7. The electrode of the electronic component has a Sn- (0.2 to
The electronic device according to any one of claims 1 to 4, wherein a plating layer of mass% Cu is formed and connected by soldering.
【請求項8】半導体素子と、該半導体素子と電気的に接
続するバンプとを備え、該はんだバンプがCu:0〜2.0mas
s%、In:0.1〜7.0mass%、残りSnからなる鉛フリーはんだ
であることを特徴とする半導体装置。
8. A semiconductor device comprising: a semiconductor element; and a bump electrically connected to the semiconductor element.
A semiconductor device characterized by being a lead-free solder comprising s%, In: 0.1 to 7.0 mass%, and the remaining Sn.
【請求項9】前記鉛フリーはんだがCu:0.1〜1.5mass%、
In:0.5〜2.0mass%、残りSnからなることを特徴とする請
求項8記載の半導体装置。
9. The method according to claim 9, wherein the lead-free solder is Cu: 0.1-1.5 mass%,
9. The semiconductor device according to claim 8, wherein In: 0.5 to 2.0 mass%, and the remaining Sn.
【請求項10】前記鉛フリーはんだがCu:0.1〜1.5mass
%、In:0.5〜7.0mass%、Ag:0〜1.0mass%、残りSnからな
ることを特徴とする請求項8記載の半導体装置。
10. The lead-free solder has a Cu content of 0.1 to 1.5 mass.
9. The semiconductor device according to claim 8, comprising: 0.5% to 7.0% by mass, In: 0% to 1.0% by mass of Ag, and the remaining Sn.
【請求項11】半導体素子をCu:0〜2.0mass%、In:0.1〜
7.0mass%、残りSnからなる鉛フリーはんだを用いてタブ
に接続したことを特徴とする半導体装置。
11. A semiconductor device comprising Cu: 0 to 2.0 mass%, In: 0.1 to
A semiconductor device characterized by being connected to a tab using lead-free solder consisting of 7.0 mass% and the remaining Sn.
【請求項12】回路基板と、該回路基板の有する電極と
電気的に接続する電子部品とを備え、該回路基板と電気
的に接続する外部のと接続部分となる外部接続端子をC
u:0〜2.0mass%、In:0.1〜7.0mass%、残りSnからなる鉛
フリーはんだにより構成したことを特徴とする半導体モ
ジュール。
12. A circuit board comprising: a circuit board; and an electronic component electrically connected to an electrode of the circuit board. An external connection terminal serving as a connection portion with an external part electrically connected to the circuit board is provided with C.
u: A semiconductor module comprising lead-free solder consisting of 0 to 2.0 mass%, In: 0.1 to 7.0 mass%, and the remaining Sn.
JP2001053475A 2000-06-12 2001-02-28 Electronic equipment and semiconductor device Pending JP2002076606A (en)

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JP2000180714 2000-06-12
JP2000-180714 2000-06-12
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Publications (1)

Publication Number Publication Date
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Country Link
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