JP2002076017A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP2002076017A
JP2002076017A JP2000257341A JP2000257341A JP2002076017A JP 2002076017 A JP2002076017 A JP 2002076017A JP 2000257341 A JP2000257341 A JP 2000257341A JP 2000257341 A JP2000257341 A JP 2000257341A JP 2002076017 A JP2002076017 A JP 2002076017A
Authority
JP
Japan
Prior art keywords
base layer
layer
type base
semiconductor device
conductive type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2000257341A
Other languages
Japanese (ja)
Other versions
JP4788028B2 (en
Inventor
Yuichi Harada
祐一 原田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP2000257341A priority Critical patent/JP4788028B2/en
Publication of JP2002076017A publication Critical patent/JP2002076017A/en
Application granted granted Critical
Publication of JP4788028B2 publication Critical patent/JP4788028B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide a reverse-blocking semiconductor device which displays a good reverse-recovery property when it acts as a diode keeping a favorable turnoff property for a reverse-blocking IGBT. SOLUTION: P-type base layer 3 is formed on a surface of high-relative- resistance n-type base layer 2, p-type collector layer 1 is formed on the back side of the base layer 2, n-type emitter layer 4 is formed on the surface part of the p-type base layer 3, an gate-insulating film 5 is formed on a region of the p-type base film 3 between two of the n-type emitter layer 4 and on the n-type emitter layer 2, a gate electrode 6 is formed on the gate-insulating film 5, and life time killer is localized at the vicinity of the junction of the p-type collector 1 and n-type base layer 2, by He radiation or proton radiation capable of localizing the life time killer into the desired depth. By the localization of life time killer, a reverse-recovery peak current (Irp) when a diode is active can be reduced and the property of reverse-blocking semiconductor becomes a soft-recovery type.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】この発明は、電力用スイッチ
ング素子である逆阻止型IGBTなどの半導体装置に関
する。
[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device such as a reverse blocking IGBT which is a power switching element.

【0002】[0002]

【従来の技術】現在スイッチング半導体素子として一般
的にバイポーラトランジスタ(以下、BJTと称す:B
ipolar Junction Transisto
r)、MOS型電界効果トランジスタ(以下、MOSF
ETと称す)、絶縁ゲート型バイポーラトタンジスタ
(以下、IGBTと称す)がその用途に応じて使用され
ている。
2. Description of the Related Art At present, bipolar transistors (hereinafter referred to as BJTs) are generally used as switching semiconductor elements.
ipolar Junction Transisto
r), MOS type field effect transistor (hereinafter, MOSF)
ET) and an insulated gate bipolar transistor (hereinafter, referred to as IGBT) are used depending on the application.

【0003】BJTは、飽和状態では伝導度変調を起こ
していることから、オン抵抗は小さいが、スイッチング
速度特にターンオフ時は少数キャリアの蓄積効果による
過剰キャリアが存在するため、ターンオフ時間が長くな
り、比較的低周波数領域で用いられる。また、電流駆動
の素子であることから駆動回路での発生損失が大きくな
る。
The BJT has a small on-resistance due to conductivity modulation in a saturated state, but has a long turn-off time due to the presence of excess carriers due to the accumulation effect of minority carriers at the switching speed, especially at the time of turn-off. Used in relatively low frequency range. Further, since the element is a current-driven element, a loss generated in the drive circuit increases.

【0004】これに対して、MOSFETは電圧駆動型
の素子であることから駆動回路での発生損失が小さく、
また本来少数キャリアが蓄積することがないのでスイッ
チング速度は速い。しかし、少数キャリアの注入に基づ
く伝導度変調が起こらないので、オン抵抗が大きくなる
という問題がある。IGBTは、MOSFETと同様
に、電圧駆動型の素子であることから駆動回路での発生
損失は小さく、また、BJTと同様に、少数キャリアの
注入に基づく伝導度変調を起こしていることからオン抵
抗は小さくできる。
On the other hand, since the MOSFET is a voltage-driven element, the loss generated in the drive circuit is small,
The switching speed is high because minority carriers do not accumulate. However, since conductivity modulation due to the injection of minority carriers does not occur, there is a problem that the on-resistance increases. The IGBT is a voltage-driven element, similar to a MOSFET, so that the loss generated in the drive circuit is small. Similarly to the BJT, the IGBT has a conductivity modulation based on the injection of minority carriers. Can be small.

【0005】しかし、ターンオフ時は少数キャリアの蓄
積効果に加えて、空乏層の広がりにより掃き出される多
数キャリアにより、裏面からの少数キャリアの再注入が
あるために、ターンオフ時間が遅くなる。従って、一般
的には、スイッチング回路において、BJTやIGBT
は、定常損失は小さいが、スイッチング損失が大きいた
めに、比較的低周波数で用いられることが多く、一方、
MOSFETは、逆に、定常損失は大きいが、スイッチ
ング損失が小さいために、比較的高周波数で用いられる
ことが多い。
However, at the time of turn-off, in addition to the effect of accumulating minority carriers, minority carriers are re-injected from the back surface due to majority carriers swept out by the expansion of the depletion layer, so that the turn-off time is delayed. Therefore, generally, in a switching circuit, BJT or IGBT is used.
Has a small steady-state loss, but is often used at a relatively low frequency because of a large switching loss.
On the other hand, MOSFETs, on the other hand, have a large steady-state loss but a small switching loss, and thus are often used at relatively high frequencies.

【0006】MOSFETは、その構造上耐圧特性が得
られるpn接合部は1箇所であることから耐圧特性は順
耐圧にしか示さない。これに対し、BJTとIGBTは
2箇所のpn接合を有している。しかし、BJTは、エ
ミッタ層からのキャリアの注入を大きくするために、エ
ミッタ層の濃度を高くしている。このため、ベース−エ
ミッタ間のPN接合の降伏電圧が小さく、順逆双方に対
して同等の耐圧特性を得ることはできない。
Since the MOSFET has only one pn junction where the withstand voltage characteristic is obtained due to its structure, the withstand voltage characteristic shows only the forward withstand voltage. On the other hand, the BJT and the IGBT have two pn junctions. However, in the BJT, the concentration of the emitter layer is increased in order to increase the injection of carriers from the emitter layer. For this reason, the breakdown voltage of the PN junction between the base and the emitter is small, and it is impossible to obtain the same breakdown voltage characteristics in both forward and reverse directions.

【0007】一方、IGBTは第1導電型ベース層内に
空乏層を広げることで耐圧特性を得ているため、表面側
の第1導電型ベース層と第2導電型ベース層、裏面側の
第1導電型ベース層と第2導電型コレクタ層のそれぞれ
のPN接合部分で、ほぼ同等の降伏電圧を確保できる。
従って、IGBTは順逆双方の耐圧特性を得ることは原
理的に可能である。しかし、通常のIGBTは、プレー
ナ型の周辺耐圧構造を採用しエミッタ層のある表面側の
みに形成するため、順方向の耐圧特性しか有すさない。
On the other hand, since the IGBT obtains a breakdown voltage characteristic by expanding a depletion layer in the first conductive type base layer, the first conductive type base layer and the second conductive type base layer on the front surface side and the second conductive type base layer on the back surface side. At the respective PN junctions of the one conductivity type base layer and the second conductivity type collector layer, substantially the same breakdown voltage can be secured.
Therefore, it is possible in principle for the IGBT to obtain both forward and reverse breakdown voltage characteristics. However, since a normal IGBT employs a planar-type peripheral withstand voltage structure and is formed only on the surface side where the emitter layer is located, it has only a forward withstand voltage characteristic.

【0008】これに対して、図11に示す特開平7−3
07469号公報に開示されている逆阻止型IGBT
は、素子側壁のNベース層51にP層57を形成するこ
とにより逆阻止耐圧特性を得ることができる。尚、図中
の符号で、52はPベース層、53はNエミッタ層、5
4はゲート絶縁膜、55はゲート電極、56はPコレク
タ層、58はエミッタ電極、59はコレクタ電極、60
は金属膜である。
On the other hand, FIG.
Reverse blocking IGBT disclosed in Japanese Patent No. 07469
By forming the P layer 57 on the N base layer 51 on the side wall of the device, reverse blocking breakdown voltage characteristics can be obtained. In the figure, reference numeral 52 denotes a P base layer, 53 denotes an N emitter layer,
4 is a gate insulating film, 55 is a gate electrode, 56 is a P collector layer, 58 is an emitter electrode, 59 is a collector electrode, 60
Is a metal film.

【0009】また、この逆阻止型IGBTを逆並列接続
することにより双方向IGBTとすることができる。こ
の双方向IGBTを用いると直流電流ばかりでなく交流
電流の制御も可能となる。
Further, a bidirectional IGBT can be obtained by connecting the reverse blocking IGBT in an anti-parallel manner. The use of this bidirectional IGBT enables control of not only DC current but also AC current.

【0010】[0010]

【発明が解決しようとする課題】つぎに、この双方向I
GBTを、交流から交流へ直接変換する回路に用いた場
合について説明する。この直接変換回路のアームは、双
方向IGBTで構成され、この双方向IGBTを構成す
る一方の逆阻止型IGBTは還流ダイオードとしての動
作モードがある。
Next, this two-way I
A case in which the GBT is used in a circuit for directly converting AC to AC will be described. The arm of the direct conversion circuit is formed of a bidirectional IGBT, and one reverse blocking IGBT constituting the bidirectional IGBT has an operation mode as a freewheeling diode.

【0011】この逆阻止型IGBTは、逆阻止能力があ
るために、ゲートを常時オン状態とすることで、逆阻止
耐圧があるダイオードとして動作させることができる。
しかし、前記の直接変換回路で、この逆阻止型IGBT
を還流ダイオードとして動作させる場合は、逆回復電流
を小さくすることが要求される。しかし、前記の公報で
は、前記逆阻止型IGBTをダイオードとして動作させ
ることは開示されておらず、従って、ダイオードとして
動作させた場合の逆回復電流を小さくする方法について
も開示されていない。
Since the reverse blocking IGBT has a reverse blocking capability, it can be operated as a diode having a reverse blocking withstand voltage by keeping the gate always on.
However, in the direct conversion circuit, the reverse blocking IGBT is used.
Is required to reduce the reverse recovery current. However, the above publication does not disclose operating the reverse blocking IGBT as a diode, and thus does not disclose a method of reducing the reverse recovery current when operating the diode as a diode.

【0012】この発明の目的は、逆阻止型IGBTの良
好なターンオフ特性を維持しながら、ダイオード動作さ
せた場合に良好な逆回復特性を示す逆阻止型の半導体装
置を提供することである。
An object of the present invention is to provide a reverse-blocking semiconductor device which exhibits good reverse recovery characteristics when operated as a diode while maintaining good turn-off characteristics of the reverse-blocking IGBT.

【0013】[0013]

【課題を解決するための手段】前記の目的を達成するた
めに、第1導電型ベース層と、該第1導電型ベース層の
表面に選択的に形成された第2導電型ベース層と、該第
2導電型ベース層の表面に選択的に形成された第1導電
型ソース層と、前記第1導電型ベース層と前記第1導電
型ソース層に挟まれた前記第2導電型ベース層上にゲー
ト絶縁膜を介して形成されたゲート電極と、前記第1導
電型ソース層と第2導電型ベース層に接触して形成され
た第1主電極と、前記第1導電型ベース層の裏面に形成
された第2導電型コレクタ層と、該コレクタ層上に形成
された第2主電極とを備え、順阻止耐圧と同等の逆阻止
耐圧を有する半導体装置において、第1導電型ベース層
と第2導電型コレクタ層の接合近傍にライフタイムキラ
ーを局在化させる構成とする。
In order to achieve the above object, a first conductivity type base layer, a second conductivity type base layer selectively formed on the surface of the first conductivity type base layer, A first conductivity type source layer selectively formed on the surface of the second conductivity type base layer; and the second conductivity type base layer sandwiched between the first conductivity type base layer and the first conductivity type source layer. A gate electrode formed thereon via a gate insulating film, a first main electrode formed in contact with the first conductive type source layer and the second conductive type base layer, and a first conductive type base layer. In a semiconductor device having a second conductivity type collector layer formed on the back surface and a second main electrode formed on the collector layer and having a reverse blocking breakdown voltage equivalent to a forward blocking breakdown voltage, a first conductivity type base layer is provided. A lifetime killer near the junction between the collector layer and the second conductivity type collector layer And it formed.

【0014】前記ライフタイムキラーの分布のピーク位
置が、前記第1導電型ベース層と前記第2導電型ベース
層で形成されるPN接合に印加される逆バイアス電圧
で、空乏層が到達しない前記第1導電型ベース層内とす
るとよい。前記ライフタイムキラーの分布のピークが、
前記第1導電型ベース層内に存在し、前記ピークの位置
と前記PN接合の位置との距離が0μmないし40μm
であるとよい。
The peak position of the distribution of the lifetime killer is a reverse bias voltage applied to a PN junction formed by the first conductivity type base layer and the second conductivity type base layer, and the depletion layer does not reach the depletion layer. It is good to be inside the first conductivity type base layer. The peak of the lifetime killer distribution is
The distance between the peak position and the PN junction position is in the first conductivity type base layer and is 0 μm to 40 μm.
It is good.

【0015】前記ライフタイムキラーが、イオン照射で
導入され、このイオンがヘリウムイオンもしくは水素イ
オンであると効果的である。前記逆阻止耐圧を得るため
に、前記第1導電型ベース層の外周部表面に、第2導電
型ベース層の側面を取り囲むように形成された第2導電
型の第1半導体層と、該第1半導体層に接し、前記第2
導電型コレクタ層と接する第2導電型の第2半導体層を
備えた耐圧構造を有するとよい。また、ベベル構造を有
すると効果的である。
[0015] It is effective that the lifetime killer is introduced by ion irradiation, and this ion is a helium ion or a hydrogen ion. A second conductive type first semiconductor layer formed on the outer peripheral surface of the first conductive type base layer so as to surround the side surface of the second conductive type base layer; Contacting the first semiconductor layer;
It is preferable to have a withstand voltage structure including a second conductive type second semiconductor layer in contact with the conductive type collector layer. It is effective to have a bevel structure.

【0016】前記のように、ライフタイムキラーを裏面
側の第1導電型ベース層と第2導電型コレクタ層の接合
部分付近に局在化させることにより、逆阻止型IGBT
のターンオフ時間を短縮できて、かつ、ダイオードとし
て動作させた場合に、逆回復電流を小さくすることがで
きる。
As described above, by making the lifetime killer localized near the junction between the first conductivity type base layer and the second conductivity type collector layer on the back side, a reverse blocking IGBT is provided.
Can be reduced, and the reverse recovery current can be reduced when operated as a diode.

【0017】[0017]

【発明の実施の形態】以下、図を参照しながらこの発明
の実施例を説明する。以下の実施例ではすべて第1導電
型をN型、第2導電型をP型とするがこれを逆にしても
構わない。図1は、この発明の第1実施例の半導体装置
の要部断面図である。ここでは、半導体装置は逆阻止型
IGBTである。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. In all of the following embodiments, the first conductivity type is N-type and the second conductivity type is P-type, but this may be reversed. FIG. 1 is a sectional view of a main part of a semiconductor device according to a first embodiment of the present invention. Here, the semiconductor device is a reverse blocking IGBT.

【0018】高比抵抗のNベース層2の表面にPベース
層3を形成し、裏面側にPコレクタ層1を形成する。活
性領域のPベース層3の表面部にはNエミッタ層4を形
成する。2つのNエミッタ層4で挟まれた領域のPベー
ス層3とNベース層2の上にはゲート絶縁膜5を形成
し、さらにゲート絶縁膜5の上にゲート電極6を形成す
る。表面から形成された各層およびゲート電極6が形成
されたエミッタ側表面は層間絶縁膜7で覆われ、これに
コンタクト孔が開けられさらにPベース層3およびNエ
ミッタ層4に接触するエミッタ電極8を形成し、裏面の
Pコレクタ層1上にコレクタ電極9を形成する。つぎ
に、耐圧構造16の外周部とPコレクタ層1に接するよ
うに、Nベース層2の側壁にはP層11を形成する。
A P base layer 3 is formed on the surface of an N base layer 2 having a high specific resistance, and a P collector layer 1 is formed on the back side. An N emitter layer 4 is formed on the surface of the P base layer 3 in the active region. A gate insulating film 5 is formed on the P base layer 3 and the N base layer 2 in a region sandwiched between the two N emitter layers 4, and a gate electrode 6 is formed on the gate insulating film 5. Each layer formed from the surface and the emitter side surface on which the gate electrode 6 is formed are covered with an interlayer insulating film 7, a contact hole is formed in the interlayer insulating film 7, and an emitter electrode 8 contacting the P base layer 3 and the N emitter layer 4 is formed. The collector electrode 9 is formed on the P collector layer 1 on the back surface. Next, a P layer 11 is formed on the side wall of the N base layer 2 so as to be in contact with the outer peripheral portion of the breakdown voltage structure 16 and the P collector layer 1.

【0019】前記のコレクタ電極9を形成する前に、ラ
イフタイム制御を行う。このライフタイム制御は、従来
のように、電子線照射などの素子全体に対して均一なラ
イフタイムキラーを用いるのではなく、任意の深さに局
所的にライフタイムキラーを存在させることのできるH
e照射やプロトン照射などを用い、Pコレクタ層1とN
ベース層2との接合付近に局在化させる。
Before forming the collector electrode 9, lifetime control is performed. This lifetime control does not use a uniform lifetime killer for the whole device such as electron beam irradiation as in the conventional technology, but instead allows a lifetime killer to exist locally at an arbitrary depth.
e irradiation, proton irradiation, etc., the P collector layer 1 and N
It is localized near the junction with the base layer 2.

【0020】このように、ライフタイムキラーを接合付
近に局在化させることで、ターンオフ時は空乏層が拡が
った状態でもライフタイムキラーが有効に働くことから
高速なターンオフ特性となる。また、Pコレクタ層1と
Nベース層2からなるPNダイオードの逆回復特性は、
Nベース層2内の接合付近のキャリア濃度が小さくなる
ために逆回復ピーク電流(Irp)が小さくソフトリカ
バリの良好な特性を示す。図2にターンオフ波形、図3
にダイオード動作させた時の逆回復波形を示す。ここで
Aは本発明品、Bは従来品である。
As described above, by localizing the lifetime killer near the junction, the lifetime killer works effectively even when the depletion layer is expanded at the time of turn-off, so that a high-speed turn-off characteristic is obtained. The reverse recovery characteristic of the PN diode composed of the P collector layer 1 and the N base layer 2 is as follows.
Since the carrier concentration near the junction in the N base layer 2 becomes small, the reverse recovery peak current (Irp) is small and good characteristics of soft recovery are exhibited. FIG. 2 shows the turn-off waveform, FIG.
Shows a reverse recovery waveform when the diode is operated. Here, A is a product of the present invention, and B is a conventional product.

【0021】また、側壁部分にP層11を設けることに
より、Nベース層2とPコレクタ層1のPN接合部分が
逆バイアス状態(逆阻止状態)になった場合、空乏層は
Nベース層2内を上方向に向かって広がるとともに、P
層11より素子の内側に向かって横方向に広がる。横方
向に広がる空乏層は表面に形成されたプレーナ型の耐圧
構造を利用して、逆向きに広がることで、素子の逆阻止
耐圧を得ることができる。
Further, by providing the P layer 11 on the side wall, when the PN junction between the N base layer 2 and the P collector layer 1 is in a reverse bias state (reverse blocking state), the depletion layer becomes the N base layer 2. The inside spreads upward and P
It extends laterally from the layer 11 toward the inside of the device. The depletion layer that spreads in the lateral direction spreads in the opposite direction using a planar breakdown voltage structure formed on the surface, so that a reverse blocking breakdown voltage of the element can be obtained.

【0022】図4は、この発明における素子の耐圧特性
の波形図である。順阻止耐圧(順耐圧)ばかりでなく、
逆阻止耐圧(逆耐圧)があるため、この逆阻止型IGB
Tのゲートを常時オン状態にすることで、Pコレクタ層
1とNベース層2からなる、逆阻止耐圧を有するPNダ
イオードとして動作させることができる。図5は、本発
明品を逆並列接続した双方向IGBTのモデル図であ
る。このように接続した場合、耐圧特性は図4で示した
耐圧波形を示し、且つ、順逆方向のスイッチング動作を
行わせることができる双方向スイッチング素子となる。
例えば、主端子T1を接地し主端子T2に正の電圧が印
加された場合、ゲート端子G1に正の電圧を印加する
と、左側の素子(第1逆阻止型IGBT41)がオン動
作して正方向に電流が流れる。これとは逆に、主端子T
2を接地し主端子T1に正の電圧を印加した場合、ゲー
ト端子G2に正の電圧を印加することで右側の素子(第
2逆阻止型IGBT42)がオン動作して、逆方向に電
流が流れる。つまり、双方向スイッチング動作を行なわ
せることができる。
FIG. 4 is a waveform diagram showing the breakdown voltage characteristics of the device according to the present invention. Not only forward blocking voltage (forward voltage),
Since there is a reverse blocking withstand voltage (reverse withstand voltage), this reverse blocking type IGB
By always turning on the gate of T, it is possible to operate as a PN diode having a reverse blocking withstand voltage, composed of the P collector layer 1 and the N base layer 2. FIG. 5 is a model diagram of a bidirectional IGBT in which the products of the present invention are connected in anti-parallel. When connected in this way, the withstand voltage characteristic shows the withstand voltage waveform shown in FIG. 4 and is a bidirectional switching element capable of performing forward and reverse switching operations.
For example, when the main terminal T1 is grounded and a positive voltage is applied to the main terminal T2, when a positive voltage is applied to the gate terminal G1, the left element (the first reverse blocking IGBT 41) is turned on to move in the positive direction. Current flows through Conversely, the main terminal T
2 is grounded and a positive voltage is applied to the main terminal T1, a positive voltage is applied to the gate terminal G2 to turn on the element on the right (the second reverse blocking IGBT 42), and a current flows in the reverse direction. Flows. That is, a bidirectional switching operation can be performed.

【0023】この双方向IGBTは、これを構成する逆
阻止型IGBT41、42のターンオフ特性やダイオー
ド動作時の逆回復特性などと同等の特性を有することは
勿論である。図6は、この本発明の第2実施例の半導体
装置の要部断面図である。ここでは、半導体装置は逆阻
止型IGBTである。
Of course, the bidirectional IGBT has characteristics equivalent to the turn-off characteristics of the reverse blocking IGBTs 41 and 42 and the reverse recovery characteristics during the operation of the diode. FIG. 6 is a sectional view showing a main part of a semiconductor device according to a second embodiment of the present invention. Here, the semiconductor device is a reverse blocking IGBT.

【0024】ライフタイムキラーを局在化させる位置と
して、Nベース層2とPベース層3のPN接合31が逆
バイアスされた時(順方向耐圧時)に空乏化しない領域
(空乏層32が広がらない領域)のNベース層2内とす
る。この素子は、第1実施例で説明した効果と同様の効
果が期待できる。図7は、この発明の第3実施例の半導
体装置の要部断面図である。ここでは、半導体装置は逆
阻止型IGBTである。
A region where the lifetime killer is localized is a region where the depletion layer 32 is not depleted when the PN junction 31 between the N base layer 2 and the P base layer 3 is reverse biased (during forward breakdown voltage). (The region where no portion exists) within the N base layer 2. This element can be expected to have the same effects as those described in the first embodiment. FIG. 7 is a sectional view showing a main part of a semiconductor device according to a third embodiment of the present invention. Here, the semiconductor device is a reverse blocking IGBT.

【0025】ライフタイムキラーを局在化させた場合の
分布のピーク位置Lを、PN接合31からライフタイム
キラーの密度分布のピーク(分布のピーク33)までの
距離と定義したとき、ピーク位置Lを40μm以下とす
る。また、ライフタイムキラーの分布の幅X(ピーク値
の10%の範囲)は20μmである。この素子は、第1
実施例で説明した効果と同様の効果が期待できる。
When the peak position L of the distribution when the lifetime killer is localized is defined as the distance from the PN junction 31 to the peak of the density distribution of the lifetime killer (the peak 33 of the distribution), the peak position L Is set to 40 μm or less. Further, the width X (range of 10% of the peak value) of the distribution of the lifetime killer is 20 μm. This element is the first
The same effect as the effect described in the embodiment can be expected.

【0026】図8は、ダイオード動作時の逆回復ピーク
電流Irpのピーク位置L依存性を示す。ピーク位置L
を40μm以下にすると、均一なライフタイムキラー
(点線のレベル)分布をさせた場合よりも、Irpが小
さく、ソフトリカバリー波形の良好な逆回復特性を示
す。図8から、このピーク位置Lを、PN接合31に近
づけると、さらに良好な逆回復特性を示し、ピーク位置
Lを20μm以下とすると、Irpは、均一なライフタ
イムキラー分布とした場合の1/2程度に低減される。
FIG. 8 shows the peak position L dependence of the reverse recovery peak current Irp during the diode operation. Peak position L
Is set to 40 μm or less, Irp is smaller than that in a case where uniform lifetime killer (dotted level) distribution is obtained, and a favorable reverse recovery characteristic of a soft recovery waveform is exhibited. 8, when the peak position L is brought closer to the PN junction 31, even better reverse recovery characteristics are exhibited. When the peak position L is set to 20 μm or less, Irp is 1/1 of the case of a uniform lifetime killer distribution. It is reduced to about 2.

【0027】図9は、この本発明の第4実施例の半導体
装置の要部断面図である。ここでは、半導体装置は逆阻
止型IGBTである。ライフタイムキラーを局在化させ
る位置は、前記第1実施例から第3実施例と同様である
が、これらと異なるのは、逆方向耐圧を得る構造として
ベベル構造21を適応している点である。
FIG. 9 is a sectional view showing a main part of a semiconductor device according to a fourth embodiment of the present invention. Here, the semiconductor device is a reverse blocking IGBT. The position where the lifetime killer is localized is the same as in the first to third embodiments, except that the bevel structure 21 is applied as a structure for obtaining a reverse breakdown voltage. is there.

【0028】図10は、この本発明の第5実施例の半導
体装置の要部断面図である。ここでは、半導体装置は逆
阻止型IGBT電極ある。ライフタイムキラーを局在化
させる位置は第1実施例から第3実施例と同様である
が、これらと異なるのは逆方向耐圧を得る構造として図
9と異なるベベル構造22を適応した点である。そし
て、このベベル構造22を形成する方法として、表面プ
レーナ耐圧構造の外側に表面よりPコレクタ層1に達す
る溝23を形成する。
FIG. 10 is a sectional view showing a main part of a semiconductor device according to a fifth embodiment of the present invention. Here, the semiconductor device is a reverse blocking IGBT electrode. The position at which the lifetime killer is localized is the same as in the first to third embodiments, except that a bevel structure 22 different from that of FIG. 9 is applied as a structure for obtaining a reverse breakdown voltage. . Then, as a method of forming the bevel structure 22, a groove 23 reaching the P collector layer 1 from the surface is formed outside the surface planar breakdown voltage structure.

【0029】[0029]

【発明の効果】この発明によれば、コレクタ層側のベー
ス層に局部的にライフタイムキラーを導入することによ
り、良好なスイッチング特性を維持しながら、ダイオー
ド動作時にも良好な逆回復特性を示す逆阻止型の半導体
装置が得られる。また、この逆阻止型の半導体装置を逆
並列に接続することで、良好な特性の双方向スイッチン
グ素子を製作することができる。
According to the present invention, by introducing a lifetime killer locally into the base layer on the collector layer side, a good reverse recovery characteristic can be exhibited during diode operation while maintaining good switching characteristics. A semiconductor device of a reverse blocking type is obtained. Further, by connecting the reverse blocking type semiconductor device in anti-parallel, a bidirectional switching element having good characteristics can be manufactured.

【図面の簡単な説明】[Brief description of the drawings]

【図1】この発明の第1実施例の半導体装置の要部断面
FIG. 1 is a sectional view of a main part of a semiconductor device according to a first embodiment of the present invention;

【図2】本発明品と従来品のターンオフ波形図FIG. 2 is a turn-off waveform diagram of a product of the present invention and a conventional product.

【図3】本発明品と従来品の逆回復波形図FIG. 3 is a reverse recovery waveform diagram of a product of the present invention and a conventional product.

【図4】この発明における素子の耐圧特性の波形図FIG. 4 is a waveform chart of breakdown voltage characteristics of the element according to the present invention.

【図5】本発明品を逆並列接続した双方向IGBTのモ
デル図
FIG. 5 is a model diagram of a bidirectional IGBT in which products of the present invention are connected in anti-parallel.

【図6】この本発明の第2実施例の半導体装置の要部断
面図
FIG. 6 is a sectional view of a main part of a semiconductor device according to a second embodiment of the present invention;

【図7】この発明の第3実施例の半導体装置の要部断面
FIG. 7 is a sectional view of a main part of a semiconductor device according to a third embodiment of the present invention;

【図8】ダイオード動作時の逆回復ピーク電流Irpの
ピーク位置L依存性を示す図
FIG. 8 is a view showing the peak position L dependence of the reverse recovery peak current Irp during the diode operation.

【図9】この本発明の第4実施例の半導体装置の要部断
面図
FIG. 9 is a sectional view of a main part of a semiconductor device according to a fourth embodiment of the present invention;

【図10】この本発明の第5実施例の半導体装置の要部
断面図
FIG. 10 is a sectional view of a main part of a semiconductor device according to a fifth embodiment of the present invention;

【図11】従来の逆阻止型IGBTの要部断面図FIG. 11 is a sectional view of a main part of a conventional reverse blocking IGBT.

【符号の説明】[Explanation of symbols]

1 Pコレクタ層 2 Nベース層 3 Pベース層 4 Nエミッタ層 5 ゲート絶縁膜 6 ゲート電極 7 層間絶縁膜 8 エミッタ電極 9 コレクタ電極 11、12、13 P層 14 金属膜 15 絶縁膜 16 耐圧構造 17 活性領域 20 ライフタイムキラー 21、22 ベベル構造 31 PN接合 32 空乏層 33 分布のピーク 41 第1逆阻止型IGBT 42 第2逆阻止型IGBT G ゲート端子 E エミッタ端子 C コレクタ端子 T1、T2 主端子 G1、G2 ゲート端子 L ピーク位置 X 分布の幅 DESCRIPTION OF SYMBOLS 1 P collector layer 2 N base layer 3 P base layer 4 N emitter layer 5 Gate insulating film 6 Gate electrode 7 Interlayer insulating film 8 Emitter electrode 9 Collector electrode 11, 12, 13 P layer 14 Metal film 15 Insulating film 16 Breakdown voltage structure 17 Active region 20 Lifetime killer 21, 22 Bevel structure 31 PN junction 32 Depletion layer 33 Distribution peak 41 First reverse blocking IGBT 42 Second reverse blocking IGBT G Gate terminal E Emitter terminal C Collector terminal T1, T2 Main terminal G1 , G2 Gate terminal L Peak position X Distribution width

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】第1導電型ベース層と、該第1導電型ベー
ス層の表面に選択的に形成された第2導電型ベース層
と、該第2導電型ベース層の表面に選択的に形成された
第1導電型ソース層と、前記第1導電型ベース層と前記
第1導電型ソース層に挟まれた前記第2導電型ベース層
上にゲート絶縁膜を介して形成されたゲート電極と、前
記第1導電型ソース層と第2導電型ベース層に接触して
形成された第1主電極と、前記第1導電型ベース層の裏
面に形成された第2導電型コレクタ層と、該コレクタ層
上に形成された第2主電極とを具備し、順阻止耐圧と同
等の逆阻止耐圧を有する半導体装置において、第1導電
型ベース層と第2導電型コレクタ層の接合近傍にライフ
タイムキラーを局在化させることを特徴とする半導体装
置。
A first conductive type base layer; a second conductive type base layer selectively formed on a surface of the first conductive type base layer; and a second conductive type base layer selectively formed on a surface of the second conductive type base layer. A first conductive type source layer formed, and a gate electrode formed on the second conductive type base layer sandwiched between the first conductive type base layer and the first conductive type source layer via a gate insulating film A first main electrode formed in contact with the first conductive type source layer and the second conductive type base layer, a second conductive type collector layer formed on the back surface of the first conductive type base layer, A semiconductor device comprising a second main electrode formed on the collector layer and having a reverse blocking breakdown voltage equivalent to a forward blocking breakdown voltage, wherein a semiconductor device has a lifetime near the junction between the first conductivity type base layer and the second conductivity type collector layer. A semiconductor device characterized by localizing a time killer.
【請求項2】前記ライフタイムキラーの分布のピーク位
置が、前記第1導電型ベース層と前記第2導電型ベース
層で形成されるPN接合に印加される逆バイアス電圧
で、空乏層が到達しない前記第1導電型ベース層内とす
ることを特徴とする請求項1に記載の半導体装置。
2. A depletion layer reaches a peak position of a distribution of the lifetime killer by a reverse bias voltage applied to a PN junction formed by the first conductivity type base layer and the second conductivity type base layer. The semiconductor device according to claim 1, wherein the first conductive type base layer is not provided.
【請求項3】前記ライフタイムキラーの分布のピーク
が、前記第1導電型ベース層内に存在し、前記ピークの
位置と前記PN接合の位置との距離が0μmないし40
μmであることを特徴とする請求項2に記載の半導体装
置。
3. A peak of the lifetime killer distribution is present in the first conductivity type base layer, and a distance between a position of the peak and a position of the PN junction is 0 μm to 40 μm.
The semiconductor device according to claim 2, wherein the thickness is μm.
【請求項4】前記ライフタイムキラーが、イオン照射で
導入されることを特徴とする請求項1ないし3のいずれ
かに記載の半導体装置。
4. The semiconductor device according to claim 1, wherein said lifetime killer is introduced by ion irradiation.
【請求項5】前記イオンが、ヘリウムイオンもしくは水
素イオンであることを特徴とする請求項4に記載の半導
体装置。
5. The semiconductor device according to claim 4, wherein said ions are helium ions or hydrogen ions.
【請求項6】前記逆阻止耐圧を得るために、前記第1導
電型ベース層の外周部表面に、第2導電型ベース層の側
面を取り囲むように形成された第2導電型の第1半導体
層と、該第1半導体層に接し、前記第2導電型コレクタ
層と接する第2導電型の第2半導体層を備えた耐圧構造
を有することを特徴とする請求項1ないし5のいずれか
に記載の半導体装置。
6. A first semiconductor of a second conductivity type formed on the outer peripheral surface of the first conductivity type base layer so as to surround the side surface of the second conductivity type base layer in order to obtain the reverse blocking withstand voltage. 6. A breakdown voltage structure comprising a layer and a second conductivity type second semiconductor layer in contact with the first semiconductor layer and in contact with the second conductivity type collector layer. 13. The semiconductor device according to claim 1.
【請求項7】前記逆阻止耐圧を得るために、ベベル構造
を有することを特徴とする請求項1ないし5のいずれか
に記載の半導体装置。
7. The semiconductor device according to claim 1, wherein the semiconductor device has a bevel structure to obtain the reverse blocking withstand voltage.
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