JP2002057279A - Semiconductor device, stacked semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a stacked semiconductor device in which a plurality of wiring boards can be secured onto a base substrate without passing them through a reflow furnace for heating. SOLUTION: In a stacked semiconductor device comprising a plurality of semiconductor devices stacked on a base substrate 41, the semiconductor device comprises a flexible semiconductor chip 36 provided with an inner electrode, a flexible wiring board 30 provided with a wiring pattern 33 being connected electrically with the inner electrode of the semiconductor chip, and an outer electrode 34 provided at an end part of the wiring board and connected electrically with the wiring pattern. The stacked semiconductor device further comprises base electrodes 42 provided on the base substrate, and solders 44 electrically connecting the outer electrode of each semiconductor device fixedly to the base electrode under a state where the plurality of semiconductor devices are stacked on the base electrode of the base substrate while aligning the position of the outer electrodes.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a semiconductor chip is mounted on a wiring board, a stacked semiconductor device in which a plurality of semiconductor devices are stacked on a base substrate, and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, a small memory card equipped with a flash memory has been rapidly expanding its market for portable information devices such as digital still cameras and portable information terminals. In particular, in the field of digital cameras, MD (MINI DISC) and floppy (registered trademark) are already becoming mainstream.
It is trying to solidify its position as a replacement for discs.

In such a technical background, a small memory card including only a flash memory is required to have a larger recording capacity, a smaller size, a lighter weight, and a lower cost. The mounting structure is considered.

[0004] In general, TSOP (Thin Small Outli
ne Package) or a thin mold package soldered to the base substrate, or bare chip (BARE CHIP) wire bonding or flip chip mounting (FLIP CHIP)
MOUNTING) to connect directly to the base substrate. However, since the capacity that can be mounted on the same area is determined by the chip size, in order to further increase the capacity, three-dimensionally stacking the chips reduces the overall configuration and the pitch. There is a demand for a stacked semiconductor device having a mounting structure that can be achieved.

FIG. 29 shows a conventional stacked semiconductor device.
This stacked semiconductor device is formed by stacking a plurality of, for example, four semiconductor devices 20. Each semiconductor device 20 has a wiring board 24 in which a wiring pattern 22 is formed on a sheet-like holding member 21 made of polyimide or the like. A bump 23 made of gold or the like is formed on the wiring pattern 22, and the semiconductor chip 1 is mounted on the bump 23 by a flip chip mounting method. The semiconductor chip 1 is sealed with a resin 7 such as epoxy and packaged.

[0006] The four semiconductor devices 20 in which the semiconductor chip 1 is packaged in this manner are stacked on desired connection lands 8 of the base substrate 3 via connection members 25 such as solder balls. Each connection member 25 is provided on an electrode 26 formed at an end of each wiring board 24.

As a method of providing the solder 25 on the electrode 26 of the wiring board 24, there are a method of supplying a solder ball on the electrode 26 and a method of printing a solder paste. In any method, in order to securely connect the plurality of stacked wiring boards 24, that is, the semiconductor device 20 in a stable state by the solder 25, after supplying the solder 25 to the electrode 26, the four It is necessary to put the wiring board 24 in a reflow furnace in a state where the wiring board 24 is stacked, and to melt the solder 25 once and fix it on the electrode 26.

[0008]

However, a plurality of stacked semiconductor devices 20 are placed in a reflow furnace and soldered.
If the fixing of No. 5 is performed, the wiring board 24 may be warped due to the thermal effect at that time, or the connection portion between the semiconductor chip 1 and the wiring pattern 22 may be damaged. As a result, a defective product is generated in the semiconductor device 20 and the yield is reduced. In addition, process management was difficult.

The present invention has a simple manufacturing process,
Moreover, it is an object of the present invention to provide a semiconductor device, a stacked semiconductor device, and a method for manufacturing the same, which can be manufactured with stable quality.

[0010]

According to a first aspect of the present invention, there is provided a semiconductor chip having flexibility and provided with internal electrodes, and a flexible and electrically connected to the internal electrodes of the semiconductor chip. A wiring board on which a wiring pattern to be provided is provided;
A semiconductor device is provided which is electrically connected to the wiring pattern and has an external electrode provided at an end of the wiring substrate.

According to a second aspect of the present invention, there is provided a stacked semiconductor device in which a plurality of semiconductor devices are stacked on a base substrate, wherein the semiconductor device comprises a semiconductor chip having flexibility and provided with internal electrodes. A wiring board having flexibility and provided with a wiring pattern electrically connected to the internal electrode of the semiconductor chip; and a wiring board electrically connected to the wiring pattern and provided at an end of the wiring board. And a base electrode provided on the base substrate, and the base electrode in a state where a plurality of semiconductor devices are stacked on the base electrode of the base substrate so that the positions of the respective external electrodes are aligned. And a solder for electrically connecting and fixing external electrodes of each semiconductor device.

According to a third aspect of the present invention, in the end portion of the wiring board, a concave portion which is open at the end surface is formed, and the external electrode of the wiring substrate is formed on both the peripheral surface of the concave portion and the front and back of the wiring substrate. 3. The stacked semiconductor device according to claim 2, wherein the stacked semiconductor device is provided over a plate surface.

According to a fourth aspect of the present invention, there is provided the stacked semiconductor device according to the second aspect, wherein the external electrodes of the wiring board are provided on one plate surface of the wiring board.

According to a fifth aspect of the present invention, an open recess is formed at an end of the wiring board, and the external electrodes of the wiring board are provided so as to close the recess. The stacked semiconductor device according to claim 2.

According to a sixth aspect of the present invention, there is provided the stacked semiconductor device according to the fifth aspect, wherein a through hole is formed in a portion of the external electrode of the wiring board which closes the concave portion.

According to a seventh aspect of the present invention, the wiring boards of the plurality of semiconductor devices to be stacked are such that the external electrodes of the wiring board located above project outwardly from the external electrodes of the wiring board located below. 3. The stacked semiconductor device according to claim 2, wherein:

According to an eighth aspect of the present invention, in the stacked semiconductor device in which a plurality of semiconductor devices are stacked, the semiconductor device includes a semiconductor chip provided with internal electrodes and an internal portion of the semiconductor chip provided on at least one plate surface. A wiring board having a wiring pattern electrically connected to the electrodes, and external electrodes provided on both plate surfaces of the wiring board and electrically connected to the wiring pattern, and provided on the wiring board. A base metal layer formed on at least a part of the external electrode,
When a plurality of semiconductor devices are stacked, a connection member is provided between opposed base metal layers between adjacent semiconductor devices or between the base metal layer and an external electrode, and electrically connected and fixed to each other. The stacked semiconductor device is characterized by comprising:

According to a ninth aspect of the present invention, there is provided a semiconductor device having a base substrate provided with a base electrode, wherein a plurality of semiconductor devices are stacked by electrically connecting external electrodes to the base electrode. Item 8. The stacked semiconductor device according to Item 8.

In a tenth aspect of the present invention, the connection member is a solder layer formed by electrolytic plating on at least one of the base metal layer and the external electrode. In the device.

The invention according to claim 11 is the stacked semiconductor device according to claim 8, wherein the connecting member is an anisotropic conductive member.

According to a twelfth aspect of the present invention, the connecting member is made of an adhesive that shrinks during curing.
In the stacked semiconductor device described above.

According to a thirteenth aspect of the present invention, a heat transfer member is provided between the stacked semiconductor devices.
In the stacked semiconductor device described above.

According to a fourteenth aspect of the present invention, in the method of manufacturing a stacked semiconductor device in which a plurality of semiconductor devices are stacked on a base substrate having a base electrode, a connection member that can be electrically connected and fixed to the base electrode is provided. A flexible wiring board having an external electrode provided at an end thereof, and a flexible semiconductor chip electrically connected to the wiring board. A stacked semiconductor device comprising: a step of aligning and laminating an external electrode of the device with the base electrode; and a step of electrically connecting and fixing the aligned external electrode by the connection member. Manufacturing method.

According to a fifteenth aspect of the present invention, there is provided a laminated semiconductor device in which a plurality of semiconductor devices are formed by punching a wiring board provided with a semiconductor chip from a base member.
A plurality of wirings provided on the wiring board, one end of which is connected to the semiconductor chip; an electrode provided on the wiring board, the other end of each of the wirings being connected to the semiconductor chip among the electrodes; A chip selection terminal for specifying the semiconductor chip according to the cut and uncut state of the wiring, and a wiring which is formed open to the outer peripheral end of the wiring board and connects the chip selection terminal to the semiconductor chip. And a cutting section that performs the cutting.

According to a sixteenth aspect of the present invention, the plurality of chip selection terminals are plural, and at least a part of each wiring for connecting each chip selection terminal and the semiconductor chip is formed at a peripheral portion of a punched wiring board. The stacked semiconductor device according to claim 15, wherein the stacked semiconductor device is provided on one surface and the other surface.

According to a seventeenth aspect of the present invention, there is provided the stacked semiconductor device according to the fifteenth aspect, wherein the cut portion is formed simultaneously when the wiring substrate is punched from the frame member.

The invention according to claim 18 is a method of manufacturing a stacked semiconductor device in which a plurality of semiconductor devices are formed by punching a wiring board having wiring and electrodes provided with semiconductor chips from a base member. And punching out the wiring board from, and when punching out the wiring board from the base member, cutting at least one of the electrodes provided on the wiring board and connected to the semiconductor chip and the wiring by cutting the wiring and A step of simultaneously cutting the wiring and a step of stacking a plurality of semiconductor devices punched from the base member so as to be used as a chip selection terminal for specifying the semiconductor chip according to an uncut state. A method for manufacturing a stacked semiconductor device characterized by the following.

[0028]

Embodiments of the present invention will be described below with reference to the drawings.

FIGS. 1 to 6 show a first embodiment of the present invention. 1A to 1C show a method of manufacturing the semiconductor device 31. In FIG. 1A, reference numeral 30 denotes a holding portion 32 made of a flexible electrically insulating synthetic resin sheet such as a sheet-like polyimide having a thickness of 25 μm.
It is a wiring board having. On one surface of the holding portion 32, a wiring pattern 33 made of, for example, copper having a thickness of 18 μm is formed.

At both ends in the width direction of the holding portion 32, electrodes (external electrodes) 3 electrically connected to the wiring pattern 33 are provided.
4 are formed. The electrode 34 has a semicircular through hole 34a as a notch as shown in FIG. That is, a semicircular concave portion 35 is provided at the end of the holding portion 32.
Are formed, and the electrode 34 is formed on the inner peripheral surface of the concave portion 35 and the concave portion 35.
Are provided over the upper and lower surfaces of the holding portion 32 along the peripheral portion of the holding portion 32. The shape of the recess 35 is not limited to a semicircular shape,
The shape may be triangular or square as long as it is open toward the outside of the wiring board 30.

On the wiring pattern 33, FIG.
Is mounted. The semiconductor chip 36 is formed to have a thickness of, for example, 50 μm, and one plate surface is provided with bumps 36 a (internal electrodes) such as gold (Au) having a height of 10 to 30 μm. Then, the semiconductor chip 36 attaches the bump 3 to the wiring pattern 33.
6a via a flip-chip mounting method. The semiconductor chip 36 having a thickness of 50 μm is extremely thin as compared with the conventional one. Thereby, this semiconductor chip 3
Numeral 6 has flexibility capable of bending and deforming.

FIG. 5 is a flow chart showing the steps of manufacturing a semiconductor device according to the present invention and FIGS. 6 (a) to 6 (e).
This will be described with reference to the schematic explanatory diagram of FIG.

First, as shown in FIG.
Elements (thin film circuits) 102 on a semiconductor wafer 101 of 0 μm
are formed (S1).

Subsequently, as shown in FIG. 6B, the semiconductor wafer 101 is vertically and horizontally 140 μm deep from the surface on which the elements 102a, 102b, 102c.
Are formed and dicing is performed in a half-cut state (S2).

Next, the back surface of the element forming surface of the semiconductor wafer 101 is uniformly thinned by grinding, lapping, or the like.
3) Yes.

As shown in FIG. 6 (c), this thinning grinding is performed by applying a circuit protection coating tape 106 to the surface on which the elements 102a, 102b, 102c... Are formed, and covering the element 102a with the coating tape 106. , 102b, 102c
.., That is, the back surface of the semiconductor wafer 101 is ground by grinding to reduce the thickness of the semiconductor wafer 101.

This grinding is performed using a vertical spindle type infeed grinder (not shown). The semiconductor wafer 101 is held on a porous chuck having a smooth flat surface, and the semiconductor wafer 101 is fixed by vacuum suction using a vacuum pump during processing.

Then, the semiconductor wafer 101 is set at 300 rpm
m using a cup-shaped diamond grindstone 110 rotated at 3000 rpm at high speed.
Processing is performed while giving a cut at a feed rate of about 50 μm / min in the thickness direction of 1. The cup type diamond grindstone 110 has a particle size of about # 360 to # 3000, and is made of a thermosetting resin or ceramic as a binder.
When the thickness of the semiconductor wafer 101 is reduced by these grindings, the grooves 105a, 105 previously diced are processed.
b, 105c... when the elements 102a, 102c
are semiconductor chips 103a, 103b, 1
03c...

Next, as shown in FIG. 6D, polishing (S) using the elastic pad 107 and the slurry 108 is performed.
4), and the semiconductor chips 103a, 103b, 103
c is reduced to 80 μm or less (50 μm in this embodiment). The elastic pad 107 was made of elastic polyurethane, and the slurry 108 was made of silica (SiO 2) fine particles having a particle size of 0.1 μm or less, an amine additive, a dispersant, and pure water. Semiconductor chips 103a, 103
The b, 103c... can be made flexible by reducing the thickness to 80 μm or less, and it is possible to minimize breakage even when a force in the bending direction acts.

Further, using the elastic pads 107 and the slurry 108, the semiconductor chips 103a, 103b,
When the polishing of 103c is performed, a load concentration occurs due to the elastic action of the elastic pad 107 at the chip edge portion as shown in FIG. As a result, the removal rate at the chip edge is increased, and the chip edge can be chamfered. By chamfering, it is possible to further suppress breakage when a force in the bending direction is applied. The amine additive is chemically used for the semiconductor chip 10.
3a, 103b, 103c... Has an action of etching, and the action of chemical etching is also taken into account.

The semiconductor chip 10 thus obtained
3a, 103b, 103c,... Are joined to the lead frame using, for example, lead bonding or an insulating paste or an Ag-containing conductive paste (S5) in a mounting step on a frame or the like, and thereafter, using a sealing agent (not shown). It is sealed and packaged (S6).

As shown in FIG. 1C, the flip chip mounting method of the semiconductor chip 36 includes the anisotropic conductive member 37 in which conductive particles are dispersed in a resin and the holding portion 32 and the semiconductor chip 3.
6 and thermocompression-bonded at a temperature of 180 ° C., for example. Thereby, the semiconductor chip 36 has its bumps 3
6a is electrically connected to the wiring pattern 33, and the surface facing the holding portion 32 and the outer peripheral surface are resin-sealed.

Note that, instead of the anisotropic conductive member 37, other methods such as solder connection and crimp connection may be used. In addition, the connection between the wiring pattern 33 and the semiconductor chip 36 may be performed by any method of collective bonding and single point bonding.

Next, the plurality of semiconductor devices 31 manufactured in this manner, in this embodiment, four semiconductor devices 3
3A to 3C, a procedure for forming a stacked semiconductor device by laminating on a base substrate 41 will be described.

The base substrate 41 is made of an electrically insulating material such as a glass epoxy resin.
As shown in (a), connection lands 42 as base electrodes are formed at both ends of the upper surface by a metal such as copper. The connection lands 42 are electrically connected to the wiring patterns 43 formed on the lower surface of the base substrate 41 via through holes 43a.

Further, the connection land 42 of the base substrate 41
, A paste-like solder 44 is supplied to a predetermined position in a predetermined shape by means such as printing or coating in advance. The solder 44 supplied to the base substrate 41 may be in a paste state, but by passing it through a reflow furnace and heating,
The connection land 42 may be fixed in a ball bump shape. At this time, the base substrate 41 is heated, but the base substrate 41 is formed of a glass epoxy resin, so that warpage hardly occurs.

On the base substrate 41, four semiconductor devices 31 are supplied by a mount tool (not shown) or the like. In FIG. 3A, the wiring board 30 of each semiconductor device 31 is shown.
Although there is a gap between them, it is actually pressed against the base substrate 41 side by a pressing tool (not shown), so that there is almost no gap and almost joined.

The four wiring substrates 30 supplied to the base substrate 41 are positioned so that the electrodes 34 formed on both ends of the holding portion 32 overlap in the vertical direction. As shown in FIG. 4A, the solder 44 supplied in advance to the connection lands 42 of the base substrate 41 faces the positions of the electrodes 34 of the four wiring boards 30 that have been positioned. That is, the solder 44 is positioned such that a part thereof enters the through hole 34 a of the electrode 34.

Next, as shown in FIG. 3B, the heater tool 46 is pressed against the electrode 34 of the uppermost wiring substrate 30 which is superimposed, and pressure heating is performed. When the uppermost electrode 34 is pressurized, the holding portions 32 of the respective wiring boards 30 and the semiconductor chips 36 mounted on the holding portions 32 are formed.
The electrodes 34 of the respective wiring boards 30 come into close contact with each other while bending.

As a result, the heat from the heater tool 46 is transmitted to the solder 44 via the electrode 34 and the connection land 42 of the base substrate 41 which are in contact with each other.
4 is heated and melted.

FIG. 3C and FIG.
As shown in FIG. 4B, the fillet is formed by flowing upward from below along the through-holes 34a of the four electrodes 34 which are in close contact, and these electrodes 34 and the connection lands 42 are electrically connected and fixed. .

According to the stacked semiconductor device thus constructed, the wiring boards 30 of the respective semiconductor devices 31 are stacked on the base substrate 41, and the electrodes 34 formed at the ends of the wiring boards 30 are connected to the heater tool. By heating under pressure at 46,
The paste-like solder 44 supplied to the connection lands 42 of the base substrate 41 is melted, and the electrodes 34 of the respective wiring boards 30 can be fixed to the connection lands 42 in an electrically connected state. Therefore, not only can the manufacturing of the stacked semiconductor device be facilitated, but also the cost is advantageous.

The electrodes 34 of the four wiring boards 30 are
Soldering can be reliably performed on the connection lands 42 of the base substrate 41 in a superposed state. Therefore, since the area of the connection land 42 does not need to be increased, it is possible to cope with the reduction in the size and the pitch of the stacked semiconductor device.

Further, while supplying the solder 44 to the base substrate 41, the electrodes 34 of the respective wiring boards 30 are vertically joined, and the uppermost electrode 34 is heated while being pressed by the heater tool 46.

Thus, the solder 44 supplied on the connection lands 42 is melted by the heat transmitted through the respective electrodes 34. That is, the electrodes 34 of the stacked wiring boards 30 can be soldered without heating the wiring boards 30 in a reflow furnace.

Therefore, there is no occurrence of warpage of the wiring board 30 and no occurrence of connection failure between the semiconductor chip 36 and the wiring pattern 33, so that the stability and reliability of the manufacturing process can be ensured.

The holding portion 32 of the wiring board 30 and the semiconductor chip 36 mounted on the holding portion 32 have flexibility that can be bent and deformed. Therefore, when the plurality of wiring boards 30 are overlapped and these electrodes 34 are pressurized and heated by the heater tool 46, the holding portion 32 and the semiconductor chip 36 are bent and deformed. Thus, the electrodes 34 of the four wiring boards 30 can be reliably pressed into contact with each other.

When the electrodes 34 of each wiring board 30 are pressed against each other,
The heat of the heater tool 46 is reliably transmitted to the solder 44 provided on the connection land 42 through the electrode 34 and the connection land 42 of the base substrate 41. Therefore, the solder 44
Can be quickly melted, and the electrodes 34 can be connected and fixed.

FIGS. 7A and 7B show a second embodiment showing a modification of the first embodiment. In the second embodiment, the solder 44 supplied to the connection land 42 of the base substrate 41 is formed in a ball shape instead of a paste shape.

The ball-shaped solder 44 supplied to the connection land 42 is held by a flux (not shown). The base substrate 41 is passed through a reflow furnace and heated to be formed into a ball bump and fixed to the connection land 42. You may make it do.

The base substrate 41 is made of glass epoxy resin or the like, and is not made of a soft material like the holding portion 32 of the wiring substrate 30. There is no.

Even if the solder 44 provided on the connection land 42 of the base substrate 41 is in a ball shape, the electrodes 34 of the wiring substrate 30 are heated and pressed by the heater tool 46 as shown in FIG.
As shown in (b), fillets are formed by flowing along the four electrodes 34 stacked, and the four wiring substrates 30 are physically connected to the connection lands 42 of the base substrate 41 and electrically connected. Can be connected. In the case of the ball-shaped solder 44, the heating temperature by the heater tool 46 is about 2
About 50 ° C. is preferable.

In the first and second embodiments,
By supplying the flux to the electrodes 34 and the connection lands 42 of the base substrate 41, the wettability of the solder can be increased.

FIGS. 8A to 8C and FIGS. 9A and 9
(B) shows a third embodiment of the present invention. This embodiment differs from the first embodiment in the electrodes formed on the wiring substrate 30A of the semiconductor device 31A. That is, as shown in FIGS. 9A and 9B, the electrode 134 of this embodiment is provided on one surface of the holding portion 32, that is, the semiconductor chip 36.
Are provided only on the surface on which the wiring pattern 33 is formed.

More specifically, a semicircular concave portion 35 (a cutout portion) opened at the end surface is formed at the end of the holding portion 32.
The electrode 134 formed of a metal such as copper is
Along one side of the recess 35 and around the recess 35
It is provided to protrude inside.

The configuration of the other parts of the wiring board 30A is the same as that of the first embodiment, including the material and dimensions, and the description is omitted.

FIGS. 8A to 8C show the electrode 1 having the above-described structure.
The four wiring boards 30 </ b> A on which are formed the base board 4.
1 shows a procedure for stacking and fixing. The connection lands 42 formed on the base substrate 41 are partially covered with a resist 51, and solder 44 is supplied in advance to the exposed portions of the connection lands 42.

The solder 44 is supplied in the form of a ball to the connection land 42, and the base substrate 41 is passed through a reflow furnace to form a ball bump and fixed to the connection land 42, or a solder paste is printed on the connection land 42. After the supply, the base substrate 41 may be passed through a reflow furnace and fixed in a ball bump shape. Further, the solder 44 may remain in a ball shape or a paste shape without passing the base substrate 41 through a reflow furnace.

As shown in FIG. 8A, four semiconductor devices 31A are sequentially positioned and supplied in a predetermined state on the base substrate 41 to which the solder 44 has been supplied to the connection lands 42. That is, the wiring board 30A of each semiconductor device 31A
Is the solder 44 provided with the electrode 134 on the connection land 42.
Is supplied in a state corresponding to.

Next, as shown in FIG. 8B, the end of the uppermost wiring board 30A on which the electrodes 134 are formed is heated at a temperature of 230 to 250 ° C. while being pressed by the heater tool 46. Thereby, the heat of the heater tool 46 is transmitted to the solder 44 supplied to the connection land 42 via the electrode 134 of the wiring board 30A in close contact. Then, since the solder 44 is melted, the electrodes 134 of each wiring board 30A are electrically connected and fixed to the connection lands 42 of the base board 41 as shown in FIG.

The stacked semiconductor device in which the four semiconductor devices 31A are stacked has a thickness of 80 to 100 μm and a thickness of the wiring substrate 30A of each semiconductor device 31A. Has a very small thickness of about 600 μm.

According to the stacked semiconductor device having such a configuration, as in the first embodiment, it is possible to reliably manufacture the semiconductor device by a simple manufacturing process without causing defective products. Moreover, since the electrodes 134 are formed only on one surface of the holding portion 32, the cost can be reduced as compared with a case where electrodes are provided on both surfaces of the holding portion 32.

FIGS. 10 (a), 10 (b) to 12
(A) and FIG. 12 (b) show fourth to sixth embodiments in which electrodes 134a, 134b and 134c are formed on one surface of the holding portion 32.

In the fourth embodiment shown in FIGS. 10A and 10B, the electrode 134a is also provided on one surface of the holding portion 32 and the inner peripheral surface of the semicircular concave portion 35. This is different from the third embodiment in that Electrode 134a
Is provided on one surface of the holding portion 32 and the inner peripheral surface of the concave portion 35, so that the heat conductivity of the heater tool is improved, and when the solder 44 supplied to the base substrate 41 is melted, Since the connection area between the solder 44 and the electrode 134a is increased as compared with the third embodiment, the connection strength between the stacked plurality of wiring boards 30A and the connection lands 42 of the base board 41 can be improved.

The electrode 134b of the fifth embodiment shown in FIGS. 11A and 11B is formed in a semicircular shape larger than the semicircular concave portion 35 formed in the holding portion 32.
It is provided on one surface of the holding portion 32 so as to cover the concave portion 35.

The sixth embodiment shown in FIGS. 12 (a) and 12 (b) is similar to the fifth embodiment shown in FIGS. 11 (a) and 11 (b).
However, the difference is that a through hole 55 is formed in a portion of the electrode 134c that covers the concave portion 35. By forming a through hole 55 in a portion of the electrode 134c covering the recess 35, the solder 44 on the base substrate 41 is formed.
Is melted, the melted solder 44 easily flows upward through the through-hole 55, so that the plurality of stacked electrodes 13
4c can be reliably and firmly connected.

FIGS. 13A to 13C and FIG. 14 show a seventh embodiment of the present invention. As shown in FIG. 14, a rectangular electrode 23 continuous with a wiring pattern 33 is provided at an end of a holding portion 32 of a wiring board 30B of each semiconductor device 31B.
4 (shown in FIG. 14) are formed with a predetermined length. In addition, the concave portion 35 is not formed in the holding portion 32.

As shown in FIG. 13A, when four wiring boards 30B are stacked on the base board 41,
The holding portion 32 is punched so that the width B has a different length in the width direction. That is, as shown by cutting lines a to d in FIG.
The holding portion 32 of each wiring board 30B is connected to the electrode 23 so that the length of the electrode 234 of the wiring board 30B gradually increases in the order of being stacked on the base substrate 41 (d → c → b → a).
4 is punched.

As shown in FIG. 13A, the base substrate 4
A paste-like solder 44 is provided on one connection land 42 by means such as printing. This base substrate 41
On the top are four wiring boards 30 formed in different sizes.
The layers B are sequentially supplied in ascending order. Thereby,
The ends of the four wiring boards 30B where the electrodes 234 are formed are arranged stepwise so as to face the solder 44.

Next, as shown in FIG. 13 (b), the electrode 2 of the uppermost wiring board 30B is
The portion 34 is pressurized and heated. As a result, FIG.
Since the solder 44 is heated and melted as shown in (c), the electrodes 234 of each wiring board 30B facing the solder 44
Is electrically connected and fixed to the connection land 42 of the base substrate 41 by the solder 44.

In this embodiment, the connection land 42
Supplied to the connection land 42 may be in the form of a ball instead of a paste. Before being supplied to the connection land 42 and before the wiring board 30B is laminated, the base board 41 is passed through a reflow furnace to remove the solder 44. It may be configured to be melted, formed into a ball bump shape, and securely fixed to the connection land 42.

FIGS. 15, 16A and 16B show an eighth embodiment of the present invention. In this embodiment,
This is a modified example of the joint structure of four wiring boards 30C stacked on the base substrate 41.

That is, the electrode 3 provided at the end of the holding portion 32
Reference numeral 34 denotes a metal film 334a provided on one surface (lower surface) of the holding portion 32 on which the electrode 334 is formed.
3, a metal film 3 provided on the other surface (upper surface).
34b is a metal film 3 on one side via a through hole 61.
34a is electrically connected.

As shown in FIG. 16 (a), the metal films 334a and 334b on the upper and lower surfaces of the electrodes 334 of each wiring board 30C are each provided with a base metal layer 62 provided with a metal such as copper or nickel by plating. Is formed in a thickness of 20 to 40 μm, and a solder layer 63 is formed in a thickness of 10 to 20 μm on the base metal layer 62 by electrolytic plating.

As shown in FIG. 15, when four wiring boards 30C are stacked on the connection lands 42 of the base board 41, the electrode 334 of the uppermost wiring board 30C is connected to a heater tool (not shown). Pressure and heat.

As a result, each wiring board 30C is
Since the solder layer 63 between the laminated wiring boards 30C is melted and integrated as shown in FIG. 16B from the state shown in FIG. 6A, the four wiring boards 30C are connected to the base substrate 41. A metal film 334a below the electrode 334 on the land 42;
It is electrically connected and fixed via the through hole 61 and the upper metal film 334b.

When the four wiring boards 30C laminated by heating and melting the solder layer 63 are connected and fixed, as shown in FIG. 15, epoxy resin or the like is attached to the end of the holding section 32 where the electrode 334 is formed. The sealing member 64 is applied, and the sealing member 64 is cured at a temperature of, for example, 150 ° C. for 2 hours and sealed.

The electrode 3 of the holder 32 is sealed by the sealing member 64.
After the portion 34 is sealed, as shown in FIG. 15, a wiring 65 for connection to the outside provided on the lower surface of the base substrate 41.
Then, for example, a ball-shaped solder 66 having a diameter of 0.1 to 0.5 mm as a connecting member is attached with a flux or the like, and is placed in a reflow furnace and melted, so that the height is 0.05 to 0.5.
A solder ball bump of about mm is fixedly formed.

It should be noted that the connection wiring 65 on the lower surface of the base substrate 41 is not provided with ball bumps (solder 66), but the connection wiring of the circuit board (not shown) on which the semiconductor device is mounted is provided with solder. You may do so.

In the stacked semiconductor device having such a configuration, in order to connect and fix the four stacked wiring boards 30C,
Metal films 334 above and below electrodes 334 of each wiring board 30C
a, 334b are plated with a base metal layer 62 to a predetermined thickness, and then the solder layer 63 is formed on the base metal layer 62 by electrolytic plating.

Since the solder layer 63 is formed by electrolytic plating, it is not necessary to heat the wiring board 30C in a reflow furnace in order to fix the solder as in the related art. As a result, there is no occurrence of warpage of each wiring board 30C or impairment of the connection state of the semiconductor chip 36 to the wiring pattern 33.

Two wiring boards 30 arranged vertically
In the case where C is bonded and fixed by the solder layer 63, the semiconductor chip 36 is provided on the lower surface of the wiring substrate 30C located above in FIG. Therefore, conventionally, 2
The interval between the wiring boards 30C must be set so that the thickness of the solder layer 63 is large so that the semiconductor chip 36 can be interposed between the wiring boards 30C.

In this embodiment, the thickness of the portion of the wiring board 30C where the semiconductor chip 36 is mounted is 8
0 to 100 μm, the distance between the upper and lower wiring boards 30C is 100 to 160 μm, and
The semiconductor chip 36 is stored between 0C.

It is not easy to form the solder layer 63 thicker according to the thickness of the semiconductor chip 36 by electrolytic plating. However, in this embodiment, the base metal layer 62 is provided on the electrode 334, and the solder layer 6 is provided on the base metal layer 62.
3 is formed. Therefore, the solder layer 63
Can be made thinner than in the case where it is formed directly on the electrode 334, so that the wiring board 30C having the solder layer 63 can be easily manufactured.

FIGS. 17A and 17B show the eighth embodiment.
It is a ninth embodiment showing a modification of the embodiment.
In this embodiment, the electrode 3 formed on the wiring board 30C is used.
34, the underlying metal layer 62a is formed only on the metal film 334a on the lower side.
Is provided in a thickness of 40 to 80 μm.
10 and the metal film 334b on the upper side of the electrode 334, respectively.
The solder layer 63 was provided with a thickness of about 20 μm.

By pressing and heating the electrode 334 portion of the laminated wiring board 30C with the heater tool 46, the solder layer 63 interposed between the wiring boards 30C is changed from the state shown in FIG. 17A to the state shown in FIG. Melt as shown in). Thereby, the four laminated wiring boards 30C can be joined and fixed.

According to this structure, as in the eighth embodiment, the wiring board 30 is fixed to fix the solder.
Since it is not necessary to heat C by passing it through a reflow furnace, there is no possibility that the wiring board 30C is warped or that the connection of the semiconductor chip 36 to the wiring board 30C is not defective. Further, by providing the base metal layer 62a, the thickness of the solder layer 63 can be reduced accordingly, so that the wiring board 3
This makes it possible to easily manufacture the OC.

FIG. 18 shows a tenth embodiment of the present invention. This embodiment is a modification of the eighth embodiment, in which metal films 334a and 334 above and below an electrode 334 are provided.
b, a base metal layer 62 is provided. The base metal layer 62 is formed by plating a metal such as copper or nickel with a thickness of 30 to 50 μm.

A paste-like or film-like anisotropic conductive member 67 in which conductive particles 67b such as nickel or gold are mixed into an epoxy resin 67a is provided between the base metal layers 62 of the pair of upper and lower wiring boards 30C. Intervene.

Then, by pressing and heating the electrodes 334 of the laminated wiring boards 30C, the conductive particles 67b of the anisotropic conductive member 67 form a pair of upper and lower wiring boards 3C.
The electrode 334 of 0C is electrically connected and fixed.

According to such a configuration, the pair of upper and lower electrodes 334 can be electrically connected and fixed without using solder.
As in the eighth embodiment, the wiring substrate 30C does not need to be passed through a reflow furnace. Therefore, the wiring board 30C may be warped, or the semiconductor chip 3
6 can be prevented from causing a connection failure.

FIG. 19 shows an eleventh embodiment of the present invention. This embodiment is a modification of the tenth embodiment, and differs from the tenth embodiment in that each wiring board 30C of a plurality of semiconductor devices 31C is provided.
Are laminated to form the electrodes 3 of the pair of upper and lower wiring boards 30C.
The base metal layers 62 formed on the upper and lower surfaces of the base metal are bonded.

The joined base metal layers 62 are bonded by an adhesive 68 that contracts when cured, for example, an adhesive 68 such as an epoxy resin. Thereby, the adhesive 68
Thus, the pair of base metal layers 62 to be joined by the contraction force can be securely joined and fixed.

In the eighth to eleventh embodiments, the case where a plurality of semiconductor devices 31C are stacked on the base substrate 41 has been described. However, in these embodiments, the base device is similar to the first embodiment. Since it is not necessary to supply the solder 44 on the substrate 41 in advance, the plurality of semiconductor devices 31C can be stacked and fixed without using the base substrate 41.

FIG. 20 shows a twelfth embodiment of the present invention. This embodiment is a modification of the eighth embodiment shown in FIG. That is, in the eighth embodiment, the portion of the electrode 334 of the laminated wiring board 30C is
In this embodiment, the sealing member 6 is used.
4 instead of sealing the semiconductor device 31
C is sealed by covering it with a container-shaped metal cap 71. The metal cap 71 is fixed to the base substrate 41 by means such as soldering or bonding.

The uppermost wiring board 30 C is pressed and held by the elastic member 72. Thereby, the metal cap 7
1, the semiconductor device 31C can be held in a stable state.

In the first to twelfth embodiments, the number of wiring substrates stacked on the base substrate is not limited to four, and may be any number as long as it is plural.

In the eighth to twelfth embodiments, even if the holding member of the wiring board and the semiconductor chip held by the holding member do not have flexibility, a plurality of wiring boards are stacked and fixed. Above, there is no particular problem.

FIGS. 21 to 24A and 24B show a thirteenth embodiment of the present invention.

FIG. 23A shows a base member 201 made of a carrier tape for punching out a holding portion 32 of a TCP (Tape Carrier Package) 31D as the semiconductor device shown in FIG. Device holes 203 are formed in the base member 201. As shown in FIGS. 21 and 23 (b), a semiconductor chip 36 is provided on the inner lead 214 protruding from the device hole 203 of the wiring 204 (shown in FIG. 21) with a bump 36a as an internal electrode fixed thereto. The semiconductor chip 36 mounted on the base member 201 is sealed with a resin (not shown).

The base member 201 is formed as shown in FIG.
A portion indicated by a chain line L in FIG. 3B is punched out by press working. Thus, the TCP 31D in which the semiconductor chip 36 is mounted on the wiring board 30 shown in FIG. 21 is formed. Then, the four TCs shown in FIG.
By stacking and integrating P31D by the method described in the first embodiment, the stacked semiconductor device 207 shown in FIG.
Is formed.

As a result, the superposed electrodes 34 on both sides of each TCP 31D are electrically connected and fixed by soldering. Although FIG. 22B does not show that a plurality of joined TCPs 31D are provided on the base substrate 41 as in the first embodiment,
P31D may be laminated on a base substrate (not shown),
Alternatively, the eighth substrate shown in FIGS.
Alternatively, the layers may be stacked by the method of the eleventh embodiment.

When the TCP 31D is punched from the base member 201, a specific semiconductor chip 36 of the stacked semiconductor device 207 can be accessed from the outside by a combination of cutting and non-cutting of the two wirings 204. I have.

The wiring 204 is cut by the base member 201.
When the holding portion 32 is punched from the above, it can be performed at the same time. That is, as shown in FIG.
The two wirings 204 connected to the electrodes 34x and 34y as chip selection terminals for detecting cutting and non-cutting of a part of the intermediate parts 204x and 204y when the wiring 204 is formed on the base member 201 by printing. Is the base member 201
It is formed so as to be located at one end edge, which is the peripheral edge of the holding portion 32 punched from the substrate.

Wiring 204 connected to one electrode 34x
The middle portion 204x is formed on one surface of the holding portion 32, and the middle portion 204y of the wiring 204 connected to the other electrode 34y is provided on the other surface of the holding portion 32.
One end and the other end of the intermediate portion 204y of the wiring 204 are electrically connected to the wiring 204 provided on one surface by through holes 221.

The middle portion 204x, 20 of the two wirings 204
4y are provided on one surface and the other surface of the holding portion 32, so that the intermediate portions 204x,
04y in a state where they do not electrically interfere with each other.
2 can be provided at one edge.

The middle part 204x, 204 of the wiring 204
The cutting and non-cutting of the base member 2 are performed by pressing.
When the holding portion 32 is punched from the sheet No. 01 in FIG.
The cutting and non-cutting of the middle portions 204x and 204y of the two wirings 204 provided at one edge of the holding portion 32 are selected by selecting the punching of the semicircular portions indicated by X and Y in FIG. Can be.

That is, as shown in FIG. 22 (a), if the X and Y portions are not punched, the two wirings 204 are not cut. If either X or Y is punched, the holding portion is not cut. One of the two wirings 204 is cut by the X-groove 250 or the Y-groove 260 as a cutting portion opened at one end of the wire 32. Furthermore, if both X and Y are punched, the middle portions 204x and 204y of the two wirings 204 are cut by the X groove 250 and the Y groove 260.

The middle part of the two wires 204 is provided at one edge of the holding portion 32 punched from the base member 201. Therefore, the holding member 32
It is possible to cope with this by slightly changing the shape of the die of the press working device for punching the groove so that the X groove 250 or the Y groove 260 can be punched.

That is, the X-groove 250 and the Y-groove 260 are selectively formed at one edge of the holding portion 32 at the same time as the punching of the holding portion 32 without complicating the mold. Can be.

The four TCP3s thus formed
1D is stacked and integrated as shown in FIG. 22B to form a stacked semiconductor device 207. The stacked semiconductor device 207 is mounted and fixed in a concave portion 320 formed in a substrate 310 of the semiconductor storage medium 300 as shown in FIGS. 24A and 24B, and its electrodes 34 and terminals 330 provided on the substrate 310 are connected. By being electrically connected, the semiconductor storage medium 300 is obtained. Although not shown, the stacked semiconductor device 207 mounted on the substrate 310 is sealed with a resin.

As described above, the middle portion 204x of the two wirings 204 connected to the two electrodes 34x and 34y for selecting a specific semiconductor chip 36 among the plurality of semiconductor chips 36 by external access. , 204yb
Is formed on one edge of the holding portion 32 punched from the base member 201.

Therefore, the cutting of at least one of the intermediate portions 204x and 204y of the two wirings 204 is performed by the holding portion 32.
Can be performed at the same time as punching, so that the productivity can be improved as compared with the case where the wiring 204 is cut in a separate step.

Since the wiring 204 is cut by the X-groove 250 and the Y-groove 260, portions cut out to form these grooves (this portion is shown in FIG.
B (indicated by 350) is integrated with the base member 201.

Therefore, as in the case where the wiring is cut by circular punching as in the prior art, each of the concave grooves 25 is cut.
Since cutting chips are not generated by processing 0 and 260, it is not necessary to perform the processing of the chips after pressing.

The middle portion 204x of the wiring 204 to be cut,
As shown in FIG. 21, the holding member 204y is provided separately on one side surface and the other side surface of the holding portion 32. Therefore, when cutting the middle part 204x or 204y of one wiring 204, the middle part 204x or 204b of these two wirings is held without cutting the middle part 204x or 204b of the other wiring 204. 32 at one end.

When the stacked semiconductor device 207 is formed by stacking five or more TCPs 31D, three or more electrodes for chip selection are provided, and these electrodes are connected to the semiconductor chip. There are also three or more wires.
In this case, by providing the middle part of each wiring not only at one end edge of the holding part 32 but also at the other end part, it becomes possible to cut the middle part of each wiring simultaneously with the punching of the holding part 32. .

In the thirteenth embodiment, as the semiconductor device, the TCP in which the wiring board is formed of a resin film is exemplified. However, the wiring board is not limited to the resin film.
If it is made of a material that can be pressed,
This invention can be applied.

FIGS. 25 to 27 show a fourteenth embodiment of the present invention. The present embodiment aims at a heat radiation effect when a laminated structure is formed, and suppresses a malfunction that occurs when the temperature of the package rises. FIGS. 25A to 25C show a method of manufacturing the wiring board 401 of the present invention. In FIG. 25A, a wiring substrate 401 is a holding member made of a flexible electrically insulating synthetic resin sheet such as a sheet-like polyimide having a thickness of 25 μm. On this wiring board 401, a wiring pattern 402 of 12 μm copper or the like and φ
An external connection land 403 having a size of 500 μm is formed. At this time, the connection lands 403 to the outside are formed by electrically connecting the opposing positions on both surfaces of the wiring board 401 via the through holes 404. Wiring pattern 4
02, for example, a film 405 of 18 μm copper or the like.
And a connection terminal 406 with the outside having a size of φ1 mm. At this time, the connection terminals 406 with the outside are formed at positions facing each other on both surfaces of the wiring board 401 via the through holes 407.

Next, copper having a thickness of, for example, 20 to 40 μm is plated only on the connection lands 403 and the connection terminals with the outside.
Nickel or the like is formed by a plating method. Further, a solder layer 408 having a thickness of 10 to 20 μm is formed by a plating method or the like.

Next, as shown in FIG. 25B, a semiconductor chip 409 is mounted on a desired wiring pattern of the wiring board formed as described above. This semiconductor chip 409
Has a thickness of, for example, 50 μm, and is connected to the wiring pattern 402 by a flip chip via a bump 409 a made of gold or the like having a height of 10 to 30 μm. A semiconductor chip having a thickness of 50 μm is extremely thin as compared with a conventional one. Thereby, this semiconductor chip 409
Has flexibility that can be bent and deformed.

As shown in FIG. 25C, the semiconductor chip 409 is flip-chip connected by interposing an anisotropic conductive member 410 in which conductive particles are dispersed in a resin between the wiring board 401 and the semiconductor chip 409. Thermocompression bonding at a temperature of about Thus, the semiconductor chip 409 is electrically connected to the wiring pattern 402, and the surface facing the wiring substrate 401 and the outer peripheral surface are sealed.

Next, a procedure for forming a semiconductor device by laminating a plurality of wiring boards 401 thus manufactured, in this embodiment, four wiring boards 402 on a base substrate 411 as shown in FIG. Will be described. The base substrate 411
Is formed of an electrically insulating material such as a glass epoxy resin, and connection lands 412 as base electrodes are formed at both ends of the upper surface by a metal such as copper. The connection land 412 is electrically connected to a wiring pattern 413 formed on the lower surface of the base via a through hole (not shown). Further, four wiring substrates 401 are supplied on the base substrate 411 by a mount tool (not shown). The four wiring boards 401 supplied to the base board 411 are positioned so that the connection lands 403 and the connection terminals 406 formed at both ends thereof are aligned in the vertical direction. Note that, for example, a high thermal conductive paste 415 is interposed between the four wiring boards 401. Thereby, the back surface of the chip 409 and the metal film 405
Are thermally connected. In addition, the high thermal conductive paste 4
15, the back surface of the chip 409 and the metal film 4
There is no problem if 05 is thermally connected.

Next, the connection lands 403 and the connection terminals 406 of the superposed wiring board 401 are pressed against a heater tool (not shown) to perform pressure heating. When the connection land 403 and the connection terminal 406 are pressurized,
Each wiring board 401 contacts. Thereby, the heat from the heater tool is transmitted to the solder layer 408 via the connection land 403 and the connection terminal 406, so that the solder layer 40
8 is heated and melted to form solder balls.
03 can be electrically connected and the connection terminal 406 can be fixed in a thermally connected state.

Next, as shown in FIG. 27, for example, the semiconductor packages stacked and connected by a metal cap 418 are sealed. At this time, the cap and the metal film 405 of the uppermost package are thermally connected via, for example, the high thermal conductive paste 419.

After sealing, solder on a ball having a diameter of, for example, 0.1 to 0.5 mm is attached as a connection member to the external connection wiring 413 provided on the lower surface of the base substrate 411 with a flux or the like. The solder ball bump 420 having a height of about 0.05 to 0.5 mm is fixedly formed by welding in a reflow furnace.

It is also possible to provide solder on the connection wiring of the circuit board on which the semiconductor device is mounted, without providing the connection wiring with balls on the lower surface of the base substrate.

The thickness of the semiconductor package stacked and connected by the above configuration is 80 to 100 μm for the semiconductor element mounting portion.
The gap between the respective wiring boards is 100 to 160 μm, and the lamination connection is performed with the semiconductor element 409 stored in the gap between the respective wiring boards 401.

Accordingly, each semiconductor chip 40
9 and the external cap 418 are thermally connected, and the heat generated from each semiconductor chip 409 is radiated to the outside, so that malfunction due to heat can be prevented.

FIG. 28 shows a fifteenth embodiment of the present invention, which is a modification of the fourteenth embodiment. In this embodiment, the semiconductor packages stacked in the fourteenth embodiment are sealed with, for example, an epoxy resin 421 or the like. After sealing, the cooling efficiency can be increased by attaching, for example, a cooling plate 422 to the uppermost metal film.

According to the fourteenth and fifteenth embodiments, the heat generated from each semiconductor element can be efficiently dissipated, and malfunction of the semiconductor element due to a rise in temperature can be prevented.

[0142]

As described above, according to the present invention, not only can a plurality of wiring boards be laminated and fixed on a base substrate by a simple process, but also the wiring boards can be soldered without being passed through a reflow furnace and heated. Since the wiring board can be fixed, it is possible to prevent the wiring board from being warped or causing a connection failure of the semiconductor chip.

Further, when the wiring board is punched from the base member, the wiring connected to the chip selection terminal can be cut at the same time, so that the productivity is improved as compared with the case where the wiring is cut in another step. be able to.

[Brief description of the drawings]

FIG. 1A to FIG. 1C are explanatory views of a manufacturing procedure of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a perspective view of an electrode formed at an end of a wiring board.

FIGS. 3A to 3C are diagrams illustrating a process of stacking and fixing a plurality of semiconductor devices on a base substrate.

FIG. 4A is a perspective view showing a positional relationship between electrodes of a wiring board and paste solder supplied to connection lands of a base board, and FIG. 4B is a view showing electrodes connected and fixed by soldering; The perspective view of the state performed.

FIG. 5 is a flowchart showing a manufacturing process of the semiconductor device.

6 (a) to 6 (e) are schematic explanatory views of a manufacturing process of a semiconductor device.

FIG. 7A is a perspective view illustrating a positional relationship between a base substrate and a ball-shaped solder-supplied electrode according to a second embodiment of the present invention, and FIG. FIG. 2 is a perspective view of a state where electrodes are connected and fixed by the above.

FIGS. 8A to 8C are explanatory views of a step of laminating and fixing a plurality of semiconductor devices on a base substrate according to a third embodiment of the present invention.

FIGS. 9A and 9B are perspective views of electrodes formed on a wiring board.

FIGS. 10A and 10B are perspective views of an electrode formed on a wiring board according to a fourth embodiment of the present invention.

FIGS. 11A and 11B are perspective views of electrodes formed on a wiring board according to a fifth embodiment of the present invention.

FIGS. 12A and 12B are perspective views of electrodes formed on a wiring board according to a sixth embodiment of the present invention.

FIGS. 13A to 13C are explanatory views of a step of stacking and fixing a plurality of semiconductor devices on a base substrate according to a seventh embodiment of the present invention.

FIG. 14 is a plan view showing an electrode formed at an end of the wiring board.

FIG. 15 is a sectional view of a schematic configuration of a stacked semiconductor device according to an eighth embodiment of the present invention.

FIGS. 16A and 16B are enlarged cross-sectional views of electrode portions of a stacked semiconductor device.

17 (a) and 17 (b) are enlarged cross-sectional views of an electrode portion of a stacked semiconductor device according to a ninth embodiment of the present invention.

FIG. 18 is an enlarged cross-sectional view of an electrode portion of a stacked wiring board according to a tenth embodiment of the present invention.

FIG. 19 is an enlarged sectional view of an electrode portion of a stacked semiconductor device according to an eleventh embodiment of the present invention.

FIG. 20 is a sectional view of a schematic configuration of a stacked semiconductor device according to a twelfth embodiment of the present invention;

FIG. 21 is a plan view of a semiconductor device according to a thirteenth embodiment of the present invention.

FIG. 22A is an exploded perspective view of a plurality of stacked semiconductor devices, and FIG. 22B is a perspective view of a stacked semiconductor device.

23A is a plan view showing a part of a base member before a semiconductor chip is mounted, and FIG. 23B is a plan view showing a part of the base member on which a semiconductor chip is mounted.

24A is a plan view of a semiconductor memory device formed by mounting a semiconductor module, and FIG. 24B is a cross-sectional view of the semiconductor memory device.

FIGS. 25 (a) to 25 (c) are explanatory diagrams of a semiconductor device manufacturing procedure according to a fourteenth embodiment of the present invention.

FIG. 26 is a cross-sectional view illustrating a state in which a wiring substrate is stacked on a base substrate.

FIG. 27 is a sectional view of a schematic configuration of a stacked semiconductor device covered with a metal cap.

FIG. 28 is a sectional view of a schematic configuration of a stacked semiconductor device according to a fifteenth embodiment of the present invention;

FIG. 29 is a sectional view of a schematic configuration of a conventional stacked semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 30 ... Wiring board 31 ... Semiconductor device 33 ... Wiring pattern 34 ... External electrode 35 ... Recess 36 ... Semiconductor chip 41 ... Base substrate 42 ... Base electrode 44 ... Solder 55 ... Through hole

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification FI FI Theme Court ゛ (Reference) H01L 23/12 501 H01L 23/12 L 23/50 (72) Inventor Masayuki Arakawa 3-chome, Shinmachi, Ome City, Tokyo 3-1, Toshiba Digital Media Engineering Co., Ltd. In-house (72) Inventor Tomohiro Iguchi 33, Shinisogo-cho, Isogo-ku, Yokohama-shi, Kanagawa Pref. Toshiba Production Technology Center (72) Inventor Naoki Watanabe Isogo, Yokohama-shi, Kanagawa 33 Toshinba Production Technology Center, Shinisogo-ku, Ward (72) Inventor Yoshitoshi Fukuchi 33, Shinisogocho, Isogo-ku, Yokohama, Kanagawa, Japan Toshiba Production Technology Center (72) Inventor Tetsuro Komatsu Yokohama, Kanagawa 33F, Shinisogo-cho, Isogo-ku, Tokyo F-term in the Toshiba Production Technology Center (reference) 5F044 KK03 KK11 LL01 LL07 LL09 RR03 5F067 BC01

Claims (18)

[Claims] 1. A semiconductor chip having flexibility and internal electrodes provided thereon, and a wiring board having flexibility and provided with a wiring pattern electrically connected to the internal electrodes of the semiconductor chip. A semiconductor device comprising: an external electrode electrically connected to the wiring pattern and provided at an end of the wiring board. 2. A stacked semiconductor device in which a plurality of semiconductor devices are stacked on a base substrate, wherein the semiconductor device has flexibility and a semiconductor chip provided with internal electrodes, and has flexibility. A wiring board provided with a wiring pattern electrically connected to the internal electrode of the semiconductor chip; and an external electrode provided at an end of the wiring board and electrically connected to the wiring pattern. A base electrode provided on the base substrate, and a plurality of semiconductor devices being stacked on the base electrode of the base substrate with their external electrodes aligned with each other. A stacked semiconductor device comprising: a solder to which external electrodes are electrically connected and fixed. 3. An end portion of the wiring board is formed with an open recess at an end face thereof, and the external electrode of the wiring board is provided over both a peripheral surface of the recess and a plate surface on both sides of the wiring board. The stacked semiconductor device according to claim 2, wherein: 4. The wiring board according to claim 2, wherein the external electrodes are provided on one surface of the wiring board.
The stacked semiconductor device according to the above. 5. An end portion of the wiring board, wherein an open recess is formed at an end face thereof, and the external electrode of the wiring board is provided so as to close the recess. The stacked semiconductor device according to the above. 6. The stacked semiconductor device according to claim 5, wherein a through hole is formed in a portion of the external electrode of the wiring substrate which closes the concave portion. 7. A wiring board of a plurality of semiconductor devices to be stacked, wherein an external electrode of an upper wiring board protrudes outward from an external electrode of a lower wiring board. Item 3. The stacked semiconductor device according to Item 2. 8. A stacked semiconductor device in which a plurality of semiconductor devices are stacked, wherein the semiconductor device includes: a semiconductor chip provided with an internal electrode; and at least one plate surface electrically connected to the internal electrode of the semiconductor chip. A wiring board having a wiring pattern to be connected; and external electrodes provided on both plate surfaces of the wiring board and electrically connected to the wiring pattern, at least one of the external electrodes provided on the wiring board. When a plurality of semiconductor devices are stacked, a plurality of semiconductor devices are provided between opposed base metal layers between adjacent semiconductor devices or between a base metal layer and an external electrode. A stacked semiconductor device comprising: a connection member for electrically connecting and fixing the stacked semiconductor device. 9. The semiconductor device according to claim 8, further comprising a base substrate provided with a base electrode, wherein the plurality of semiconductor devices are stacked by electrically connecting external electrodes to the base electrode.
The stacked semiconductor device according to the above. 10. The stacked semiconductor device according to claim 8, wherein said connection member is a solder layer formed by electrolytic plating on at least one of said base metal layer and said external electrode. 11. The stacked semiconductor device according to claim 8, wherein said connection member is an anisotropic conductive member. 12. The stacked semiconductor device according to claim 8, wherein the connection member is an adhesive that shrinks during curing. 13. The stacked semiconductor device according to claim 8, wherein a heat transfer member is provided between the stacked semiconductor devices. 14. A method of manufacturing a stacked semiconductor device in which a plurality of semiconductor devices are stacked on a base substrate having a base electrode, a step of supplying a connection member that can be electrically connected and fixed to the base electrode; And a flexible semiconductor chip electrically connected to the wiring substrate, the external electrodes of the plurality of semiconductor devices being provided. A method of manufacturing a stacked semiconductor device, comprising: a step of aligning and laminating the external electrode with the base electrode; and a step of electrically connecting and fixing the aligned external electrode with the connecting member. 15. A stacked semiconductor device in which a plurality of semiconductor devices are formed by punching a wiring board provided with a semiconductor chip from a base member, wherein the plurality of semiconductor devices are provided on the wiring board and one end of which is connected to the semiconductor chip. The semiconductor chip is specified by the state of cutting and non-cutting of the wiring provided on the wiring substrate, the electrode connected to the other end of each of the wirings, and the wiring connected to the semiconductor chip among the electrodes. And a cutting portion formed at the outer peripheral end of the wiring substrate and opened to connect the chip selecting terminal and the semiconductor chip. . 16. The device according to claim 16, wherein the plurality of chip selection terminals are plural,
16. The semiconductor device according to claim 15, wherein at least a part of each wiring connecting each of the chip selection terminals and the semiconductor chip is provided on one surface and the other surface of a peripheral portion of the wiring board formed by punching. The stacked semiconductor device according to the above. 17. The stacked semiconductor device according to claim 15, wherein the cut portion is formed at the same time when the wiring substrate is punched from the frame member. 18. A method for manufacturing a stacked semiconductor device in which a plurality of semiconductor devices formed by punching a wiring board having wiring and electrodes provided with semiconductor chips from a base member are stacked, wherein the wiring substrate is formed from the base member. A step of punching, when punching the wiring board from the base member, at least one of the electrodes provided on the wiring board and connected to the semiconductor chip and the wiring, by cutting and uncutting the wiring. A step of simultaneously cutting the wiring and a step of stacking a plurality of semiconductor devices punched from the base member so as to serve as a chip selection terminal for specifying the semiconductor chip. Of manufacturing a semiconductor device.