JP2002050956A - Field programmable gate array - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the data structure from being intercepted upon reconfiguration of volatile FPGA. SOLUTION: For example, upon power source making, ciphered configuration data are fed to the input terminal of FPGA. In FPGA, the configuration data are first decoded by decoding algorithm embedded in the logic. This algorithm uses nonvolatile memory in FPGA, such as decoding key stored in an EEPROM, as an operand. The decoded configuration data are distributed to volatile function part in FPGA in conventional way. According to this design, even when the streams of configuration data which are transmitted from the external memory to FPGA upon reconfiguration are intercepted, the intercepting part can obtain only ciphered configuration data. Thus, this design can improve security, protecting intellectual property of commercial value and secret information, consisting of non-ciphered configuration data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

FIELD OF THE INVENTION The present invention relates to field programmable gate arrays, and in particular, but not exclusively, to:
The present invention relates to a volatile field programmable gate array.

[0002]

2. Description of the Related Art Field programmable gates
Arrays (FPGAs) include functional parts, including logical structures, whose configuration is programmable at the design stage to a state determined by configuration data specified for the application concerned and can be loaded into the FPGA. .

[0003] FPGAs based on volatile technology are widely used. Altera Corporation and Xi
Linx companies are active in this area. Such volatile FPGAs lose their configuration when power is removed. Thus, the volatile FPGA is reconfigured at power up by reloading the externally held configuration data. To perform this function, the volatile FPGA is equipped with circuitry to route the respective configuration data to the appropriate elements in the functional part of the FPGA.

When reloading configuration data at power up, it is relatively difficult to intercept the data stream between the external configuration data storage device and the FPGA and observe the configuration data as it is configured. It would be easy.
In addition, unauthorized reverse of programmed FPGAs
Engineering may also use the intercepted configuration data.

[0005] A first possibility would be to obtain unprogrammed FPGAs on the open market and program them with intercepted configuration data.

[0006] The second possibility is that an FPGA
Reverse engineer the design at the logical level,
And to manufacture an FPGA with a design programmed with intercepted configuration data or other configuration data. This is because the intercepted configuration data and the resulting FPGA
It becomes possible if the relationship with the configuration is known. The reverse is then used, for example, to use the unauthorized reverse engineering of the original FPGA logic as a starting point for another design or to hide that the design was obtained by reverse engineering from the original FPGA.・
Modifications can also be made to the engineered FPGA design.

A third possibility can be employed when the relationship between the configuration data and the resulting FPGA configuration is not known, but using slice and scan methods or other hardware cloning techniques. FPGA
Will be reverse engineered at the hardware level.

[0008] Thus, there is the potential for unauthorized duplication of commercially valuable configuration data that may have been produced after the original design work, possibly with a team of designers for a significant period of time. In addition, the use of configuration data obtained from unauthorized interception during the FPGA configuration process has the potential for unauthorized reverse engineering of the FPGA hardware at the logical level.

[0009]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a volatile field programmable gate array (FP).
When reconstructing the GA) after volatilization, the content of the configuration data sent from the outside should not be known even if it is intercepted.

[0010]

Certain preferred embodiments according to the present invention are set out in the accompanying independent and dependent claims. Features of the dependent claims may be combined with features of the independent claims as appropriate, in combinations other than those explicitly stated in the claims.

According to a first aspect of the present invention, the system is configured to receive encrypted configuration data, and upon decryption, acts on the encrypted configuration data received at power up, for example, to decrypt it. There is provided a field programmable gate array having decoding logic at its input side to perform the decoding. The decoded configuration data is then processed in a conventional manner in a field programmable gate array. That is, it is distributed so as to constitute the logical structure of the functional part of the field programmable gate array.

In one embodiment of the invention, the decoding logic is F
Access the decryption key stored in the PGA. The decryption algorithm then uses this key as an operand. Preferably, the decoding algorithm is stateful rather than stateless. Stateful algorithms use standard linear feedback shift
It can be implemented in hardware based on register (LFSR) design. Usually, the key memory is formed of a nonvolatile storage element, for example, an EEPROM, and the functional part of the gate array is formed of a volatile element, for example, an SRAM. The key size can typically be on the order of 1 kilobit or more. This size is
It is selected to provide the desired level of data security taking into account cracking techniques. For some applications, smaller sizes, eg, 64 bits, 12
Eight bits or even 256 bits may be suitable.

Since the key memory generally only forms a small portion of the FPGA as compared to the gate array of the functional portion of the FPGA, the key memory is implemented in relatively large feature size hardware that is advantageous for yield. can do.

According to a second aspect of the present invention, there is provided a method of processing field programmable gate array configuration data. The method includes inputting configuration data, encrypting the configuration data, and storing the encrypted configuration data in a configuration data memory or subsequently on an intermediate recording medium for loading into the configuration data memory. Including. The encryption can use an algorithm that utilizes an encryption key. The decryption key can be generated from the encryption key, which can then be embedded in the non-volatile memory of the field programmable gate array intended to provide the encrypted configuration data.

According to a third aspect of the present invention, there is provided a method for reconfiguring a field programmable gate array. The method inputs encrypted configuration data into a field programmable gate array,
Decrypting the encrypted configuration data and distributing the decrypted configuration data to configure the field programmable gate array. In this third aspect of the invention, the decrypting step comprises decrypting the encrypted configuration data using a decryption key stored in a non-volatile form within the field programmable gate array as an operand of the algorithm. It can include applying an algorithm. The decoding algorithm can be stateful or stateless.

According to a fourth aspect of the present invention, there is provided a field programmable gate array configurable in accordance with externally input encrypted configuration data. The gate array has a non-volatile storage element loaded with the decryption key, and is a data manipulation element that is part of the configuration data input channel, the data manipulation element passing through the input channel in response to the decryption key. There is also a data manipulation element configured to apply a decoding algorithm to the data.

Further, a field programmable gate array module can be provided, including a field programmable gate array and a non-volatile configuration data memory, the field programmable gate array and its memory. Are interconnected by a configuration data transfer link.

In an alternative embodiment of the invention, a configurable logic structure having a default state and configurable to a program state by configuration data, an input terminal for receiving encrypted configuration data, and a program state. A field programmable gate array including a data storage area for storing a set of configuration data for determining the encrypted configuration data received from the input terminal in a default state. And outputs the decoded configuration data to a data storage for subsequent reconfiguration of the configurable logic structure into a programmed state. The data storage may include a plurality of configuration data holding registers, to detect completion of decoding by the configurable logic structure, and
A state machine connected to trigger the data holding register to load the configuration data stored in the data storage into the configurable logic structure may also be provided.

Thus, according to the above embodiments and aspects of the present invention, both in terms of the logical structure designed by the FPGA manufacturer and the configuration data developed for a particular application by the FPGA application designer, It is possible to increase the security of intellectual property and confidential information incorporated in the FPGA design. A decoding or descrambling circuit is located inside the FPGA and operates on configuration data supplied to it from outside the FPGA. Therefore, the configuration data supplied to the FPGA is stored outside the FPGA in an encrypted form for an external circuit using the FPGA. Thus, obtaining configuration data, for example by intercepting while powering up the FPGA, will see the encrypted configuration data rather than the raw, unscrambled configuration data. Therefore, the task of establishing the relationship between the encrypted configuration data and the logic design of the FPGA can be made even more difficult. This is because the relationship is made less transparent by encryption. In addition, the same raw configuration data
Even when programmed into the PGA, different encryptions can be used for different FPGAs, thus making the conversion process of intercepted configuration data still difficult.

In one embodiment of the invention, the application designer is responsible for defining at least one aspect of the decryption process. In this embodiment, described further below, the designer defines a decryption key. The decryption algorithm that uses the key defined by the designer as the operand is predetermined by the FPGA manufacturer and is typically
It will be embedded in PGA hardware. The corresponding encryption key and encryption algorithm are also defined.
The corresponding encryption key and decryption key may be the same or different.

In one approach, the FPGA is provided with an input terminal through which the application designer can access the FPGA.
Key can be entered into a non-volatile memory in the device. In this embodiment, it is also preferred to provide a structure for disabling subsequent external access of the key to the non-volatile memory to prevent unauthorized access of the key later. For example, the key input can be manufactured to respond to a disable signal that, when received, is irreversible in the FPGA such that subsequent external communication to the decryption key is closed. Cause significant changes.

In another approach, there is no input terminal by which the application designer can externally program the non-volatile memory of the key. Instead, the application designer notifies the FPGA manufacturer of the desired key, and the manufacturer embeds the key as part of the manufacturing process.

The technique described first has the advantage of improving the security of key information that needs to be known only to the application designer. The second technique described is F
PGA has the advantage that it has no externally accessible channel in its non-volatile key memory.

After the application design is completed, the application designer is required to perform an operation of generating an encrypted configuration data set, that is, an operation of generating encrypted configuration data from raw unencrypted configuration data. Can be given. To this end, the application designer will use an encryption key corresponding to the aforementioned decryption key together with the design tool, which can be provided by the FPGA manufacturer, in which the PFGA is embedded. An encryption algorithm is programmed that includes the inverse function of the decryption algorithm. This design tool can be software or hardware based.

The configuration data is stored in an encrypted form,
It is also transferred to the FPGA in encrypted form during power-up, creating a barrier to reverse engineering. If cloning is attempted, the infringer needs to know how the encryption and decryption are configured, but obtaining this information from the FPGA would be extremely difficult. Reverse engineering of FPGA hardware can be made even more difficult by interspersing non-volatile storage elements used to store decoded data defined by the designer on the FPGA chips. Techniques for dispersing elements in this manner are known from the art of secure microcontroller design, where the ROM elements are dispersed or spatially interspersed, so that they are then automatically Do not form a regular and recognizable pattern that can be scanned.

The present invention will now be described, by way of example, with reference to the accompanying drawings, in order to better understand the invention and to show how the invention may be implemented.

[0027]

FIG. 1 shows a field programmable gate array (FPGA) 1 and a memory 4.
FIG. 4 is a schematic block diagram of an associated configuration data storage in the form of The FPGA 1 includes a functional part 3 including a programmable gate array structure. The programmable gate array structure includes, for example, an M × N array of configurable logic blocks (CLBs) (not shown). FPGA1 is
It is connected via a communication link 9 to the configuration data memory 4, which on the one hand
And the other end is connected to the input terminal of the FPGA 1.

FPGA 1 also includes logic 5 and memory 6
And a configuration data decoding circuit in the form of The decoding circuit applies a decoding process to the configuration data received via the communication link 10 extending between the input 8 and the input of the decoding circuit. The decoding circuit also includes an output terminal for outputting the decoded configuration data to the functional part 3 of the FPGA via the communication link 11 to form a functional part.

The memory 6 serves to store a decryption key,
Logic 5 is configured to apply the decryption algorithm to the configuration data using the decryption key as an operand of the algorithm. Key data defining the operands can be loaded from the memory 6 to the logic 5 via the communication link 16. The decryption key storage area 6 uses the EEPROM technology,
² It is formed of a nonvolatile element based on PROM technology. Alternatively, the nonvolatile element is a flash memory, a fusible link PROM, a UV-EPROM, an OTPR
It can be based on OM, ferroelectric cell, laser programmable fuse, or any other suitable technology that is compatible with the technology used elsewhere in FPGA1. Multiple combinations of technologies can be used in a single FPGA.

A decryption key can be loaded into the non-volatile decryption key storage area 6 through a decryption key input terminal 13 shown by a broken line in FIG. The FPGA 1 also includes a disabling element 14 in the form of a fusible switch, the purpose of which is to connect the decryption key input 13 to the decryption key storage 6 after the disabling element 14 is activated. It is to close external communication. The disabling element 14 is such that the receipt of a disabling signal that can be applied to the decryption key input terminal 13 causes an irreversible change in the disabling switch, and thereafter permanently opens the switch. ,
Responds to the disable signal. With this design, the application designer loads the decryption key into the decryption key storage 6, confirms that the decryption key was successfully loaded, and then outputs the disable signal to the input terminal 13 of the decryption key storage 6. To activate the disable element 14.

The functional part 3 of the FPGA 1 is formed by a volatile element based on the SRAM technology. The SRAM technology of the functional part 3 of the FPGA 1 is generally compatible with the EEPROM technology used for the nonvolatile decryption key storage 6. Alternatively, other techniques that meet the requirements for compatibility with other FPGA components, especially those used for the decryption key storage 6, can be used for the functional part 3.

To further increase the security, the non-volatile elements of the decryption key memory 6 are physically distributed among the volatile elements of the functional part 3 of the FPGA 1. This procedure makes the physical chip placement less susceptible to reverse engineering. FIG. 5 schematically shows a chip arrangement of each part of the FPGA 1, that is, the functional part 3, the decryption key storage area 6, and the decryption algorithm logic 5. The non-volatile elements of the decryption key storage area 6 are distributed over the chip arrangement between the volatile elements of the functional part 3. A programmable logic device having a plurality of safety bits distributed over the area of the configuration data memory block is a Ch
U.S. Pat. No. 5,349,249 assigned to Iang et al.
And the contents of which are incorporated herein by reference.

In order to design a system based on the FPGA, the application technician will prepare the configuration data for programming the functional part 3 of the FPGA 1 in a conventional manner. The designer then selects an encryption key and inputs the encryption key into an encryption algorithm that can be used by the designer as a design tool. Next, the designer encrypts the configuration data by applying an encryption algorithm using the encryption key specified by the designer. The encrypted configuration data is then stored by the designer in a configuration data storage 4 that can be incorporated into non-volatile memory or any other suitable recording medium. The generic encryption algorithm has the inverse function forming the decryption algorithm incorporated in the decryption algorithm logic 5 of the FPGA 1. The designer-designated encryption key also has a corresponding decryption key, which, again,
Linked by an inverse function, which can be an identity function, this decryption key is obtained by the FPGA 1 directly or by the manufacturer at the request of the designer, as described further above with reference to FIG. It is loaded into the decryption key storage area 6.

FIG. 2 illustrates, in flow chart form, a designer-led configuration data encryption process. The method includes step 20
To enter the configuration data set, then step 21
Proceed by applying an encryption algorithm 23 having the designer-specified encryption key 22 as an operand, described further above with reference to FIG. 1, to the configuration data set. Next, the encrypted configuration data set generated in step 21 is stored in a storage medium such as the configuration data storage area 4 and the intermediate storage medium shown in FIG. 1 in step 24.

FIG. 3 shows, in a schematic flow chart, storing a decryption key in the nonvolatile decryption key storage area 6 of the FPGA 1 under the initiative of the designer. This process comprises step 30
In step 31, a decryption key is generated from the encryption key in step 31, and the decryption key is written in the decryption key storage area 6 of the FPGA 1 in step 32, thereby proceeding.

FIG. 4 shows, in the form of a flowchart, a method for reconfiguring the FPGA 1 of FIG. 1 with the encrypted configuration data from the configuration data storage area 4. Reconfiguration is typically performed at power-on, but may be performed on-the-fly in some designs. At step 40, the encrypted configuration data is
A and then decrypted in step 41 by applying a decryption algorithm 43 to the encrypted configuration data. The decryption algorithm 43 uses the decryption key 42 stored in the decryption key storage area 6 of the FPGA 1. The decrypted configuration data is delivered to the functional part 3 of the FPGA 1 in step 44, thereby configuring the FPGA 1. The decoding algorithm 43 incorporated in the decoding algorithm logic 5 is stateful for further security, but may be stateless in less secure systems. The stateful decoding algorithm can be implemented in hardware using, for example, a linear feedback shift register design.

FIG. 6 shows an alternative embodiment of the present invention. The same reference numbers are used for parts having functions similar to those of the embodiment of FIG.

As in the previous embodiment, F interconnected via communication link 9, output terminal 7, and input terminal 8
1 shows a PGA 1 and an associated configuration data memory 4. F
PGA 1 also includes a key data memory 6 connected to communication link 16 to provide key data for decryption purposes.

In contrast to the previous embodiment, a decoding function is included in the functional part 3 of the FPGA and in the state machine 17 rather than with a dedicated decoding circuit. The state machine 17
It is configured to detect completion of decoding of the set of configuration data and to generate an output on a communication link 25 to the functional part 3 of the FPGA in response. The role of the state machine 17 will be more readily understood on reading the following discussion on the design of the functional part 3 of the FPGA.

FIG. 7 shows a modified design of the configurable logic block (CLB) 27 of the functional part 3 and the associated registers in more detail. The functional part 3 includes a plurality of CLBs therein, for example, a two-dimensional array of M × N. The CLB is configured to receive encrypted configuration data from communication link 10 and key data from communication link 16.

Associated with the CLB 27 of FIG. 7 is a set 18 of configuration registers. As in conventional FPGA designs, the configuration register set 18 serves to hold configuration data that, when loaded into the CLB 27, configures the CLB 27 according to that data.

However, in contrast to the conventional design, each CL
B also has a set 19 of holding registers. Referring to FIG. 7, the illustrated holding register set 19 serves to hold another set of configuration data. The holding register set 19 is connected to receive configuration data from the output terminal of the CLB 27 and load the configuration data stored therein into the configuration register set 18. FIG.
Although the connection between the register sets 18 and 19 is shown as a parallel connection, it may be a series connection. Holding register set 19 also has an input terminal for receiving a trigger signal from state machine via state machine communication link 25. In addition, the configuration register set 18
It also has an input terminal for receiving a global reset signal, and is designed to adopt a default state upon receiving a reset signal via this input terminal.

Configuration Register Set 1 in Default State
8 is loaded into CLB 27 when F
Operating the PGA as a decryption engine, the encrypted configuration data received over communication link 10 is thus decrypted according to the key data received over communication link 16 and output from CLB 27 in decrypted form. The data is supplied to the holding register set 19 and stored therein. Completion of the decoding process is detected by the state machine, and in response, the state machine outputs a signal on communication link 25. This signal is the holding register set 19
When received by the CLB, the contents of the holding register set 19, i.e., the decoded configuration data,
27, and then the CLB 27 changes state from its decoding engine state to the desired program state for conventional FPGA operation. A programmable logic device having a configuration memory capable of storing two sets of configuration data is disclosed in Randy T .; Ong
No. 5,426,378, which is incorporated herein by reference.

It should be understood that the embodiments of FIGS. 6 and 7 can be modified to include a decryption key input and a disable element, as further described with reference to FIG.

The alternative embodiment described above with reference to FIGS. 6 and 7 can also be implemented with a reduced number of devices to reduce chip area and provide additional decoding capabilities. This is achieved by designing the functional part 3 to adopt by default a decoding configuration in which the functional part 3 of the FPGA operates as a decoding engine.

As described above, a functional part having a configurable logical structure, an input terminal for receiving configuration data for configuring the functional part, and a decoding process applied to the configuration data to form a field programmable gate And means for generating decoded configuration data to configure functional portions of the array. It will be appreciated that a field programmable gate array can be provided. The decryption means can be composed of means for storing the decryption key and means for applying the decryption algorithm to the configuration data using the decryption key as an operand of the algorithm. In the conventional system, there is also a means for distributing the configuration data decrypted from the decrypting means to the functional part so as to constitute the functional part.

Having described certain embodiments of the invention, many modifications / additions and / or substitutions may be made without departing from the spirit and scope of the invention as defined in the appended claims. Please understand what you can do.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of a field programmable gate array and configuration data memory according to an embodiment of the present invention.

FIG. 2 is a flowchart illustrating a method of encrypting field programmable gate array configuration data.

FIG. 3 shows the field programmable gate of FIG.
5 is a flowchart illustrating a method for loading a decryption key into an array.

FIG. 4 is a flowchart illustrating a method of reconfiguring the field programmable gate array of FIG. 1 with decoded configuration data.

FIG. 5 shows the field programmable gate of FIG.
FIG. 3 is a diagram schematically illustrating a chip arrangement of parts of an array.

FIG. 6 is a schematic block diagram of a field programmable gate array and configuration data memory according to an alternative embodiment of the present invention.

FIG. 7 shows the field programmable gate of FIG.
FIG. 2 is a schematic block diagram of a configurable logic block (CLB) of an array and associated registers.

[Explanation of symbols]

1 Field Programmable Gate Array (F
PGA) 1 FPGA 3 Functional part 4 Memory 4 Configuration data storage area 4 Configuration data memory 5 Logic 6 Memory 6 Decryption key memory 6 Decryption key storage area 6 Non-volatile decryption key storage area 7 Output terminal 8 Input terminal 9 Communication link 10 Communication Link 11 Communication link 13 Decryption key input terminal 14 Disable element 16 Communication link 17 State machine 18 Configuration register set 19 Holding register set 22 Encryption key 23 Encryption algorithm 25 Communication link 25 State machine communication link 27 Configurable logic block (CLB) 27 CLB 42 decryption key 43 decryption algorithm

Continuation of front page (71) Applicant 591064003 901 SAN ANTONIO ROAD PALO ALTO, CA 94303, US A. (72) Inventor Paul Jeffrey Garnett, 129 British Columbia, 9 Piedab, Rue Mercyside Newton-Le-Willows, The Rookley, 2F Term (Reference) 5B076 FA02 5J042 BA11 CA21 DA00 5J104 AA01 AA16 EA04 NA02 NA23

Claims (23)

[Claims] 1. A function part having a configurable logical structure; (b) an input terminal for receiving configuration data forming the function part; and (c) an arrangement between the input terminal and the function part. And
A decoding circuit configured to apply a decoding process to the configuration data received at the input terminal and relay the decoded configuration data to a functional portion to configure the functional portion. Gate array. 2. The decryption circuit includes a decryption key storage area and decryption logic, and the decryption logic includes a decryption algorithm that can be applied to the configuration data using a decryption key that can be retrieved from the decryption key storage area as an operand of the algorithm. 2. The field programmable gate array of claim 1, wherein said array is embedded. 3. The field programmable storage device according to claim 2, wherein said decryption key storage area is formed by a nonvolatile element.
Gate array. 4. The method according to claim 1, wherein the non-volatile element is the field device.
4. The field programmable gate array according to claim 3, wherein the field programmable gate array is physically distributed among the programmable gate arrays. 5. The non-volatile element is an EEPROM element, a flash PROM element, a UV-EPROM element,
4. The field programmable gate array of claim 3, wherein the array is at least one of the group consisting of an OTPROM device, a fusible link PROM device, a ferroelectric cell, and a laser programmable fuse. 6. The field programmable gate array of claim 1, wherein said functional portion of said gate array is formed of volatile elements. 7. The field programmable gate according to claim 6, wherein said volatile element is an SRAM element.
array. 8. The field programmable gate array according to claim 1, wherein said decoding circuit is formed of a nonvolatile element, and said functional portion of said gate array is formed of a volatile element. 9. The field programmable gate array of claim 8, wherein said non-volatile elements are distributed between said volatile elements. 10. The field programmable gate array according to claim 2, wherein the decryption key storage area is formed of a non-volatile element, and the functional part of the gate array is formed of a volatile element. 11. The decryption key storage area is a non-volatile EEPROM.
2. The field programmable gate array of claim 1, wherein the field programmable gate array is formed of an OM device and the functional portion of the gate array is formed of a volatile SRAM device. 12. The field programmable gate array of claim 2, including a key input terminal for loading a decryption key into said decryption key storage. 13. An irreversible change is caused to the field programmable gate array to close subsequent external communication to the decryption key storage upon receipt of an externally applied disable signal. 13. The field programmable gate array of claim 12, including a disabling element constructed as such. 14. (a) inputting a configuration data set; (b) applying an encryption algorithm having a user-specified encryption key as an operand to the configuration data set; (c) recording medium Storing the encrypted configuration data on the field programmable gate array configuration data. 15. The method of claim 14, further comprising: (d) generating a decryption key from the encryption key; and (e) writing the decryption key to a non-volatile memory of the field programmable gate array. the method of. 16. An apparatus comprising: (a) inputting encrypted configuration data into a field programmable gate array; and (b) storing the encrypted configuration data in the field programmable gate array.
Decoding in a programmable gate array; and (c) distributing the decoded configuration data in the field programmable gate array to configure the field programmable gate array. , Field programmable gate
How to reconfigure the array. 17. The method as recited in claim 17, wherein the decrypting step comprises: decrypting the encrypted configuration data using a decryption key stored in a nonvolatile manner in the field programmable gate array as an operand of an algorithm. 17. The method according to claim 16, comprising applying a decoding algorithm. 18. The method of claim 17, wherein in step (b) the decoding algorithm is stateful. 19. A function part having a configurable logic structure, an input terminal for receiving the configuration data making up the function part, and a decoding process applied to the configuration data to provide the function of the field programmable gate array. Decoding means for generating decoded configuration data to cause the portion to be configured.
array. 20. The method according to claim 19, wherein said decryption means includes: means for storing a decryption key; and means for applying a decryption algorithm to said configuration data using said decryption key as an operand of the algorithm. Programmable gate array. 21. A configurable logic structure having an input terminal for receiving decoded configuration data and a default state, each of which is programmed into one of a plurality of program states defined by a set of decoded configuration data. A field programmable gate array comprising a configurable logic structure that is enabled and a data storage that stores a set of decoded configuration data defining one of the program states, wherein the configurable logic structure comprises: Decrypts, in the default state, the encrypted configuration data received at the input terminal, and subsequently reconfigures the configurable logical structure to a program state defined by the decrypted configuration data set A corresponding decoded configuration data set for storing the data in the data storage. Field-programmable gate array to be. 22. The field programming gate array of claim 21, wherein said data storage includes a plurality of configuration data holding registers. 23. Triggering the data storage to detect completion of decoding by the configurable logical structure and to load the configuration data stored in the data storage into the configurable logical structure. 22. The field programmable gate array of claim 21, including a state machine connected to reconfigure said configurable logic structure into a programmed state.