JP2002024311A - Method, device, and system for integrated circuit design, and computer-readable recording medium with program for executing this method by computer recorded thereon - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the efficiency of design verification and that of IP (intellectual property). SOLUTION: The system is provided with a verification algorithm generation part 4 and a function design verification part 5 which convert RTL description to a programmable logic and verify whether an algorithm and the RTL description are equivalent to each other or not on the basis of the algorithm and the programmable logic, and a logic design verification part 6 which designs the logic of an integrated circuit on the basis of the RTL description of which the equivalence to the algorithm has been verified by parts 4 and 5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for creating a specification corresponding to an algorithm describing a function of an integrated circuit as a design target, and creating an RTL description relating to the function of the integrated circuit from the created specification. In particular, the present invention relates to an integrated circuit design apparatus, an integrated circuit design system, an integrated circuit design method, and an integrated circuit design method capable of improving the efficiency of design verification and the efficiency of use of IP (design resources). The present invention relates to a computer-readable recording medium storing a program to be executed by a computer.

[0002]

2. Description of the Related Art Conventionally, integrated circuits (ICs) for a basic logic circuit in which 20 to 30 transistors are integrated on one chip.
Integrated circuit) has appeared, and LSI (Large-scale integrated circuit: Large Sca)
le Integrated circuit)
What is called a "system LSI" is becoming widespread.

[0003] The system LSI is an IC in which functions necessary for the system are integrated on a single chip as circuit blocks (memory, core, logic, middleware, etc.) with a CPU as a core, thereby enabling a system-like operation. Such a system LSI is commercialized through a design process of creating mask data of a chip based on a customer's purchase order and a manufacturing process of actually manufacturing a chip based on the mask data. .

Here, a system LSI in the prior art
The design procedure will be described. FIG. 8 is a flowchart showing a procedure for designing a system LSI according to the related art. As shown in the figure, the design of the system LSI in the conventional technique includes algorithm design / verification (step S801),
This is performed in the steps of specification creation (step S802), function design / verification by RTL description (step S803), logic design / verification (step S804), and layout design / verification (step S805). The following briefly describes each of these steps.

In general, a semiconductor manufacturer obtains an order form for a system from a customer (set maker) and starts designing a system LSI based on the order form. In this purchase order, the general description of the system, features, performance,
Target prices and other information have been disclosed. Then, first, the algorithm design / verification process (step S80)
As 1), based on the purchase order, an algorithm that describes the functions and operations of the system in a programming language such as C ++ or C is created, and it is verified whether the algorithm satisfies the contents of the purchase order.

Next, a specification creation process (step S80)
2) The whole system is divided into several functional modules (subsystems) based on the algorithm of the system.
The behavior model of the system divided into HDL and VH
Create a specification written in DL language or the like. Next, RT
Function design / verification process based on L description (step S80)
As 3), based on the specification of the HDL description of the behavior model, the function of the system LSI is changed to RTL (Register Tr
Ansfer Level) is created, and it is verified whether this RTL description satisfies the specifications of the specification. The RTL description is design data expressing functions and operations of the entire system by connecting circuits such as flip-flops and registers.

Next, the logic design / verification process (step S
In step 804), a netlist describing the logic circuit connection is created using a logic synthesis tool or the like based on the RTL description, and whether the netlist satisfies the specifications of the specification is re-verified. Next, as a layout design / verification step (step S805), based on the netlist, mask data in which each functional block composed of a logic circuit is arranged and wired on a silicon chip is created, and the wiring connection is designed. Verify that it is as expected. Then, the mask data is passed to the manufacturing process.

By the way, in the design of a system LSI, it takes a lot of time to newly design all circuits. Therefore, a design method for performing a function design using an IP (Intellectual Property) has appeared. . The design method utilizing this IP is based on the I
By reusing C, or by using ICs with excellent functions or ICs with standard functions owned by other companies or IP providers, it is possible to shorten the design period and reduce the design cost. Are a hardware IP (functional block) and a software IP (middleware). In general, IP is used for designing a system LSI, for example, when a semiconductor manufacturer discloses an algorithm or an IP provider discloses IP design data.

[0009]

However, the prior art described above requires a long design period because there is a limit in the efficiency of design verification and the use of IP (design assets) in the design of a system LSI. There was a problem.

That is, while the design of an algorithm is performed at a high level of abstraction, the design of a function based on an RTL description is performed with consideration given to a specific circuit configuration. It largely depends on experience and ability, and it is easy to make design mistakes for algorithms. However, in the above-described conventional technology, design verification between an algorithm and an RTL description is performed only through a specification. Therefore, at the stage of function design based on the RTL description, it is verified whether the RTL description is equivalent to the algorithm. I couldn't. Therefore, there is a limit in efficiently performing design verification, and it is not possible to sufficiently cope with shortening of the design period.

In order to sufficiently cope with the shortening of the design period, ICs developed in the past may be reused, ICs having excellent functions owned by other companies or IP providers, and ICs having standard functions may be used.
It is necessary to use IP efficiently, such as using C. However, in the above prior art, as described above, the RTL is described in the stage of the function design based on the RTL description.
Since it does not verify that the description is equivalent to the algorithm,
We could not guarantee that the procured IP would work correctly for the desired algorithm. For this reason, there is a limit in efficiently using the IP, and it is not possible to sufficiently cope with the shortening of the design period.

Further, in the design of a system LSI, it is premised that sufficient protection of intellectual property such as an algorithm owned by a semiconductor manufacturer and IP design data owned by an IP provider is provided. However, in the above-mentioned conventional technology, when using IP owned by an IP provider, it is necessary to disclose intellectual properties such as algorithms and IP design data to each other. It was necessary to take steps such as license negotiations.
For this reason, there is a limit to easily procure and efficiently use the IP, and it is not possible to sufficiently cope with the shortening of the design period.

Therefore, the present invention solves the above-mentioned problems of the prior art, and therefore, the efficiency of design verification and the IP
(Design resource) An integrated circuit design device, an integrated circuit design system, an integrated circuit design method, and a computer-readable recording medium storing a program for causing a computer to execute the method can be provided. With the goal.

[0014]

Means for Solving the Problems The above-mentioned problems are solved,
In order to achieve the object, an integrated circuit design apparatus according to the present invention creates a specification corresponding to an algorithm describing a function of an integrated circuit, which is a design target, and converts the created specification into a function of the integrated circuit. In the integrated circuit design apparatus for creating the RTL description and performing the logic design, the RTL
Verification for verifying whether the algorithm and the RTL description are equivalent based on the programmable logic conversion means for converting the description into programmable logic, and the algorithm and the programmable logic converted by the programmable logic conversion means. Means and logic design means for performing a logic design of the integrated circuit based on the RTL description verified to be equivalent by the verification means.

According to a second aspect of the present invention, in the integrated circuit design apparatus according to the second aspect, the verifying means performs a verification for making a predetermined modification to the algorithm to access the programmable logic. Verification algorithm creating means for creating an algorithm for use, and accessing the programmable logic using the verification algorithm created by the verification algorithm creating means, so that the programmable logic implements the function described in the algorithm. Determining means for determining whether or not the above is true.

According to a third aspect of the present invention, in the integrated circuit design apparatus according to the second aspect, the verification means includes an input / output for generating input data and output data relating to a function described in the algorithm. Data creation means,
The input data created by the input / output data creation unit is input to the programmable logic converted by the programmable logic conversion unit, and the output data output in response to the input data and the input / output data creation unit Comparing means for comparing whether or not the created output data matches.

According to a fourth aspect of the present invention, there is provided an integrated circuit designing apparatus as set forth in the first, second or third aspects.
The algorithm is described in an object-oriented language.

According to a fifth aspect of the present invention, there is provided an integrated circuit design system comprising: a first client for creating a specification corresponding to an algorithm describing a function of an integrated circuit as a design target; R related to the function of the circuit
Connecting to a network a second client that creates a TL description and a server that provides the specifications created by the first client to the second client;
In an integrated circuit design system for performing a logic design of the integrated circuit based on an RTL description created by the second client, the first client transmits the algorithm and the specification to the server by a first transmission. Means, first receiving means for receiving predetermined binary data from the server, and logic design means for performing a logic design of the integrated circuit based on the predetermined binary data received by the first receiving means. Prepared,
The second client creates a second receiving unit that receives the algorithm and the specification from the server, and creates an RTL description related to an integrated circuit function from the specification received by the second receiving unit. Programmable logic conversion means for converting the created RTL description into programmable logic, and verification for creating a verification algorithm for accessing the programmable logic by applying a predetermined modification to the algorithm received by the second receiving means Determining whether the programmable logic implements the function described in the algorithm by accessing the programmable logic using an algorithm creating unit and a verification algorithm created by the verification algorithm creating unit; Means and the determination means Therefore, a second transmission unit that creates binary data relating to the configuration of the programmable logic that is determined to realize the function and transmits the created binary data to the server, wherein the server is configured by the first transmission unit There is provided a publicizing unit for publicizing the transmitted algorithm, the specification transmitted by the first transmitting unit, and the binary data transmitted by the second transmitting unit.

According to a sixth aspect of the present invention, there is provided an integrated circuit design system comprising: a first client for creating a specification corresponding to an algorithm describing a function of an integrated circuit as a design target; R related to the function of the circuit
Connecting to a network a second client that creates a TL description and a server that provides the specifications created by the first client to the second client;
In an integrated circuit design system for performing a logic design of the integrated circuit based on an RTL description created by the second client, the first client converts input data and output data relating to a function described in the algorithm. Input / output data generating means for generating, input / output data generated by the input / output data generating means, first transmitting means for transmitting the specification to the server, and first receiving means for receiving predetermined binary data from the server Receiving means, and logic design means for performing a logic design of the integrated circuit based on the predetermined binary data received by the first receiving means, wherein the second client receives the input / output from the server Second receiving means for receiving the data and the specification, and receiving the data by the second receiving means. R of from specifications to the function of the integrated circuit
A programmable logic conversion means for creating a TL description and converting the created RTL description into programmable logic; and inputting input data received by the second receiving means to the programmable logic converted by the programmable logic conversion means. Comparing means for comparing whether output data output in response to the input data input and output data received by the second receiving means match, and when the output data matches by the comparing means, Second transmitting means for generating binary data relating to the verified configuration of the programmable logic, and transmitting the generated binary data to the server, wherein the server receives and outputs the input / output transmitted by the first transmitting means. Data, specifications transmitted by the first transmission means, Further comprising a public means to expose the transmitted binary data by the serial second transmission means and said.

According to a seventh aspect of the present invention, there is provided an integrated circuit design system according to the fifth or sixth aspect, wherein
The first client and the second client further include a protection unit for transmitting and receiving only specific data to and from the server.

According to an eighth aspect of the present invention, there is provided an integrated circuit designing method, wherein a specification corresponding to an algorithm describing a function of an integrated circuit, which is a design target, is created, and the function of the integrated circuit is created from the created specification. An integrated circuit design method for creating an RTL description and performing a logic design, comprising: a programmable logic conversion step of converting the RTL description into programmable logic; and The algorithm and the R
A verification step of verifying whether or not the TL description is equivalent;
A logic design step of performing a logic design of the integrated circuit based on the RTL description verified to be equivalent in the verification step.

According to a ninth aspect of the present invention, in the integrated circuit design method according to the eighth aspect, the verifying step includes verifying the algorithm to access the programmable logic by applying a predetermined modification to the algorithm. A verification algorithm creating step of creating a verification algorithm, and accessing the programmable logic using the verification algorithm created by the verification algorithm creation step, so that the programmable logic implements a function described in the algorithm. And a determining step of determining whether or not this is the case.

According to a tenth aspect of the present invention, in the integrated circuit designing method according to the eighth aspect, the verifying step includes an input / output for generating input data and output data relating to a function described in the algorithm. A data creation step, inputting the input data created by the input / output data creation step to the programmable logic converted by the programmable logic conversion step, and outputting the output data corresponding to the input data and the input data. And a comparing step of comparing whether the output data created by the output data creating step matches the output data.

An integrated circuit design method according to an eleventh aspect of the present invention is the integrated circuit design method according to the eighth, ninth or tenth aspect, wherein the algorithm is described in an object-oriented language.

According to a twelfth aspect of the present invention, there is provided an integrated circuit design method, comprising: a first client for creating a specification corresponding to an algorithm describing a function of an integrated circuit as a design target; RT related to circuit function
An LTL description created by the second client and a server that provides the specifications created by the first client to the second client are connected to a network, and an RTL description created by the second client is connected to the network. An integrated circuit design method for performing a logic design of the integrated circuit based on the first transmission step in which the first client transmits the algorithm and the specification to the server; A first publishing step of publishing the algorithm and the specification transmitted by the step, a first receiving step in which the second client receives the algorithm and the specification from the server, and a first receiving step An RTL description relating to the function of the integrated circuit is created from the specifications received in the process, and the created RT A programmable logic conversion step of converting the described programmable logic, said first
A verification algorithm creating step of creating a verification algorithm for accessing the programmable logic by adding a predetermined modification to the algorithm received by the receiving step, and a verification algorithm created by the verification algorithm creating step. A determination step of determining whether the programmable logic realizes the function described in the algorithm by accessing the programmable logic using the programmable logic, and a configuration of the programmable logic determined to realize the function by the determination step. A second transmitting step of creating binary data and transmitting the created binary data to the server; and a second publishing step of publishing the binary data transmitted by the second transmitting step, The first client is A second reception step of receiving the binary data from a server; and a logic design step of performing a logic design of the integrated circuit based on the binary data received by the second reception step. And

According to a thirteenth aspect of the present invention, there is provided an integrated circuit design method comprising: a first client for creating a specification corresponding to an algorithm describing a function of an integrated circuit as a design target; RT related to circuit function
An LTL description created by the second client and a server that provides the specifications created by the first client to the second client are connected to a network, and an RTL description created by the second client is connected to the network. An integrated circuit design method for performing a logical design of the integrated circuit based on the input / output data creating step in which the first client creates input data and output data related to a function described in the algorithm; A first transmission step of transmitting the input / output data and the specification created by the data creation step to the server, and the server publishing the input / output data and the specification transmitted by the first transmission step A first publishing step, wherein the second client sends the input / output data list from the server A first receiving step of receiving the specification, the creating an RTL description of the specification received by the first reception step to the function of the integrated circuit, and the generated R
A programmable logic conversion step of converting the TL description into a programmable logic; and inputting the input data received in the first receiving step to the programmable logic converted in the programmable logic conversion step, and corresponding to the input data. Comparing the output data outputted by the first receiving step with the output data received by the first receiving step; and comparing the binary data relating to the configuration of the programmable logic verified that the output data matches by the comparing step. A second transmitting step of creating data and transmitting the created binary data to the server; a second publishing step in which the server publishes the binary data transmitted by the second transmitting step; A first client sends the binary data from the server. A second reception step of receiving data, characterized in that it contains a logic design process for performing a logic design of the integrated circuit based on the binary data received by said second reception step.

According to a fourteenth aspect of the present invention, in the integrated circuit design method according to the twelfth or thirteenth aspect, the first client and the second client are specified between the first client and the second client. The method further comprises a protection step of transmitting and receiving only the data of (i).

According to a fifteenth aspect of the present invention, there is provided a recording medium on which a program for causing a computer to execute the method according to any one of the eighth to fourteenth aspects is machine-readable. Thereby, the operation of any one of claims 8 to 14 can be executed by a computer.

[0029]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS With reference to the accompanying drawings, an integrated circuit design apparatus, an integrated circuit design system,
Preferred embodiments of an integrated circuit design method and a computer-readable recording medium that records a program for causing a computer to execute the method will be described in detail. In this embodiment, a case where the present invention is applied to the design of a system LSI will be described. However, the present invention is not limited by the present embodiment. For example, any integrated circuit that performs a logic design based on an algorithm describing the function of an integrated circuit as a design target, such as an IC or an LSI for a basic circuit, may be used. It can be applied to circuit design.

In the first embodiment described below, a case will be described in which a verification design is performed using a verification algorithm. In a second embodiment, a case in which a verification design is performed between a network-connected IP (design asset) provider is described. In the third embodiment, a case where a verification design is performed using a verification algorithm will be described. In a third embodiment, a case where a verification design is performed using input / output data (test vector) of an algorithm will be described. In Section 4, a case will be described in which verification design is performed using input / output data of an algorithm with an IP provider connected to a network.

(Embodiment 1) First, the configuration of an integrated circuit design apparatus according to Embodiment 1 will be described.
FIG. 1 is a block diagram showing a configuration of an integrated circuit design device 1 according to the first embodiment. As shown in FIG. 1, the integrated circuit design device 1 according to the first embodiment includes an algorithm design verification unit 2, a system specification generation unit 3, a verification algorithm generation unit 4, a function design verification unit 5, A logic design verification unit 6 and a layout design verification unit 7 are provided.

Generally, in the integrated circuit design apparatus 1 according to the first embodiment, the function design verification unit 5 converts the RTL description into programmable logic, and the verification algorithm creation unit 4 converts the RTL description into a predetermined algorithm. A verification algorithm for accessing the programmable logic with modification is created, and the functional design verification unit 5
By accessing the programmable logic using the verification algorithm and determining whether or not this programmable logic realizes the function described in the algorithm, the R is described at the stage of the function design based on the RTL description.
This is to verify whether the TL description is equivalent to the algorithm.

Hereinafter, with reference to FIG. 1 and FIG. 2, the processing contents of each unit in the integrated circuit design apparatus 1 according to the first embodiment will be described. First, the algorithm design verification unit 2 shown in FIG. 1 describes the functions and operations of the system in C ++ based on an order form obtained from a customer (set maker).
A processing unit that creates an algorithm described in an object-oriented programming language such as C and C, and verifies whether the algorithm satisfies the contents of the purchase order. It should be noted that the order form generally clarifies the outline, function, performance, target price, and the like of the system.

Here, the algorithm can be designed not only by distinguishing between the functions implemented by hardware and the functions implemented by software, but also by design without distinguishing between them. Further, the functions to be realized can be designed by being divided from the highest level (unit) to the lowest level (unit). In the first embodiment,
Although the algorithm is described in an object-oriented language, the present invention is not limited to this.
It can also be described in a hardware description language such as L or VHDL.

The system specification creating unit 3 shown in FIG. 1 divides the behavior of the system into several functional modules (subsystems) based on the algorithm designed and verified by the algorithm design verifying unit 2. , A processing unit that creates specifications written in HDL, VHDL, or the like.

Specifically, the system specification creating section 3 takes into account the mechanical part, input / output hardware, and application software function sharing based on the algorithm, and provides functions to be assigned to the system LSI. The performance is determined, and the outline of the internal configuration of the LSI is determined while selecting the circuit block and software design assets and the application system method that have already been used. Then, the entire system is divided into several functional modules (sub systems), and a specification in which functional blocks are determined is created.

The verification algorithm creating section 4 shown in FIG.
Is a processing unit for creating a verification algorithm for accessing a programmable logic, which will be described later, by applying a predetermined modification to the algorithm designed and verified by the algorithm design verification unit 2 as verification algorithm generation means.

Here, a method of creating a verification algorithm by the verification algorithm creation unit 4 will be described. FIG.
FIG. 2 is an explanatory diagram for explaining a method of creating a verification algorithm by a verification algorithm creation unit 4 shown in FIG. 1. Specifically, FIG. An example of
FIG. 2B shows a verification algorithm created by adding a predetermined modification to this algorithm.

FIG. 2A shows an example in which the multiplication is realized by hardware in C ++.
+ Description class func is a unit realized by hardware. Then, as shown in FIG. 2B, a verification algorithm for accessing the programmable logic is created by changing the algorithm class func to func # FPGA. Note that FIG.
(B) shows a case where hardware access is described, but software access can also be described.

The function design verification section 5 shown in FIG. 1 includes an RTL description section 51, a programmable logic creation section 52, and a determination section 53, as shown in FIG.
Hereinafter, processing contents of each unit of the functional design verification unit 5 will be described.

The RTL description section 51 of the functional design verification section 5
Based on the specification of the HDL description of the behavior model, the function of the system LSI is changed to RTL (Register Transfer Level).
This is a processing unit that creates the design data described in l). The RTL description is design data expressing functions and operations of the entire system by connecting circuits such as flip-flops and registers. Further, the RTL description is made using IPs (design assets) such as hardware IPs (functional blocks) and software IPs (middleware). That is, ICs developed in the past can be reused or ICs with excellent functions owned by other companies or IP providers
Alternatively, an IC having a standard function can be used.

The programmable logic creating section 52 of the functional design verifying section 5 serves as a programmable logic converting means.
This is a processing unit that converts descriptions into programmable logic.

The determination unit 53 of the function design verification unit 5
As the determination means, using the verification algorithm created by the verification algorithm creation unit 4 to access the programmable logic created by the programmable logic creation unit 52, this programmable logic implements the function described in the algorithm. It is a processing unit that determines whether or not the processing is performed. When the determination unit 53 determines that the programmable logic realizes the function described in the algorithm, it is verified that the algorithm and the RTL description are equivalent. On the other hand, when it is determined not to be realized, a new RTL description is performed until it is determined that the realization is realized.

The logic design verifying unit 6 shown in FIG. 1 uses the RTL description (programmable logic) verified as equivalent to the algorithm by the determining unit 53 of the functional design verifying unit 5 as a logic design means. A processing unit that creates a netlist describing the logic circuit connection using a logic synthesis tool or the like, and re-verifies whether the netlist satisfies the specifications of the specification.

The layout design verification section 7 shown in FIG.
Based on the netlist created by the logic design verification unit 6, mask data is created by arranging and wiring each functional block composed of a logic circuit on a silicon chip, and it is checked whether the wiring connection is as designed. This is a processing unit to be verified. Then, the mask data is passed to the manufacturing process.

Next, a design processing procedure in the integrated circuit designing apparatus 1 according to the first embodiment configured as described above will be described. FIG. 3 is a flowchart showing a design processing procedure in the integrated circuit design device 1 according to the first embodiment. First, the algorithm design verification unit 2
The design verification of the algorithm is performed based on the purchase order (step S301), and the verification algorithm creation unit 3 creates a verification algorithm based on the algorithm (step S302).

Then, the system specification creating unit 3
A specification is created based on the algorithm (step S3
03), the RTL description unit 51 performs RTL description based on the specification (step S304), and the programmable logic creation unit 52 converts the RTL description into programmable logic (step S305).

Then, the determining unit 53 determines whether or not the programmable logic realizes the function described in the algorithm (step S306). An RTL description is made (step S304). On the other hand, when it is determined to be realized (Yes at Step S306),
A logical design is performed by the logical design verification unit 6 (step S307), and a layout design is performed by the layout design verification unit 7 (step S308).

As described above, in the first embodiment, the programmable logic creation unit 52 converts the RTL description described by the RTL description unit 51 into programmable logic, and the verification algorithm creation unit 4 executes the algorithm design. A verification algorithm for accessing the programmable logic is created by adding a predetermined modification to the algorithm designed and verified by the verification unit 2, and the determination unit 53 accesses the programmable logic using the verification algorithm and Since it is determined whether or not the logic realizes the function described in the algorithm, it is possible to verify whether the RTL description is equivalent to the algorithm at the stage of the function design based on the RTL description. For this reason, it is also possible to verify whether the procured IP functions correctly for the target algorithm. Therefore, the efficiency of design verification and the efficiency of IP utilization can be improved, and the design time can be reduced.

In the first embodiment, since the algorithm design verification unit 2 describes the algorithm in an object-oriented language, the behavior of the circuit (system) can be handled as a unit. For this reason, the operability of design can be improved.

(Embodiment 2) In Embodiment 2, an integrated circuit design system in which the integrated circuit design method described in Embodiment 1 is performed with an IP (design asset) provider connected to a network. Will be described. That is, the integrated circuit design system according to the second embodiment
A first client as a semiconductor maker that creates specifications corresponding to an algorithm describing the function of an integrated circuit, which is a design target, and RTL related to the functions of the integrated circuit from the specifications
A second client as an IP provider that creates a description and a WEB server that provides a specification created by the first client to the second client are connected to a network.

Generally, in the integrated circuit design system according to the second embodiment, a first client as a semiconductor maker transmits an algorithm and specifications to a second client as an IP provider via a WEB server. Then, the second client transmits binary data related to the configuration of the programmable logic for which the verification design has been performed using the verification algorithm to the first client via the WEB server, and the first client transmits the binary data based on the binary data. Logic design.

The configuration and processing of the first client as a semiconductor maker, the second client as an IP provider, and the WEB server in the integrated circuit design system according to the second embodiment will be briefly described below.

The first client creates an algorithm based on the purchase order, and verifies whether the algorithm satisfies the contents of the purchase order.
A system specification creation unit that creates system specifications based on algorithms, and WE for algorithms and specifications
b, a transmitting unit for transmitting to the server, a receiving unit for receiving predetermined binary data from the WEb server, a programmable logic creating unit for creating program logic based on the binary data, and a logic design based on the programmable logic. And a layout design verification unit for generating mask data based on the netlist.

Further, the second client includes: a receiving unit that receives the algorithm and the specification from the web server;
A programmable logic creating unit for creating an RTL description related to the function of the integrated circuit from the received specifications and converting the RTL description into programmable logic; and a program for accessing the programmable logic by adding a predetermined modification to the received algorithm. A verification algorithm creation unit that creates a verification algorithm; a determination unit that accesses the programmable logic using the verification algorithm to determine whether the programmable logic implements the function described in the algorithm; and a determination unit. A binary data creation unit that creates binary data related to the configuration of the programmable logic that is determined to realize the function by the function, and a transmission unit that sends the created binary data to the web server.

Further, the WEB server is provided with a publishing unit for publishing the algorithm and specifications transmitted from the first client and the binary data transmitted from the second client. Note that the first client and the second client each have a firewall as a protection means for transmitting and receiving only specific data to and from the WEB server.

Next, a design processing procedure in the integrated circuit design system according to the second embodiment configured as described above will be described. FIG. 4 is a sequence diagram showing a design processing procedure in the integrated circuit design system according to the second embodiment. First, the semiconductor maker verifies the design of the algorithm and creates a specification, and transmits the algorithm and the specification to the WEB server (step S40).
1 and step S402). The transmitted algorithm and specifications are made public on the server.

Then, the IP provider receives the algorithm from the web server and creates a verification algorithm (step S403). Further, the specification is received from the WEB server, and RTL description, selection and customization of IP, creation of programmable logic, determination regarding function realization of programmable logic using a verification algorithm, and the like are performed (step S404). Then, the determination unit creates binary data relating to the configuration of the programmable logic determined to realize the function, and transmits the binary data to the web server (step S405).

Then, the semiconductor maker receives the binary data from the web server and creates a programmable logic based on the binary data (step S40).
6). Since it is impossible to restore the original IP circuit from the binary data, the intellectual property relating to the IP design data of the IP provider is protected. Then, the semiconductor manufacturer performs a logic design verification (step S40).
7) Perform layout design verification (step S40)
8).

As described above, in the second embodiment, in the first client, the transmitting unit transmits the algorithm and the specification to the WEB server, and the receiving unit transmits
Receiving predetermined binary data from the EB server, the logic design unit performs a logic design based on the predetermined binary data received by the reception unit, and in the second client, the reception unit transmits the algorithm and the data from the WEB server. Receiving the specification, the programmable logic creating unit creates an RTL description related to the function of the integrated circuit from the specification received by the receiving unit, converts the created RTL description into programmable logic, A verification algorithm is created for accessing the programmable logic by adding a predetermined modification to the algorithm received by the receiving unit, and the determining unit accesses the programmable logic using the verification algorithm, and the programmable logic executes the algorithm. Implement the functions described in Determines whether Luke, transmitting unit, to create a binary data relating to the configuration of the programmable logic is determined to realize the function by the determination unit, to transmit binary data the created WEB server, WE
In the B server, since the publishing unit publishes the algorithm and specifications transmitted from the first client and the binary data transmitted from the second client, the IP provider (second client)
Can verify that its own IP works correctly for the desired algorithm. Also, IP
Since the provider (second client) does not need to disclose its own IP design data, it can naturally protect intellectual property. Therefore, it is possible to easily and efficiently use the IP and sufficiently cope with the shortening of the design period.

In the second embodiment, the first client and the second client further include a firewall between the server and the server as a protection means for transmitting and receiving only specific data. In addition, it is possible to prevent data theft and system destruction by malicious external users. For this reason, IP can be procured in a wide range. Therefore, it is possible to easily and efficiently use the IP and sufficiently cope with the shortening of the design period.

Although the second embodiment has been described with reference to a case where one first client and one second client are provided, the present invention is not limited to this. It may be configured to include a plurality of first clients and a plurality of second clients. Also,
In the second embodiment, the case in which the second client performs the function design and the verification is described. However, the third client performs the function verification of the IP provided from the second client using the verification algorithm. May be provided.

In the second embodiment, the case where binary data is transmitted from the second client via the WEB server has been described. However, the binary data is directly transmitted to the first client without via the WEB server. It can also be configured to do so. In the second embodiment, the first
Although the case where the algorithm is transmitted from the client to the second client has been described, a configuration may be such that the verification algorithm is transmitted instead of the algorithm.

(Embodiment 3) By the way, in Embodiments 1 and 2, the case where the verification design is performed by using the verification algorithm is shown. However, the present invention is not limited to this. Verification design can also be performed using input / output data (test vectors) of the algorithm. Therefore, in the third embodiment, a case will be described in which verification design is performed using input / output data (test vector) of an algorithm. It is to be noted that the same reference numerals are given to the portions having the same functions as the respective portions described in the first embodiment, and the detailed description thereof will be omitted.

First, the configuration of the integrated circuit designing apparatus according to the third embodiment will be described. FIG. 5 is a block diagram showing a configuration of the integrated circuit design device 8 according to the third embodiment. As shown in the figure, an integrated circuit design device 8 according to the third embodiment includes an algorithm design verification unit 2, a system specification generation unit 3, a test vector generation unit 9, a function design verification unit 10, a logic It comprises a design verification unit 6 and a layout design verification unit 7.

Schematically, integrated circuit designing apparatus 8 according to the third embodiment includes a
The description is converted into a programmable logic, input data and output data (test vector) relating to the function described in the algorithm are created in a test vector creation unit 9, and input data of the test vector is converted into a programmable logic in a function design verification unit 10. To compare whether the output data based on the input and the output data of the test vector match, thereby verifying whether the RTL description is equivalent to the algorithm at the stage of the function design based on the RTL description. Is what you do.

Referring to FIG. 5, the processing contents of test vector creation unit 9 and function design verification unit 10 in integrated circuit design apparatus 8 according to the third embodiment will be described. First, the test vector creation unit 9 shown in FIG. 5 uses input data and output data related to the function described in the algorithm that has been designed and verified by the algorithm design verification unit 2 as test vectors as input / output data creation means. This is a processing unit to be created.

The function design verification unit 10 shown in FIG.
As shown in FIG. 1, the configuration includes an RTL description unit 11, a programmable logic creation unit 12, and a comparison unit 13. Note that the RTL description section 11 and the programmable logic creation section 12 correspond to the RTL described in the first embodiment.
TL description section 51 and programmable logic creation section 5
2 has the same function as that of FIG. 2, and the description thereof will be omitted, and only the comparison unit 13 will be described.

The comparing section 13 of the functional design verifying section 10 inputs the input data created by the test vector creating section 9 to the programmable logic created by the programmable logic creating section 12 as an comparing means, and outputs an output based on the input. A processing unit that compares whether or not the data matches the output data created by the test vector creation unit 9. If the comparison unit 13 determines that the output data matches, it verifies that the algorithm and the RTL description are equivalent. On the other hand, if they do not match, a new RTL description is made until they match.

Next, a design processing procedure in the integrated circuit designing apparatus 8 according to the third embodiment configured as described above will be described. FIG. 6 is a flowchart showing a design processing procedure in the integrated circuit design device 8 according to the third embodiment. First, the algorithm design verification unit 2
The design of the algorithm is verified based on the purchase order (Step S601), and the test vector (input / output data) is created by the test vector creating unit 9 based on the algorithm (Step S602).

Then, the system specification creating unit 3
A specification is created based on the algorithm (step S6).
03), the RTL description unit 11 performs RTL description based on the specification (step S604), and the programmable logic creation unit 12 converts the RTL description into programmable logic (step S605).

Then, the comparing unit 13 compares whether the output data of the programmable logic and the output data of the test vector match (step S606), and when it is determined that they do not match (No at step S606). , Perform a new RTL description (step S60)
4). On the other hand, if it is determined that they match (step S
606), a logical design is performed by the logical design verification unit 6 (step S607), and a layout design is performed by the layout design verification unit 7 (step S6).
08).

As described above, in the third embodiment, the programmable logic creating unit 12 converts the RTL description described by the RTL description unit 11 into programmable logic, and the test vector creating unit 9 executes the algorithm design verification. The input data and output data related to the function described in the algorithm that has been designed and verified by the unit 2 are created. The comparison unit 13 inputs the input data of the test vector to the programmable logic, and outputs the output data and Since it is determined whether or not the output data matches the output data, it is possible to verify whether the RTL description is equivalent to the algorithm at the stage of the function design based on the RTL description. For this reason, it is also possible to verify whether the procured IP functions correctly for the target algorithm. Therefore, the efficiency of design verification and the efficiency of IP utilization can be improved, and the design time can be reduced.

(Embodiment 4) In Embodiment 4, an integrated circuit design system for performing the integrated circuit design method described in Embodiment 3 with an IP (design asset) provider connected to a network. Will be described. That is, the integrated circuit design system according to the fourth embodiment includes:
A first client as a semiconductor maker that creates specifications corresponding to an algorithm describing the function of an integrated circuit, which is a design target, and RTL related to the functions of the integrated circuit from the specifications
A second client as an IP provider that creates a description and a WEB server that provides a specification created by the first client to the second client are connected to a network.

Schematically, in the integrated circuit design system according to the fourth embodiment, a first client as a semiconductor maker transmits a test vector (algorithm input / output data) and specifications via a web server to an IP. Transmitting to the second client as a provider, the second client transmits binary data relating to the configuration of the programmable logic that has been subjected to the verification design using the test vector to the first client via the WEB server,
A first client performs a logical design based on the binary data.

Hereinafter, in the integrated circuit design system according to the fourth embodiment, the configuration and the contents of a first client as a semiconductor maker, a second client as an IP provider, and a WEB server will be briefly described.

The first client creates an algorithm based on the purchase order, and verifies whether the algorithm satisfies the contents of the purchase order.
A system specification creator that creates a system specification based on the algorithm, a test vector creator that creates algorithm input / output data based on the algorithm,
A transmitting unit for transmitting test vectors and specifications to the WEb server, a receiving unit for receiving predetermined binary data from the WEb server, a programmable logic creating unit for creating program logic based on the binary data, and a programmable logic And a layout design verification unit that generates mask data based on the netlist.

Further, the second client includes: a receiving unit that receives the test vector and the specification from the WEB server;
An RTL description related to the function of the integrated circuit is created from the received specifications, and a programmable logic creating unit that converts the RTL description into programmable logic is input to the programmable logic. A comparison unit that compares whether the output data based on the test vector and the output data of the test vector match, a binary data creation unit that creates binary data related to the configuration of the programmable logic determined to match by the comparison unit, and a created binary And a transmission unit for transmitting data to the WEB server.

Further, the WEB server includes a publishing unit for publishing the test vector and the specification transmitted from the first client and the binary data transmitted from the second client. Note that the first client and the second client each have a firewall as a protection means for transmitting and receiving only specific data to and from the WEB server.

Next, a design processing procedure in the integrated circuit design system according to the fourth embodiment configured as described above will be described. FIG. 7 is a sequence diagram showing a design processing procedure in the integrated circuit design system according to the fourth embodiment.

First, the semiconductor maker verifies the design of the algorithm, creates a test vector, and creates a specification, and transmits the test vector and the specification to the WEB server (steps S701 and S702).
And step S703). Although the transmitted test vector and specifications are made public on the server, it is impossible to restore the original algorithm from the test vector, so that the intellectual property relating to the algorithm of the semiconductor maker is protected.

Then, the IP provider receives the test vector and the specification from the WEB server, and performs RTL description, selection and customization of IP, creation of programmable logic, and comparison of output data of programmable logic using the test vector. And so on (step S704). Then, the comparison unit creates binary data relating to the configuration of the programmable logic for which the output data is determined to match, and transmits the binary data to the web server (step S70).
5).

Then, the semiconductor maker receives the binary data from the WEB server and creates a programmable logic based on the binary data (step S70).
6). Since it is impossible to restore the original IP circuit from the binary data, the intellectual property relating to the IP design data of the IP provider is protected. Then, the semiconductor manufacturer performs a logic design verification (step S70).
7) Perform layout design verification (step S70)
8).

As described above, in the fourth embodiment, in the first client, the test vector creation unit creates input data and output data related to the function described in the algorithm, and the transmission unit The input / output data and the specification are transmitted to the WEB server, the receiving unit receives predetermined binary data from the WEB server, and the logical designing unit performs a logical design based on the predetermined binary data received by the receiving unit, In the second client, the receiving unit receives input / output data and specifications from the WEB server, and the programmable logic creating unit creates an RTL description related to the function of the integrated circuit from the specifications received by the receiving unit. The created RTL description is converted into programmable logic, and the comparing unit converts the input data received by the receiving unit. Enter the log Lama Logic compares whether the output data received by the receiving unit and the output data based on the input match, the transmission section,
The comparing unit creates binary data relating to the configuration of the programmable logic verified to match the output data, and transmits the created binary data to a WEB server. Input and output data and specifications, and the second
The IP provider (the second client) can verify that the IP owned by itself functions correctly for the target algorithm. Further, the semiconductor maker (first client) does not need to disclose the algorithm, and the IP provider (second client) does not need to disclose the IP design data owned by the semiconductor maker. Can be protected. Therefore, it is possible to easily and efficiently use the IP and sufficiently cope with the shortening of the design period.

In the fourth embodiment, the first client and the second client further include a firewall between the server and the server as protection means for transmitting and receiving only specific data. In addition, it is possible to prevent data theft and system destruction by malicious external users. For this reason, IP can be procured in a wide range. Therefore, it is possible to easily and efficiently use the IP and sufficiently cope with the shortening of the design period.

Although the fourth embodiment has been described with reference to a case in which one first client and one second client are provided, the present invention is not limited to this. It may be configured to include a plurality of first clients and a plurality of second clients. Also,
In the fourth embodiment, the case where the function design and verification are performed in the second client has been described. However, the IP provided from the second client using the test vector
It is also possible to provide a third client for performing the function verification. Further, in the fourth embodiment, the case where binary data is transmitted from the second client via the web server has been described. It can also be configured.

The integrated circuit designing method described in the first to fourth embodiments can be realized by executing a prepared program on a computer such as a personal computer or a workstation. This program is recorded on a computer-readable recording medium such as a hard disk, a floppy (registered trademark) disk, a CD-ROM, an MO, and a DVD.
It is executed by being read from a recording medium by a computer. This program can be distributed via the recording medium and a network such as the Internet.

[0088]

As described above, according to the first aspect of the present invention, the programmable logic conversion means comprises the RT.
Converting the L description into programmable logic, the verification unit verifies whether the algorithm and the RTL description are equivalent based on the algorithm and the programmable logic converted by the programmable logic conversion unit, The logic design means performs the logic design of the integrated circuit based on the RTL description verified as equivalent by the verification means.
It is possible to verify whether the RTL description is equivalent to the algorithm at the stage of the functional design based on the description. For this reason, it is also possible to verify whether the procured IP functions correctly for the target algorithm. Therefore, there is an effect that an efficiency of design verification and an efficiency of IP utilization can be improved, and an integrated circuit design device capable of shortening design time can be obtained.

According to the second aspect of the present invention, in the verification means, the verification algorithm generating means generates a verification algorithm for accessing the programmable logic by making a predetermined modification to the algorithm. The determining unit accesses the programmable logic using the verification algorithm created by the verification algorithm creating unit, and determines whether the programmable logic realizes the function described in the algorithm. Therefore, it is possible to verify whether the RTL description is equivalent to the algorithm at the stage of the function design based on the RTL description. For this reason, it is also possible to verify whether the procured IP functions correctly for the target algorithm. Therefore, there is an effect that an efficiency of design verification and an efficiency of IP utilization can be improved, and an integrated circuit design device capable of shortening design time can be obtained.

According to the third aspect of the present invention, in the verification means, the input / output data creation means creates input data and output data related to the function described in the algorithm, and the comparison means creates the input / output data. The input data created by the data creation unit is input to the programmable logic converted by the programmable logic conversion unit, and output data output in response to the input data and the input / output data created by the input / output data creation unit. Since it is determined whether or not the output data coincides with the output data, it is determined in the stage of the function design based on the RTL description that the
It is possible to verify whether the L description is equivalent to the algorithm. For this reason, it is also possible to verify whether the procured IP functions correctly for the target algorithm. Therefore, there is an effect that an efficiency of design verification and an efficiency of IP utilization can be improved, and an integrated circuit design device capable of shortening design time can be obtained.

According to the fourth aspect of the present invention, since the algorithm is described in an object-oriented language, the behavior of a circuit (system) can be handled as a group. For this reason, there is an effect that an integrated circuit design device capable of improving the design operability can be obtained.

According to the fifth aspect of the present invention, the first
Wherein the first transmitting means transmits the algorithm and the specification to the server, the first receiving means receives predetermined binary data from the server, and the logical designing means The logic design of the integrated circuit is performed based on the predetermined binary data received by the receiving means. In the second client, the second receiving means receives the algorithm and the specification from the server, and A logic conversion unit that creates an RTL description related to the function of the integrated circuit from the specification received by the second reception unit, converts the created RTL description into programmable logic,
Verification algorithm creating means for creating a verification algorithm for accessing the programmable logic by applying a predetermined modification to the algorithm received by the second receiving means, and determining means for the verification algorithm creating means By accessing the programmable logic using a verification algorithm created by,
Determining whether the programmable logic implements the function described in the algorithm, the second transmission unit creates binary data relating to the configuration of the programmable logic determined to implement the function by the determination unit, The created binary data is transmitted to the server. In the server, the publishing unit includes an algorithm transmitted by the first transmitting unit and the first
Since the specification transmitted by the transmitting means and the binary data transmitted by the second transmitting means are disclosed, the IP provider (the second client)
Can verify that its own IP works correctly for the desired algorithm. Also, IP
Since the provider (second client) does not need to disclose its own IP design data, it can naturally protect intellectual property. Therefore, there is an effect that an integrated circuit design system that can easily and efficiently use the IP and can sufficiently cope with the reduction of the design period is obtained.

Further, according to the invention of claim 6, the first
Client, the input / output data creation means
First input means for generating input data and output data relating to the function described in the algorithm, the first transmitting means transmitting the input / output data and the specifications generated by the input / output data generating means to the server, The receiving means of
Upon receiving predetermined binary data from the server, the logic designing means performs a logic design of the integrated circuit based on the predetermined binary data received by the first receiving means, and in the second client, The second receiving means receives the input / output data and the specification from the server, and the programmable logic converting means
An RTL description relating to the function of the integrated circuit is created from the specification received by the second receiving means,
The description is converted into programmable logic, and the comparison means
The input data received by the second receiving means is input to the programmable logic converted by the programmable logic converting means, and the output data output in response to the input data and the second receiving means A comparison is made as to whether or not the received output data matches, and the second transmission means creates binary data relating to the configuration of the programmable logic verified by the comparison means that the output data matches, and the created binary data To the server, in the server, the publishing means, the input / output data transmitted by the first transmitting means, the specification transmitted by the first transmitting means, and the second transmitting means And the binary data sent by the IP provider (second class). Ant) can be IP to self-owned to verify whether the function correctly for the purposes of the algorithm. Also, the semiconductor maker (first client) does not need to disclose the algorithm, and the IP provider (second client) does
Since there is no need to disclose the P design data, intellectual property can be naturally protected. Therefore, there is an effect that an integrated circuit design system that can easily and efficiently use the IP and can sufficiently cope with the reduction of the design period is obtained.

According to the seventh aspect of the present invention, the first
Of the second client and the second client further include a protection means for transmitting and receiving only specific data to and from the server, so that a malicious external user can steal data or destroy the system. Can be prevented. For this reason, IP can be procured in a wide range. Therefore, there is an effect that an integrated circuit design system that can easily and efficiently use the IP and can sufficiently cope with the reduction of the design period is obtained.

According to the invention of claim 8, the programmable logic conversion step converts the RTL description into programmable logic, and the verification step converts the algorithm and the programmable logic converted by the programmable logic conversion step. And verifying whether or not the algorithm and the RTL description are equivalent, based on the RTL description verified to be equivalent in the verification step. Since the decision is made, it is possible to verify whether the RTL description is equivalent to the algorithm at the stage of the function design based on the RTL description. For this reason, it is also possible to verify whether the procured IP functions correctly for the target algorithm. Therefore, the efficiency of design verification and IP
There is an effect that an integrated circuit design method capable of improving the efficiency of use and shortening the design time is obtained.

According to the ninth aspect of the present invention, in the verifying step, the verifying algorithm creating step creates a verifying algorithm for accessing the programmable logic by applying a predetermined modification to the algorithm. The determining step includes accessing the programmable logic using the verification algorithm created in the verification algorithm creating step, and determining whether the programmable logic implements the function described in the algorithm. Therefore, it is possible to verify whether the RTL description is equivalent to the algorithm at the stage of the function design based on the RTL description. For this reason, it is also possible to verify whether the procured IP functions correctly for the target algorithm. Therefore, there is an effect that an integrated circuit design method capable of shortening the design time by improving the efficiency of design verification and the efficiency of IP utilization can be obtained.

According to the tenth aspect of the present invention, in the verification step, the input / output data creating step creates input data and output data related to the function described in the algorithm, and the comparing step includes the input / output data. The input data created by the data creation step is input to the programmable logic converted by the programmable logic conversion step, and the output data output corresponding to the input data and the input / output data created by the input / output data creation step Since it is determined whether or not the output data matches the output data, R
It is possible to verify whether the TL description is equivalent to the algorithm. For this reason, it is also possible to verify whether the procured IP functions correctly for the target algorithm.
Therefore, there is an effect that an integrated circuit design method capable of shortening the design time by improving the efficiency of design verification and the efficiency of IP utilization can be obtained.

According to the eleventh aspect of the present invention, since the algorithm is described in an object-oriented language, the behavior of a circuit (system) can be handled as a group. Therefore, there is an effect that an integrated circuit design method capable of improving the operability of design can be obtained.

According to the twelfth aspect of the present invention, in the first client, the first transmitting step transmits the algorithm and the specification to the server. Publishing the algorithm and the specification transmitted by the first transmitting step, and in the second client, the first receiving step includes receiving the algorithm and the specification from the server; Creates an RTL description relating to the function of the integrated circuit from the specifications received in the first receiving step, converts the created RTL description into programmable logic, and creates a verification algorithm in the first receiving step. A predetermined modification is made to the algorithm received by the process to access the programmable logic. A verification algorithm for performing the verification, and the determination step includes accessing the programmable logic using the verification algorithm created in the verification algorithm creation step, and the programmable logic describes a function described in the algorithm. The second transmission step creates binary data relating to the configuration of the programmable logic that has been determined to realize the function by the determination step, and transmits the created binary data to the server. In the server, the second publishing step publishes the binary data transmitted by the second transmitting step, and in the first client, the second receiving step receives the binary data from the server In the logic design process, the data is received in the second reception process. Since the logic design of the integrated circuit is performed based on the binary data, the IP provider (the second client) can verify whether the IP owned by the IP provider functions correctly with the target algorithm. it can. In addition, since the IP provider (second client) does not need to disclose its own IP design data, it can naturally protect intellectual property. Therefore, there is an effect that an integrated circuit design method that can easily and efficiently use the IP and sufficiently cope with the reduction of the design period is obtained.

According to the thirteenth aspect of the present invention, in the first client, the input / output data creating step includes:
Creating input data and output data related to the function described in the algorithm, a first transmitting step of transmitting the input / output data and the specification created in the input / output data creating step to the server, In the first publishing step, the input / output data and the specification transmitted in the first transmission step are disclosed, and in the second client, the first reception step includes: Receiving the data and the specifications, the programmable logic conversion step creates an RTL description relating to the function of the integrated circuit from the specifications received in the first reception step, converts the created RTL description into programmable logic, And comparing the input data received by the first receiving step with the programmable logic converting step. Therefore, the output is input to the converted programmable logic, and the output data output in response to the input data is compared with the output data received in the first receiving step to determine whether the output data matches the second input. The transmitting step creates binary data relating to the configuration of the programmable logic verified that the output data matches by the comparing step, and transmits the created binary data to the server. In the server, a second publishing step includes: Publish the binary data transmitted in the second transmitting step, and in the first client,
In the second receiving step, the binary data is received from the server, and in the logical designing step, the logical design of the integrated circuit is performed based on the binary data received in the second receiving step. , The IP provider (second client) can verify that the IP owned by the IP provider functions correctly for the target algorithm. Further, the semiconductor maker (first client) does not need to disclose the algorithm, and the IP provider (second client) does not need to disclose its own IP.
Since there is no need to disclose design data, intellectual property can naturally be protected. Therefore, there is an effect that an integrated circuit design method that can easily and efficiently use the IP and sufficiently cope with the reduction of the design period is obtained.

According to the fourteenth aspect of the present invention, the first client and the second client further include a protection step of transmitting / receiving only specific data to / from the server. Therefore, it is possible to prevent data theft and system destruction by malicious external users. For this reason, IP can be procured in a wide range. Therefore, there is an effect that an integrated circuit design method that can easily and efficiently use the IP and sufficiently cope with the reduction of the design period is obtained.

According to the fifteenth aspect of the present invention, a program for causing a computer to execute the method according to any one of the eighth to fourteenth aspects is recorded, so that the program becomes machine-readable. Accordingly, an effect is obtained that a recording medium capable of realizing the operation of any one of claims 8 to 14 by a computer can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an integrated circuit design device according to a first embodiment.

FIG. 2 is an explanatory diagram for describing a method of creating a verification algorithm by a verification algorithm creation unit illustrated in FIG. 1;

FIG. 3 is a flowchart showing a design processing procedure in the integrated circuit design device according to the first embodiment;

FIG. 4 is a sequence diagram illustrating a design processing procedure in the integrated circuit design system according to the second embodiment;

FIG. 5 is a block diagram showing a configuration of an integrated circuit design device according to a third embodiment.

FIG. 6 is a flowchart illustrating a design processing procedure in the integrated circuit design apparatus according to the third embodiment;

FIG. 7 is a sequence diagram showing a design processing procedure in the integrated circuit design system according to the fourth embodiment.

FIG. 8 is a flowchart showing a procedure for designing a system LSI according to the related art.

[Explanation of symbols]

 1, 8 Integrated circuit design device 2 Algorithm design verification unit 3 System specification preparation unit 4 Verification algorithm preparation unit 5 Function design verification unit 6 Logic design verification unit 7 Layout design verification unit 11, 51 RTL description unit 12, 52 Programmable logic generation Unit 13 Comparison unit 53 Judgment unit

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/82 A

Claims (15)

[Claims] 1. An integrated circuit design that creates a specification corresponding to an algorithm describing a function of an integrated circuit, which is a design target, and creates an RTL description relating to the function of the integrated circuit from the created specification to perform logical design. In the apparatus, based on the algorithm and the programmable logic converted by the programmable logic conversion means, the algorithm and the RTL description are equivalent based on programmable logic conversion means for converting the RTL description into programmable logic. An integrated circuit design apparatus, comprising: a verification unit for verifying whether the integrated circuit is logically designed based on the RTL description verified to be equivalent by the verification unit. . 2. The verification unit according to claim 1, wherein the verification unit is configured to generate a verification algorithm for accessing the programmable logic by adding a predetermined modification to the algorithm. Determining means for accessing the programmable logic using a verification algorithm to determine whether the programmable logic implements the function described in the algorithm. An integrated circuit design apparatus according to the above. 3. The input / output data generating means for generating input data and output data relating to a function described in the algorithm, and the input / output data generating means converts the input data generated by the input / output data generating means into the programmable logic conversion. Comparing means for inputting to the programmable logic converted by the means, and comparing whether output data output according to the input data and output data generated by the input / output data generating means coincide with each other. The integrated circuit design apparatus according to claim 1, comprising: 4. The integrated circuit design apparatus according to claim 1, wherein the algorithm is described in an object-oriented language. 5. A first client for creating a specification corresponding to an algorithm describing a function of an integrated circuit, which is a design target, and a second client for creating an RTL description related to the function of the integrated circuit from the created specification. A client and the first
And a server that provides the specifications created by the second client to the second client to a network, and the RTL created by the second client
In an integrated circuit design system for performing a logical design of the integrated circuit based on a description, the first client includes: a first transmission unit that transmits the algorithm and the specification to the server; and predetermined binary data from the server. And a logic design unit that performs a logic design of the integrated circuit based on predetermined binary data received by the first reception unit. The second client includes: A second receiving means for receiving the algorithm and the specification from a server, and creating an RTL description relating to the function of the integrated circuit from the specification received by the second receiving means; A programmable logic converting means for converting, and an A verification algorithm creating means for creating a verification algorithm for accessing the programmable logic by applying a predetermined modification to the algorithm, and accessing the programmable logic using the verification algorithm created by the verification algorithm creating means. Determining means for determining whether the programmable logic implements the function described in the algorithm, and creating binary data relating to the configuration of the programmable logic determined to implement the function by the determination means; A second transmitting unit that transmits the created binary data to the server, the server comprising: an algorithm transmitted by the first transmitting unit; a specification transmitted by the first transmitting unit; Transmitted by the second transmitting means. Integrated circuit design system comprising the public means to expose the binary data. 6. A first client for creating a specification corresponding to an algorithm describing a function of an integrated circuit, which is a design target, and a second client for creating an RTL description related to the function of the integrated circuit from the created specification. The client and the first
And a server that provides the specifications created by the second client to the second client to a network, and the RTL created by the second client
In an integrated circuit design system for performing a logical design of the integrated circuit based on the description, the first client includes: an input / output data generating unit configured to generate input data and output data relating to a function described in the algorithm; First transmission means for transmitting the input / output data created by the entry output data creation means and the specification to the server, first reception means for receiving predetermined binary data from the server, and first reception Logic design means for performing a logic design of the integrated circuit based on predetermined binary data received by the means, wherein the second client receives the input / output data and the specification from the server. Receiving means and, based on the specification received by the second receiving means, an RTL description relating to the function of the integrated circuit; A programmable logic converting means for converting the generated RTL description into programmable logic, and inputting the input data received by the second receiving means to the programmable logic converted by the programmable logic converting means; Comparing means for comparing whether output data output in response to the input data and the output data received by the second receiving means match, and verifying that the output data matches by the comparing means. And a second transmitting unit that generates binary data relating to the configuration of the programmable logic and transmits the generated binary data to the server. The server includes: an input / output data transmitted by the first transmitting unit; , The specification transmitted by the first transmitting means, Integrated circuit design system comprising the public means to expose the transmitted binary data by the transmitting means. 7. The first client and the second client
7. The integrated circuit design system according to claim 5, wherein said client further comprises a protection means for transmitting and receiving only specific data to and from said server. 8. An integrated circuit design which creates a specification corresponding to an algorithm describing an integrated circuit function which is a design target, and creates an RTL description relating to the function of the integrated circuit from the created specification to perform a logic design. A method of converting the RTL description into programmable logic; and determining whether the algorithm and the RTL description are equivalent based on the algorithm and the programmable logic converted by the programmable logic conversion step. A verification process for verifying whether the integrated circuit is logically designed based on the RTL description verified to be equivalent in the verification process. . 9. The verification step, wherein the verification step is performed by a predetermined modification to the algorithm to generate a verification algorithm for accessing the programmable logic, and the verification algorithm is generated by the verification algorithm generation step. And determining whether the programmable logic implements the function described in the algorithm by accessing the programmable logic using a verification algorithm. The integrated circuit design method according to the above. 10. The input / output data generating step of generating input data and output data relating to a function described in the algorithm, and the input / output data generating step of converting the input data generated by the input / output data generating step into the programmable logic conversion. A comparing step of comparing whether or not output data output in accordance with the input data input to the programmable logic converted in the step and output data generated in the input / output data generating step match with each other; The integrated circuit design method according to claim 8, comprising: 11. The integrated circuit design method according to claim 8, wherein the algorithm is described in an object-oriented language. 12. A first client for creating a specification corresponding to an algorithm describing a function of an integrated circuit which is a design target, and a second client for creating an RTL description relating to the function of the integrated circuit from the created specification. Connecting a client and a server that provides the specification created by the first client to the second client to a network, and connecting the RTL created by the second client
An integrated circuit design method for performing a logical design of the integrated circuit based on a description, wherein: the first client transmits the algorithm and the specification to the server; a first transmitting step; A first publishing step of publishing the algorithm and the specification transmitted by the transmitting step of: a first receiving step of receiving the algorithm and the specification from the server by the second client; Generating an RTL description related to the function of the integrated circuit from the specifications received in the receiving step, and converting the generated RTL description into programmable logic; and an algorithm received in the first receiving step. Verification for accessing the programmable logic with a predetermined modification A verification algorithm creating step of creating an algorithm, and accessing the programmable logic using the verification algorithm created by the verification algorithm creating step, and determining whether the programmable logic implements a function described in the algorithm. A determining step of determining whether or not the binary logic is to be implemented by the determining step, creating binary data related to a configuration of the programmable logic determined to realize the function, and transmitting the created binary data to the server; A second publishing step in which the server publishes the binary data transmitted by the second transmitting step; a second receiving step in which the first client receives the binary data from the server; The binary data received by the receiving step A logic design step of performing a logic design of the integrated circuit based on the data. 13. A first client for creating a specification corresponding to an algorithm describing a function of an integrated circuit, which is a design target, and a second client for creating an RTL description relating to the function of the integrated circuit from the created specification. Connecting a client and a server that provides the specification created by the first client to the second client to a network, and connecting the RTL created by the second client
An integrated circuit design method for performing a logic design of the integrated circuit based on a description, wherein an input / output data creating step in which the first client creates input data and output data related to a function described in the algorithm; A first transmission step of transmitting the input / output data and the specification created by the entry output data creation step to the server; and the server transmits the input / output data and the specification transmitted by the first transmission step. A first publishing step of publishing, a first receiving step in which the second client receives the input / output data and the specification from the server, and an integrated circuit from the specification received in the first receiving step RTL description relating to the function of (1), and converts the generated RTL description into programmable logic. And the input data received in the first receiving step is input to the programmable logic converted in the programmable logic converting step, and the output data output in response to the input data and A comparing step of comparing whether or not the output data received by the first receiving step matches, and binary data relating to the configuration of the programmable logic verified to have the matching output data by the comparing step, A second transmitting step of transmitting binary data to the server; a second publishing step in which the server publishes the binary data transmitted in the second transmitting step; and the first client: A second receiving step of receiving the binary data from A logic design step of performing a logic design of the integrated circuit based on the received binary data. 14. The method according to claim 12, wherein the first client and the second client further include a protection step of transmitting / receiving only specific data to / from the server. Integrated circuit design method. 15. A computer-readable recording medium having recorded thereon a program for causing a computer to execute the method according to any one of claims 8 to 14.