JP2002009144A - Method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technique for reducing a hollow (a divot) occurring at the end part of an element region and an element isolation region for the purpose of an oxide film removal process carried out repeatedly in forming a groove buried type element isolation region of a semiconductor device, and further to provide a technique for decreasing an oxidizing treating temperature after having formed a STI groove so as to isolate the element region. SOLUTION: In this method for manufacturing the semiconductor device, a silicon film is formed on the element isolation groove formed on the semiconduction substrate and on a first insulating layer, or after having formed the silicon film on an isolation mask opening and on the first insulating layer, the element isolation groove is formed, and the surface of the element isolation groove and the silicon film are then oxidized. As a result, the silicon film becomes an etching stopper in an oxide film removal process and thus the divot can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor memory device, and more particularly to a DRAM (Dynamic Lando).
m Access Memory).

[0002]

2. Description of the Related Art As the capacity of semiconductors has increased, the cell size has been reduced.
STI (Shallow Trench Isolat)
ion). However, in this STI, the shape of the end of the element region is bad. Therefore, after forming the STI trench, an oxidation process is performed to improve the shape of the end portion,
Thereafter, a method of forming an oxide film in the element isolation region has been adopted.

A method for forming an STI when a conventional DRAM is manufactured will be described with reference to the drawings. FIG.
FIG. 11 is a longitudinal sectional view sequentially showing a manufacturing process of an STI in a conventional DRAM. First, as shown in FIG. 3A, a silicon oxide film 2 having a thickness of 10 to 30 nm is formed on a semiconductor substrate 1 and a silicon nitride film 3 having a thickness of 100 to 300 nm is formed thereon. The region to be formed and the region to be a field are patterned by lithography and dry etching. Then, as shown in FIG.
The element isolation region where the film is removed and the semiconductor substrate 1 is exposed is further anisotropically etched to form an element isolation groove 4 having a depth of about 100 to 500 nm.

Subsequently, as shown in FIG. 3C, a silicon oxide film 10 is formed on the side wall of the isolation trench 4 by a thermal oxidation method. Subsequently, as shown in FIG. 3D, the element isolation trench 4 is buried with a silicon oxide film 5 by a chemical vapor deposition (CVD) method, and a flattening process is performed. After this, FIG.
As shown in FIG. 3E, the silicon nitride film 3 is removed, and as shown in FIG. 3F, the silicon oxide film 2 is also removed to expose the semiconductor substrate 1. Subsequently, as shown in FIG. 3 (g), a silicon oxide film 6 is formed again on the exposed semiconductor substrate 1, and thereafter, a diffusion layer 7 is formed on the semiconductor substrate 1 by ion implantation. Thereafter, the silicon oxide film 6 is removed as shown in FIG. Subsequently, although not shown, after depositing the gate electrode material, a gate electrode is formed by lithography and dry etching.

In such a conventional method, since a thermal oxidation treatment as shown in FIG. 3C for improving the shape of the end portion of the element region is performed at a high temperature, a large stress is applied to the silicon substrate, and particularly, Since there is no margin for stress in a wafer of 6 inches or more, there is a problem that a defect or a transfer is caused.

Furthermore, in this conventional method, the silicon oxide film 5 used for embedding the STI is etched in the lateral direction by an oxide film removing step that is repeatedly performed from the formation of the STI to the formation of the gate electrode, and thus the element region is formed. And S
A depression (divot) occurs at the TI interface as shown in FIG. If the semiconductor substrate portion is exposed by the divot, an electric field is concentrated on the exposed substrate portion, causing problems such as a decrease in threshold current and an adverse effect on transistor performance.

[0007]

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem. When forming a trench-filled element isolation region of a semiconductor device by STI, an oxidation treatment temperature is reduced. And the element region and ST
It is an object of the present invention to provide a method for efficiently manufacturing a highly reliable semiconductor device having a smooth substrate surface without causing depression at an I interface.

[Means for Solving the Problems]

The invention of the present invention, which solves the above-mentioned problems, is characterized by the fact that a silicon thermal oxide film is formed on a side wall of an element isolation groove by a thermal oxidation method after forming an element isolation groove. A method for manufacturing a semiconductor device, characterized by "a silicon film is formed in an element isolation groove and on a first insulating layer after the element isolation groove is formed, and the silicon layer is oxidized to a silicon oxide film."

According to the first aspect of the present invention, since the silicon film formed on the element isolation trench is oxidized, the oxidization temperature is reduced as compared with the case where the conventional thermal oxide film is formed with the semiconductor substrate exposed. It can be reduced. For this reason, the stress applied to the silicon substrate is reduced, so that the problem of defects and transfer in a large-sized wafer can be reduced. In addition, since the silicon film and the oxide film on the side walls of the isolation trench serve as stoppers in the oxide film etching performed in a later step, the divot can be suppressed low.

[0010] The invention of claim 2 of the present invention is directed to a method of forming a silicon thermal oxide film by a thermal oxidation method on a side wall of an element isolation groove after forming an element isolation groove. Before forming the groove, a silicon film is formed on the semiconductor substrate and the first insulating layer, and after forming the element isolation groove, the sidewall portion of the element isolation groove and the silicon film are oxidized to form a silicon oxide film. Of the semiconductor device.

According to the second aspect of the present invention, since the silicon film and the oxide film on the side wall of the first insulating layer serve as stoppers when the oxide film is etched in a later step, the divot can be kept low. become.

[0012] Claims 3 to 6 of the present invention each have a first
The film constituting the insulating film is a silicon nitride film;
The film constituting the insulating film is a silicon oxide film, the oxidation of the silicon film is to partially or entirely oxidize the silicon film, and the first insulating film is formed directly or via another layer on the semiconductor substrate. The method according to claim 1 or 2, wherein
Semiconductor device manufacturing method.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 Next, an embodiment of a method of manufacturing a semiconductor device according to the present invention will be described with reference to the drawings.
FIG. 1 is a longitudinal sectional view showing the first embodiment of the present invention in the order of steps.

First, as shown in FIG. 1A, a silicon oxide film 2 having a thickness of 10 to 30 nm is formed on a semiconductor substrate 1 and a silicon nitride film 3 having a thickness of 100 to 300 nm is formed thereon as shown in FIG. Is formed, a region to be a diffusion layer and a region to be a field are patterned by lithography and dry etching. Subsequently, as shown in FIG. 1B, as shown in FIG.
Is further anisotropically etched in the element isolation region where
An element isolation groove 4 having a depth of about 100 to 500 nm is formed.

Subsequently, as shown in FIG. 1C, a silicon film 8 is formed to a thickness of 5 to 30 nm in a state where the semiconductor substrate 1 is exposed, and thereafter, as shown in FIG. Form 10. Thereafter, as in the conventional method, as shown in FIG.
Is buried with a buried oxide film 5 of silicon oxide, and thereafter, the surface is flattened. Subsequently, the silicon nitride film 3 is removed as shown in FIG. 1F, and the silicon oxide film 2 is removed as shown in FIG. Next, FIG.
As shown in (1), after a silicon oxide film 6 is formed again on the exposed semiconductor substrate 1, a diffusion layer 7 is formed on the semiconductor substrate 1 by ion implantation. Subsequently, as shown in FIG. 1I, the silicon oxide film 6 is removed. Thereafter, although not shown, after depositing the gate electrode material, a gate electrode is formed by lithography and dry etching.

In this embodiment, by forming a silicon film having little dependence on plane orientation, an effect of improving the shape of the end portion of the diffusion layer can be obtained even at low-temperature oxidation treatment. And the problem of defects and dislocations can be suppressed. In addition, since the silicon film and the thermal oxide film on the side wall of the silicon nitride film serve as protection regions when the oxide film is etched in the step shown in FIG. 1 (g), divot hardly occurs and a smooth surface is easily obtained. Occurs.

[Second Embodiment] The same effect as described above can be realized by forming a silicon film in a method of manufacturing a semiconductor device of the present invention before forming an element isolation groove. FIG. 2 is a longitudinal sectional view showing the steps of the second embodiment of the present invention in order.

First, as shown in FIG. 2A, a silicon oxide film 2 having a thickness of 10 to 30 nm is formed on a semiconductor substrate 1 and a silicon nitride film 3 having a thickness of 100 to 300 nm is formed thereon as shown in FIG. Is formed, a region to be a diffusion layer and a region to be a field are patterned by lithography and dry etching. Subsequently, as shown in FIG. 2B, a silicon film 9 is formed with a thickness of 5 to 30 nm. Further, anisotropic etching is performed in the element isolation region, and a depth of 100 to 500 as shown in FIG.
A device isolation groove 4 of nm is formed. Next, as shown in FIG. 2D, a silicon thermal oxide film 10 is formed with the semiconductor substrate 1 exposed.

Thereafter, as shown in FIG.
The element isolation trench 4 is buried with a buried oxide film 5 of a silicon oxide film by a method, and a planarization process is performed. Then, FIG.
The silicon nitride film 3 is removed as shown in FIG.
As shown in (g), the silicon oxide film 2 is removed. Subsequently, as shown in FIG.
The silicon oxide film 6 is formed again. After that, the diffusion layer 7 is formed on the semiconductor substrate 1 by ion implantation. After this,
As shown in FIG. 2I, the silicon oxide film 6 is removed. Although not shown, as a subsequent step, a gate electrode material is deposited, and a gate electrode is formed by lithography and dry etching.

In this embodiment, since the silicon film and the thermal oxide film on the side wall of the silicon nitride film serve as protection regions when the oxide film is etched in the step shown in FIG. 2 (g), divot hardly occurs and a smooth surface is obtained. The effect that it becomes easy to obtain arises.

In the first and second embodiments, the film forming the first insulating layer is a silicon nitride film, and the film forming the second insulating layer is a silicon oxide film. However, the present invention is not limited to this. Any material may be used as long as it has a higher etching rate than the silicon film and is selectively removed at the time of etching. In the first and second embodiments, the first insulating layer is formed on the semiconductor substrate via the silicon oxide film.
It may be formed directly on the semiconductor substrate or via another layer.

[0022]

As described above, according to the method of manufacturing a semiconductor device of the present invention, a low-temperature thermal oxidation is made possible by forming a silicon film on a silicon nitride film via an insulating film on a semiconductor substrate, Defects and dislocation problems can be reduced. Furthermore, since the silicon film on the side wall of the silicon nitride film serves as a stopper for oxide film etching performed in a later process, divot generated on the surface when the diffusion phase is exposed can be reduced, and the exposure of the semiconductor substrate portion can be reduced. Prevent,
Problems such as a decrease in threshold current and an adverse effect on transistor performance can be reduced.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view showing a manufacturing process according to a first embodiment of the present invention, in which the order is shown from (a) to (i).

FIG. 2 is a longitudinal sectional view showing a manufacturing process according to a second embodiment of the present invention, in which the order is shown from (a) to (i).

FIG. 3 is a longitudinal sectional view showing a manufacturing process of a conventional invention.
The order is shown from (a) to (h).

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 semiconductor substrate 2 6 silicon oxide film 5 buried oxide film 10 silicon thermal oxide film 3 silicon nitride film 4 element isolation groove 7 diffusion layer 8 9 silicon film

Claims (6)

[Claims] A step of forming an element isolation groove in an opening of a first insulating layer and an isolation mask formed on a semiconductor substrate; and forming a silicon film in the element isolation groove and on the first insulating layer by oxidation. And a step of filling the element isolation trench with a second insulating layer and then planarizing the same in this order. 2. A step of forming an isolation mask opening in a first insulating layer formed on a semiconductor substrate; a step of forming a silicon film on the isolation mask opening and the first insulating layer; Forming an element isolation groove in the mask opening and then oxidizing the inside of the element isolation groove and the silicon film; and filling the element isolation groove with a second insulating layer and then planarizing the same. A method for manufacturing a semiconductor device, comprising: 3. The method according to claim 1, wherein the film constituting the first insulating layer is a silicon nitride film. 4. The method according to claim 1, wherein the film forming the second insulating layer is a silicon oxide film. 5. The method according to claim 1, wherein the oxidation of the silicon film oxidizes part or all of the silicon film. 6. The method according to claim 1, wherein the first insulating layer is formed on the semiconductor substrate directly or via another layer.