JP2001510303A - ATM cell enhancement with buffering data - Google Patents

Abstract

(57) Abstract: An asynchronous transfer mode (ATM) switch (20) includes a controller (44) that augments ATM cells with buffered data. During input of the cell into the switch, a buffer circuit (46) connected to the controller (44) receives the enhanced ATM cells and stores the enhanced ATM cells in a buffer cell memory (90) in response to the buffered data. Store cells. The ATM cells are extracted from the buffer cell memory (90), and the ATM cells are derived through the switch core (22). During output of the cell from the switch, the cell leaves the switch core (22), travels through the switch port (50), and is received at the second buffer circuit (72). The second buffer circuit (72) stores the enhanced ATM cell in the cell buffer memory (92) according to the buffering data.

Description

DETAILED DESCRIPTION OF THE INVENTION

(Background) [0001] The present application relates to "BUFFERING OF POINT-TO-POINT AND / OR POINT-TO-MULTIPOINT ATM
CELLS "(buffering point-to-point and / or point-to-multipoint ATM cells)
And assigned to U.S. Patent Application Serial No. 08 /, 083, filed concurrently and filed (Attorney Docket No. 1410-312), the contents of which are hereby incorporated by reference.

[0002] The present invention relates to telecommunications, and more particularly to the processing of cells at switching nodes of a telecommunications network operating in an asynchronous transfer mode.

Related Technologies and Other Considerations Multimedia applications, video on demand, video telephony,
Increasing interest in high band services, such as video conferencing and video conferencing, has driven the development of broadband integrated digital networks (B-ISDN).
B-ISDN is based on a technique known as Asynchronous Transfer Mode (ATM) and provides a significant extension of telecommunications capabilities.

[0004] ATM is a packet-oriented transfer mode that uses asynchronous time-division multiplexing technology. Packets are called cells and have a fixed size. An ATM cell is composed of 53 octets, of which 5 octets form the header and 48 octets constitute the payload, or information portion of the cell. The header of an ATM cell contains two quantities used to identify a connection in the ATM network in which the cell travels, namely a VPI (virtual path identifier) and a VCI (virtual channel identifier). Typically, a virtual route is a main route defined between two switching nodes in a network, and a virtual channel is one specific connection on each main route.

[0005] The ATM network is connected at its terminal points to terminal equipment, for example, ATM network users. There are a plurality of switching nodes (for example, ATM switches) between terminal points of the ATM network, and ports of the switching nodes are connected to each other by a physical transmission path. When transmitting from the originating terminal to the destination terminal, the ATM cells forming the message may pass through several switching nodes.

[0006] Typically, the switching nodes each have several functional parts, including a switch core. The switch core functions essentially like a cross connection between the ports of the switch. The switch core includes a spatial switching circuit and sends the incoming cell of the message to the target output port via the switch core based on the routing information. Thus, the switching node facilitates the transmission of the message from the source terminal of the cell to the final destination terminal.

[0007] In addition to port connections (eg, routing through a switch core), typical ATM switches also perform several other functions. For example, address translation,
Functions such as policing, buffering, etc. must also be performed. The data required to perform these other functions must be made available to the components of the ATM switch (eg, by table lookup). It is important to note that such functions of a switch are usually distributed over multiple circuits, as not all of these functions can be legitimately integrated into a single integrated circuit.

In a conventional ATM switch, when an ATM cell arrives at the switch, A
The VPI / VCI amount in the TM cell header and the link identification information are used in a table lookup operation (eg, by the switch's first cell processing circuit) to obtain both a routing tag and an internal channel number within the switch. use. The routing tag and internal channel number are then added to the ATM cell and used in other parts of the circuits in the switch. Some of these other circuits use the internal channel number for yet another table lookup operation involving external memory. Others of these circuits use routing tags for yet another table lookup operation involving internal (eg, on-chip) or external memory.

As described above, in the conventional ATM switch, it is necessary to refer to a table in some circuits. If the number of reference operations increases, the required memory naturally increases,
For example, in terms of memory cost, more complex and costly circuits that require interfaces for such memories, premium switch size, required power consumption, and memory access time. Is undesirable.

In view of the foregoing, one approach to simplifying cell processing with an ATM switch is to limit the total amount of data required for cell transport through the switch. Such restrictions include: (1) limiting data per connection;
Or (2) reducing the number of allowed connections. The first solution is to keep the number of connections allowed, but the ATM parameters become more more courses. These two approaches merely reduce the memory size and still require table lookup.

[0011] Therefore, in the ATM switch, there is a need for an effective and efficient cell processing in which the amount of reference memory is minimized, and this is an object of the present invention.

(Summary) Asynchronous transfer mode (ATM) switch performs A
A controller is provided to augment the TM cells. In a reference operation performed using a reference table, the controller extracts buffering data using VPI / VCI and a link ID as an index.

During input of cells into the switch, a first buffer circuit connected to the controller receives the enhanced ATM cells and stores the enhanced ATM cells in a buffer cell memory in response to buffered data. . ATM cells are extracted from the buffer cell memory and derived through the switch core. During output of the cell from the switch, the cell leaves the switch core, travels through the switch port, and is received at the second buffer circuit. The second buffer circuit stores the enhanced ATM cell in the cell buffer memory at the time of output according to the buffering data.

In a point-to-point cell, the advantage is that the reference operation performed by the controller is the only reference operation performed on the ATM cell at the entry side of the switch (ie, before being derived through the switch core). is there. The buffering data for enhancing the ATM cells also includes buffering data for the second buffer circuit, and the reference operation performed by the controller is the only reference operation performed by the entire switch using the external memory.

In a multicast (ie, point-to-multipoint) cell, a second reference operation is performed at the egress side of the switch, and the second buffer circuit allocates a new VPI / VCI to an output cell.

The foregoing and other objects, features, and advantages of the invention will be apparent from the following more particular description of preferred embodiments, as illustrated in the accompanying drawings. In the drawings, reference characters indicate the same parts throughout the different views. The drawings are not necessarily drawn to the same magnification and, instead, emphasis is placed upon illustrating the principles of the invention.

In the following description, for purposes of explanation and not limitation, specific details, such as particular architectures, interfaces, techniques, etc., are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known devices, circuits, and methods are omitted so as not to obscure the present invention with unnecessary detail.

FIG. 1 mainly illustrates a switch core 22 and a plurality of device boards or replacements.
Terminal 24₁~ 24_n2 illustrates an ATM switch 20 including: Each exchange terminal has a set of
The ATM physical link 30 and the set of egress physical links 31 provide an ATM network.
Connected to another part of the network, for example another node. For example, switching node 24 ₁ Is the entrance physical link 30₁And exit physical link 31₁It is shown with

While only two switching terminals 24 are shown in FIG. 1, many such switching terminals are provided and are connected to the switch core 22 as shown with respect to the switching terminals shown. It will be understood. Furthermore, when quoting a switching terminal or a component of a switching terminal, if there is no subscript, it is not possible to indicate either such switching terminal or element comprehensively and a particular switching terminal or element. Is intended.

The main function of the switch core 22 is to perform spatial switching, for example,
The ATM cells received at one of its input terminals are routed to the appropriate output terminal (s) of the switch core 22 and the ATM transmission (consisting of potentially many ATM cells) is sent to the calling terminal (sending side). And the destination terminal device (target receiver). For example, as shown by dashed line 39, FIG.
2 cell links 30 on _one incoming to to send the final exit link 31 _n
1 shows a switch core 22 connecting two ports. For a point-to-multipoint cell, also known as a multicast cell, the switch core 22
It also copies M cells and distributes ATM cells to appropriate output terminals. The structure and operation of the switch core 22 is well known to those skilled in the art and therefore will not be described in further detail here.

The switching terminals 24 of the switch 20 each include a line termination (LT) 40 that interfaces with an ingress physical link 30 and an egress physical link 31. Each switching terminal 24 has a link 42 on the receiving side that connects the line terminating equipment 40 to the ATM controller 44. In the illustrated embodiment, as many as 32 physical links 30 can be connected to the ATM controller 44. The output terminal of the controller 44 is connected to a first buffer circuit 46, while the first buffer circuit 46 is connected to a switch port entry side input terminal 48 of the switch port 50. The switch port 50 is connected to an appropriate one of the plurality of switch core ingress input terminals 54 by a switch core ingress input interface 56.
It has an inlet-side output terminal 52.

The switch core 22 has a plurality of outlet output terminals 64, which are
It is paired with the entry-side input terminal 54 of the core 22 and, depending on the corresponding pairing configuration, is connected to the switching terminal 24 by the output-side output interface 66 of the switch core. On its exit side, each switching terminal 24 has an exit-side input terminal 68. The outlet side input terminal 68 is connected to the interface 66. Switch port 50
The output terminal 70 on the outlet side is connected to a second buffer circuit 72, while the second buffer circuit 72 is connected to the line termination device 40 by a link 74. Line termination 40 functions to interface link 74 to egress physical link 31.

At each switching terminal 24, the ATM controller 44
And the database memory 82. The database memory is preferably a random access memory (RAM). Microprocessor 80 is used, for example, to build a database located in database memory 82. Regarding the use of the database in the memory 82, A
This will be described later in connection with the operation of the TM controller 44. In the illustrated embodiment, A
The TM controller 44 is a device sold by PMC-Sierra, Inc. (PMC-Sierra) under the part number PM7322 RCMP-800, and performs ATM layer routing control, monitoring, and management.

In the illustrated embodiment, each switching terminal 24 has a microprocessor 80. The switch 20 has one or more central processors, not shown, to which the microprocessors 80 of the various switching terminals 24 are connected.

An output terminal of the controller 44 is connected to the first buffer circuit 46. The first buffer circuit 46 is connected to store ATM cells in the cell buffer 90 and access the ATM cells in the cell buffer 90. Similarly, on the outgoing side of the exchange terminal 24, the second buffer circuit 72
It is connected to store M cells and to access ATM cells in cell buffer 92.

Collectively, buffer circuit 46 and cell buffer 90 form entry buffering section 100, and buffer circuit 72 and cell buffer 92 form exit buffering section 102. Inlet buffering section 100 can take many forms, such as in the form of section 100A shown in FIG. 3 (for example). FIG.
2 includes both an input queue selector 120 and an output queue selector 122. The cell buffer 92 has a plurality of queues 110 for each of a plurality of priorities. Only one queue for each priority is associated with the corresponding switch port. 1 for each priority
One queue is a point-to-multipoint queue. In response, in FIG.
10 is subscripted according to priority and destination switch port. That is, the queues 110 _{1 and 2} are, for example, queues for priority 1 and destination switch port 2. The point-to-multipoint queue has "p-" as an indicator for each rank.
mp ”. Therefore, the queue _{1101, p-mp} is a queue for a point-to-multipoint cell of priority 1.

The switch 20 performs a preparation operation and adds both “buffering data” and routing data to the incoming ATM cell. FIG. 2 schematically illustrates the transmission of ATM cells through switch 20 and the contents of ATM cells at different junctions in routing through switch 20.

When arriving at the ATM controller 44 of the switch 20, the ATM cell has both its payload 200 and its header 202. ATM controller 44 uses information about the VPI / VCI portion of cell header 202 and the physical link of the incoming cell as an index in a smart search algorithm (based on a binary search) and is in a database stored in memory 82. An appropriate one is determined from the plurality of records 400. As shown in FIG.
Records in the data base database include, for example, a core routing data field, a threshold value field of the first buffer circuit 46, a queue data field of the first buffer circuit 46, and a connection type of the first buffer circuit 46. It includes a data field, a threshold value field of the second buffer circuit 92, a queue data field of the second buffer circuit 92, a connection type data field of the second buffer circuit 92, and a new VPI / VCI.

As used herein, the term “first buffering data” refers to one or more of the following fields for the first buffer circuit 46: a threshold value field, a queue data field, and a connection. Means a field for type data.
The term “second buffering data” refers to one or more of the following fields for the second buffer circuit 72: a field for threshold values, a field for queue data, and a field for connection-type data. The more generalized term "
“Buffering data” means one or both of “first buffering data” and “second buffering data”.

FIG. 4 shows various parameters (in parentheses []) included in each field of a record in the database stored in the memory 82. The abbreviations used for the parameters shown in FIG.

As seen in FIG. 4, the core routing data fields include parameters RI (routing information), IDP (implicit delay priority), ICLP (ICL
P implied cell loss priority), MCI, and CID (cell identity). In the illustrated embodiment, the routing information parameter RI holds 14 bits of information used to derive the cell through the switch core. In the direction toward the switch core, the RI parameters are used to address the out port (s) that deliver the cell. Such addressing can be performed in either of two modes: cross-point addressing or table addressing. The choice between these two addressing modes is distinguished by the MCI parameter. FIG. 8A shows the format of the routing information parameter RI for the cross point addressing mode.

FIG. 8B shows the format of the routing information parameter RI for the table addressing mode. In the table addressing mode, the routing information parameter RI contains a pointer to the addressing table. The addressing table holds information necessary to derive a cell. The RI parameter can hold pointers to up to 2 ¹³ -1 table entries, each table entry corresponding to one combination of one or more out ports of the switch core.

The threshold value field in the record 400 can contain one or more threshold values. Typical threshold type values are discarded selected cells and EFCI (Explicit Forward Congestion Identifier).
fier) [see FIG. 4].

As mentioned above, microprocessor 80 constructs records 400 in a database located in database memory 82. Each record is a VPI
/ VCI and information identifying the physical link arriving at the ATM controller 44.

In accessing a database in memory 82 for ATM cells, ATM controller 44 uses data from the appropriate one of records 400 in several ways. First, the ATM controller 44 modifies the standard ATM header 202 with such data to obtain a modified standard ATM header 202 '. Second, the ATM controller 44 augments the switch internal header 204 in the cell, ie,
Prepend. The augmented cell will include the switch 200 as well as the payload 200 and the modified standard ATM header 202 '. As shown in FIG. 2, the switch internal header 204 includes the first buffer circuit 46).
Uses the first buffering data (indicated by reference numeral 206),
Switch core data (reference numeral 208) used by the core 22 and second buffering data (reference number 21) used by the second buffer circuit 72)
0).

The modified standard ATM header 202 ′ contains the new VPI / VCI from the appropriate record 400 from the database stored in the memory 82. ATM switches typically use a VPI / VCI such that the value of the VPI / VCI of the arriving cell is not the same as the VPI / VCI of the cell as it leaves the switch.
Change the value of I.

At the time of receiving a cell, the buffer circuit 46 performs a number of operations using the prepended data included in the cell by the ATM controller 44. Normally, the buffer circuit 4
6 uses the first buffering data 206 for its operation. That is, the first
For items included in the buffering data, buffer circuit 46 uses the connection type data to determine whether the connection should be made at a cell or packet based level. The buffer circuit 46 uses the threshold value to determine whether to buffer or discard the incoming cell. The EC bit in the switch internal header 208 is used to determine whether to mark the cell with EFCI (Explicit Forward Congestion Identifier) if the EFCI threshold has been exceeded. The EFCI bit in the ATM header is set to 1 when there is congestion and EC is true. Queue data is used when buffering cells. This will be described below.

Generally speaking, the first buffer circuit 46 stores the first buffering data 20
From step 6, check which switch port queue to put the ATM cell in. For example, in the embodiment of the entry buffering unit 100 shown in FIG. 3, an ATM cell is stored in one of the switch port queues 110.

Upon leaving the first buffer circuit 46, the ATM cell no longer has the first buffering data 206. This cell is applied to the input port 48 of the switch port 50. At the switch port 50, in the particular example shown, a line code and a checksum (indicated by reference numeral 212) are added to the ATM cell. Line codes are used for synchronization. The checksum is used in determining whether a bit error has occurred during transport through the switch core 22. It will be appreciated that the location and use of the information corresponding to the line code and checksum may be different in other embodiments.

As the ATM cell exits the switch port 50, it is applied to an input 54 of the switch core 22. The switch core 22 is controlled such that the entry-side input terminal 54 for receiving the ATM cell is connected to a desired exit-side output terminal 64 by an internal path in the switch core 22 according to the destination of the ATM cell. You. Switch core 22 can handle simple cross-point connections in point-to-point cells. Otherwise (in the case of point-to-multipoint cells), a reference to the table address may be required to determine a plurality of egress output terminals 64 to which the input terminals 54 should be connected.

Control of the switch core 22 to establish an “interconnect” will be well known to those skilled in the art. Recall that ATM controller 44 has added routing information (eg, RI parameters). The RI parameter contains the destination address of the switch port, which the switch core uses to derive the cell. Point-to-point connections are not set up on the switch core. On the other hand, point-to-multipoint connections must be set up in the switch core. As can be seen with reference to FIG. 8B,
The RI parameter finds an entry in the table for the connection,
Used to determine to which destination port the point-to-multipoint cell is copied.

The ATM cell leaves the switch core 22 and is applied to the egress input terminal 68 of the switch port 50 with the same content as when it entered. Switch port 50
Extract both line code and checksum 212 and core routing data 208. Switch port 50 uses the line code and checksum 212 for synchronization and also determines whether a bit error has occurred during transport through switch core 22. Core routing
Data 208 is deleted because it could serve its purpose, that is, allowing the ATM cell to navigate switch core 22.

When the ATM cell leaves the output terminal 70 on the output side of the switch port 50, the second
It is input to the buffer circuit 72. Upon entering the second buffer circuit 72, the ATM cell has second buffering data 210 (in addition to its payload and modified standard ATM header 202 '). Just as the first buffer circuit 46 utilizes the first buffering data 206, the second buffer circuit 72 uses the second buffering data 210 to check the threshold and to determine its intended destination and class of service. The cell is stored in the queue corresponding to.

In a point-to-point cell, assuming that the controller 44 has provided a VPI / VCI value, the cell header 202 ′ emerging from the second buffer circuit 72 is basically
It is prepared by the ATM controller 44. That is, a new cell header 20
2 'is essentially the ATM header sent with the ATM cell from the switch 20. If congestion occurs at the egress, some exception may occur, such as (for example) a change in the EFCI bit. On the other hand, in a point-to-multipoint cell, FIG.
, The new VPI / VCI value is determined and the header 202 is determined.
'Must be inserted.

In the embodiment described so far, the ATM controller 44 has the (1) first
Buffering data 206 and (2) second buffering data 21
0 were added to the cell. In other embodiments, the ATM controller 44 need not add both the first buffering data 206 and the second buffering data 210, and instead use the buffering data for only one of the circuits 46 and 72. It will be appreciated that in some cases (ie, either the first buffering data 206 or the second buffering data 210) may need to be added. For example, the ATM controller 44 controls the first buffering data 2
If it is desired to add only 06, it can.

It will also be appreciated that other switch embodiments are within the scope of the present invention. For example, the invention also relates to a switch having, for example, a central buffering device in its switch core 22.

In addition, it will be appreciated that there are many techniques and formats for prepending an ATM cell. One such technique illustrated here is to include buffering data in the switch internal header 204 and allow the ATM controller 4
4 to prepend to the ATM cell. If buffering data is to be included in the switch's internal header 204, the internal header will have fields assigned to all of the prepended information, for example, information obtained from a database in the memory 82. FIG. 5 shows an example of the format of a switch internal header of an ATM cell. The internal header contains the buffering data. The format of FIG. 5 is applicable to cells at the entry side of an ATM switch using a 16-bit interface. From FIG. 5, it can be seen that the first buffering data 206, the switch core data 208, and the second buffering data 210 need not be separated in the switch internal header 204, but instead between the fields of the switch internal header 204. It can be seen that the distribution is possible.

The switch internal header 502 of FIG. 5 has the embodiment described in the previous section, ie, the AT
It is directed to an embodiment in which the M controller 44 adds only the first buffering data 206. In an embodiment in which the second buffering data is also included in the cell for the second buffer circuit as described below with reference to FIG. 7, for example, FIG.
Of the switch internal header 500 of FIG. For example, in the internal header of the modified switch, the fields EDP / NSCD T and SCD / EP
D / ET is also added for the second buffer circuit, making the cell 3 bytes longer.
In this embodiment, the fields DP and POL are used in the second buffering circuit to determine which buffer stores the cell.

The switch internal header 208 moves with the ATM cell throughout the switch.
Abbreviations used for the parameters shown in FIG.

FIG. 6 is a flowchart showing steps executed by the buffer circuit 46 for an ATM cell having an internal header 500 (see FIG. 5). In step 600, buffer circuit 46 uses the values of the DP and DSP parameters to determine in which queue in cell buffer 90 to store the cell. As can be seen from Supplementary Material 1, the DP parameter is a delay priority parameter and indicates the delay priority of the cell. DSP parameter is a destination switch port parameters, which switch port is one of the cell destination (e.g., one to switch port 50 ₁ 5 0 _n) contains information about the. Thus, the DP and DSP parameters are a part of the parameters corresponding to the first buffering data 206.

In step 602, the buffer circuit 46 checks the parameter PC and determines whether or not the cell belongs to a packet connection. If the cell does not belong to the packet connection, perform step 604 (and possibly steps 608-612). In step 604, the buffer circuit 46 determines that the counter corresponding to the queue length of the specific queue identified in step 600 is PPD / NSCD T
A determination is made as to whether the value of the parameter has been exceeded. From Supplementary Material 1,
The PPD / NSCD T parameter is a partial packet discard / non-select cell discard threshold and is used to transfer a partial packet discard threshold (for packet connection) or a non-select cell discard threshold (for non-packet connection). It turns out that it is used for. If the counter corresponding to the queue length of the particular queue identified in step 600 exceeds the value of the PPD / NSCD T parameter, execute step 606 and discard the cell. Otherwise, operation proceeds to step 608.

In step 608, the buffer circuit 46 determines whether or not the internal header 500 indicates that cell discarding is permitted by checking the parameter DE.

If the cell discarding is permitted, the buffer circuit 46 determines in step 610
A determination is made as to whether the queue length counter of the subject queue (ie, the queue determined in step 600) has exceeded the congestion threshold. The congestion threshold is ascertained from the parameters SCD / EPD / ET of the inner header 500. The parameters SCD / EPD / ET refer to selected cell discard / early packet discard / EFCI threshold, EFCI and early packet discard threshold (for packet connection) or EFCI and selected cell discard threshold (for non-packet connection) To accommodate.

If it is determined in step 610 that the congestion threshold has been exceeded, in step 612, the buffer circuit 36 determines whether the priority of the cell is low, that is, if the CLP bit in the ATM cell header is “1”. Is determined. This check is important. This is because discarding selected cells means discarding lower priority cells if this threshold is exceeded.

If the determination in step 612 is affirmative, the cell is discarded in step 614. On the other hand, if any of the checks or determinations in steps 608, 610, or 612 is negative, step 616 is performed. At step 616, the cell is stored in the particular queue identified at step 600. Then, after step 616, the queue length counter associated with this particular queue is incremented in step 618.

If it is determined in step 602 that the cell is part of a packet connection, then step 620 is performed. At step 620, a determination is made as to whether the cell is the last cell in the packet. If the cell is the last cell in the packet, step 622 marks this cell as the last cell in internal memory. Otherwise, at step 624, mark this cell as not the last cell. Thus, steps 622 and 624
Respectively, set or clear the "end of message" (EOM) flag (which also means the end of the packet or the last cell of the packet).

Following either step 622 or 624, the flag is checked at step 626 to determine whether a partial packet discard (PPD) is in progress. If partial packet discard is in progress, then execute step 628. At step 628, a check is made as to whether the end of message (EOM) flag is set. This check is important. This is because if partial packet discard is in progress, the last cell must not be discarded. If the check at step 628 is positive, then at step 630,
A further check is made as to whether the counter corresponding to the queue length of the particular queue identified in step 600 has exceeded the value of the PPD / NSCD T parameter (see step 604). If the check at step 628 is negative or the determination at step 630 is positive, the cell is discarded at step 632. Otherwise, step 634 is executed next. In step 634, the cell is stored in the particular queue identified in step 600. Then, in step 636, the queue length counter associated with this particular queue is incremented. At step 638, the flag indicating partial packet discard is cleared.

If it is determined in step 626 that partial packet discard is not in progress, step 640 checks whether early packet discard (EPD) is in progress by checking the early packet discard flag. . If early packet discard is in progress, execute steps 642, 644, and 646. In step 642, the cell is discarded. In step 644, it is checked whether the end of message (EOM) flag is set.
If the determination in step 644 is positive, early packet discard (EPD)
Clear the flag.

Assuming that early packet discarding is not in progress, at step 650 the buffer circuit 46 determines that the counter corresponding to the queue length of the particular queue identified at step 600 has exceeded the value of the PPD / NSCD T parameter. A determination is made as to whether the If so, steps 652, 654, and 656 are performed. In step 652, the cell is discarded. Step 654
Check whether the end of message (EOM) flag is set. If the determination in step 654 is negative, step 65
At 6, set the partial packet discard (PPD) flag.

If the queue length counter value has not been exceeded in step 650, the flag is checked in step 660 to see if the discard allowance is valid. If not, the cell is stored at step 662 and the queue length counter is incremented at step 664. If discard allowance is enabled, then at step 670, a check is made as to whether the queue length counter has exceeded the selected cell discard / early packet discard / EFCI threshold (SCD / EPD / ET). If not, the cell is stored (step 672) and the queue length counter is incremented (step 674). If step 670 is positive, discard the cell (
Step 680), checking whether the end of message (EOM) flag is set. If the flag is set, early packet discard (E
PD) is in progress (step 684).

As can be seen from the above description, in the selection cell discarding, a cell having a low priority (determined by its CLP parameter) is discarded. In early packet discard, the entire packet is discarded.

As can be seen from the description of FIG. 3, the queue for storing cells can be organized and configured in various ways. A typical buffer circuit 46 includes a scheduler and selects a queue to obtain cells to feed into switch core 22 via switch port 50. Usually, the scheduler selects the queue with the highest priority,
Send out the oldest cell stored in the queue. When sending cells into the switch core 22, the queue length counter for the sending queue is decremented.

Although the preceding description has illustrated the use of certain thresholds for individual queues, the present invention contemplates other types of thresholds. For example, the threshold of the entire cell buffer 90 may be used (for example, the total number of cells in all the queues of the cell buffer 90). It is also possible to have a maximum queue length and a congestion threshold for a selected group of queues, for example a particular service class for all connections. A threshold for each connection is also possible. In such a situation, an additional threshold is also used to determine whether to discard the cell. Like the illustrated thresholds, these additional thresholds are also used to enhance ATM cells.

The buffering data is transferred to the first buffer circuit 44 and the second buffer circuit 72.
In the embodiments described above, such as the embodiment of FIG. 1 that supplies both, the buffering data need not be unique for each buffer circuit. However,
In still other embodiments, each buffer circuit may utilize different buffering data, eg, different thresholds.

FIG. 3 shows a particularly representative embodiment of an ingress buffering unit that can be used with the ATM switch of FIG. 1, but it will be appreciated that there are other embodiments. That is, many different buffering / queue architectures can be used. For example, buffering / alignment may be, for example, one queue per connection,
One queue per service class and destination, or per service class.

FIG. 7 shows another embodiment of a switching terminal 24 ′ that includes a second database in the memory 500 and is different from the switching terminal 24 of FIG. The memory 500 (in which the second database is stored) is connected to the second buffer circuit 72. The second database is used for point-to-multipoint connection. At this point, for point-to-multipoint cells, the exit VPI / VCI value at the exit of switch 20 must be added. Adding all outgoing VPI / VCI values to a cell at the entrance (e.g., using ATM controller 44) can cause the cell to be too large to transmit through, for example, switch core 22. For this reason, the outgoing VPI / VCI value is added to the cell in the second buffer circuit 72. VPI / VC
The I value is obtained by a reference operation in a database stored in the memory 500. For this reason, microprocessor 80 is shown connected to both second buffer circuit 72 and data base memory 500.

The size of the memory utilized for the switch 20 depends on the number of connections that must be accommodated and the degree of implementation of the implementation (eg, how many thresholds are used).

Thus, when processing point-to-point cells, the switch 20 of the present invention has only one database, a database stored in the memory 82,
Look up on a look-up basis to obtain routing and buffering data. When processing point-to-multipoint cells, two data bases (memory 82 and 92) are located inside the switch and outside the switch core.
Only). Thus, switch 20 minimizes the need for costly memory and the time spent performing reference operations. Further, since a large number of reference memories are not required, the circuit design of the switch 20 is simplified.

As shown in FIG. 2, the bandwidth of each ATM cell sent to the first buffer circuit 46 (
For example, the size) is the same as that sent to the switch core 22. Therefore, assuming that switch core 22 can handle sufficient bandwidth,
The data required by the components of the switch 20 are transmitted via the switch 20 to the ATM.
All can be transmitted with the cell.

While the present invention has been particularly shown and described with reference to the preferred embodiments, various modifications can be made in form and detail without departing from the spirit and scope of the invention. It will be understood by those skilled in the art. For example, while buffer circuits 46 and 72 are shown as connected to a switch port, other locations for buffer circuits 46 and 72 are possible. For example, buffering circuits 46 and 72 can be included within switch core 22.
Further, the present invention can be put to practical use in an embodiment of a switch that does not use a switch core. In such a coreless embodiment, a central buffer is used to store all cells from all links from all extension terminals. The present invention
For example, coreless implementations where buffering data such as one or both of the first buffering data 206 and the second buffering data 210 as described above are prepended to cells are also contemplated. .

Appendix 1 PPD / NSCD T Partial Packet Discard / Unselected Cell Discard Threshold. This field is used to transfer a partial packet discard threshold (for packet connection) or an unselected cell discard threshold (for non-packet connection). Length: 12
bit. PC packet connection. This field is used to specify whether the cell belongs to a connection carrying AAL5 packets. This information is used to determine whether to discard the packet. Length: 1 bit. DP delay priority. This field is used to transfer information about the delay priority of the cell. This information, along with the destination switch port field, is used to determine the buffer queue in which to store the cell. Length: 6 bits. SCD / EPD / E T Discard Selected Cell / Early Packet Discard / EFCI Threshold. This field is used to transfer the EFCI and early packet discard threshold (for packet connection) or EFCI and selected cell discard threshold (for non-packet connection). Length: 6 bits. POL Physical output link. This field is used to transfer information about the physical link to which the cell should be sent. This information is used for explicit rate calculation. Length: 4 bits.

PIL physical input link. This field is used to transfer information about from which physical link the cell was received. This information is used for explicit rate calculation. Length: 4 bits. EC EFCI marking connection. This field is used to specify whether to mark cells as EFCI when crossing the EFCI threshold.
The EFCI threshold is transferred to the Selected Cell Discard / Early Packet Discard / EFCI Threshold field. Length: 1 bit. CT cell type. This field is used to specify whether the cell is a forward RM cell, a backward RM cell, or not an RM cell. Length: 1 bit. AC ABR connection. This field is used to specify whether the cell belongs to an ABR connection. Length: 1 bit. RI routing information. This field is used to contain the information used to derive the cell through the switch core. Length: 14 bits. IDP Implicit delay priority. This field assigns one of the two loss priority levels and the cell of the established connection one of the two delay priority levels. . Length: 1 bit. ICI Internal channel identifier. This field serves as an internal channel identifier that maps the standardized VPI field at the switch. Length: 15 bits.

ICLP Implied cell loss priority. This field assigns one of the two loss priority levels and the cell of the established connection one of the two loss priority levels. . Length: 1
bit. MCI multicast indication. This field specifies the destination address as a cross-point
Used to indicate whether to interpret as an address or a table address. Length: 1 bit. SAV source address valid. This field is used to indicate the validity of the SA field. Length: 1 bit. SA source address. This field is the number of the input port. Length: 7 bits. CID Cell identity. This field contains an identity code to identify the cell as either an idle cell, alarm cell, traffic cell, or forward RM cell. Length: 3 bits. VCI virtual channel identifier. This field holds no information if switching is performed at the virtual channel level, but holds the VCI value from the standardized cell if switching is performed at the VP level. The AM field is the VCI
Used to determine how to interpret the field. Length: 12 bits.

PT payload type. This field indicates whether the payload is user cell data or OAM data, whether congestion has occurred, and how to set the ATM-layer-user to ATM-layer-user indicator. length:
3 bits. CLP cell loss priority. This field contains the CCITT Recommendation I. 361 (B-ISD
N ATM layer use) and two different cells within the same connection.
Used to assign one of two priority levels. Length: 1 bit. DE can be destroyed. For a packet connection, this field is used to specify whether to perform early packet discard. If not a packet connection, this field is used to specify whether or not to perform discard of the selected cell. Length: 1 bit. DSP Destination switch port. This field is used to transfer information about which switch port to send the cell to. This information, together with the delay priority field, is used to determine the queue in the buffer to store the cell. Length: 7 bits. PAYLOAD Transparent payload. This field is used to store user data. Length: 384 bits.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an ATM switch according to an embodiment of the present invention.

2 is a schematic diagram of the contents of an ATM cell and transmission via the ATM switch of FIG. 1;

FIG. 3 is a configuration diagram of an entrance buffering unit usable with the ATM switch of FIG. 1;

FIG. 4 is a schematic diagram of a database used with the ATM switch of FIG. 1;

FIG. 5 shows an example of an internal switch cell, an ATM employing a 16-bit interface.
It is a schematic diagram of a format applicable to a cell on the entrance side of a switch.

FIG. 6 is a flowchart showing an operation performed in a buffer circuit included in the ATM switch of FIG. 1;

FIG. 7 is a configuration diagram of another embodiment of the exchange terminal of the ATM switch of FIG. 1;

FIG. 8A is a schematic diagram of a format example of a routing information parameter RI for a cross-point addressing mode. B is a schematic diagram of a format example of the routing information parameter RI for the table addressing mode.

[Procedural Amendment] Submission of translation of Article 34 Amendment of the Patent Cooperation Treaty

[Submission date] January 11, 2000 (2000.1.11)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0010

[Correction method] Change

[Correction contents]

[0010] In view of the foregoing, one approach to simplifying cell processing with ATM switches is to limit the total amount of data required for cell transport through the switch. Such limitations can be achieved either by (1) limiting the data per connection, or (2) reducing the number of allowed connections. The first solution is to keep the number of connections allowed,
ATM parameter becomes more course (become more course)
). These two approaches merely reduce the memory size and still require table lookup. Deriving ATM cells via the switch core, and further providing service information to the ATM cells
It is known to add information to ATM cells for the purpose of including a class of
. In this regard, Diaz et al. (Dazs et al.) US Patent No. 5
, 537400 and 5,361,255. July 1997
EP0785697 published on the 23rd discloses a switch structure (switch f).
abc) Change the header of standard ATM cells input to
Output port bitmap, and via one or more stages of the switch fabric
Thus, it is taught to pass from the current position to a desired output port .

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0028

[Correction method] Change

[Correction contents]

When arriving at the ATM controller 44 of the switch 20, the ATM cell has both its payload 200 and its header 202. The ATM controller 44 uses the VPI / VCI portion of the cell header 202 and information about the bull link of the incoming cell as an index in a smart search algorithm (based on a binary search) and is in a database stored in memory 82. An appropriate one is determined from the plurality of records 400. As shown in FIG.
Each record in the second database includes, for example, a field for core routing data, a field for threshold value of the first buffer circuit 46, a field for queue data of the first buffer circuit 46, and a connection of the first buffer circuit 46. Type data field, threshold value field of second buffer circuit 72 , second
Including queue data fields of the buffer circuit 72, connected type data field of the second buffer circuit 72, and a new VPI / VCI.

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] 0070

[Correction method] Change

[Correction contents]

[0070] with reference to the preferred embodiments above, it the present invention have been shown and described specifically, without departing from the scope of the present invention, various modifications are possible in form and detail Will be understood by those skilled in the art. For example, while buffer circuits 46 and 72 are shown as being connected to a switch port, other locations for buffer circuits 46 and 72 are possible. For example, the buffering circuit 46
And 72 can also be included inside the switch core 22. Furthermore,
The present invention can be put to practical use in a switch embodiment that does not use a switch core. In such a coreless embodiment, a central buffer is used to store all cells from all links from all extension terminals. The present invention provides, for example, the first buffering data 206 and the second buffering data 206 as described above.
Also contemplated are coreless implementations in which buffered data, such as either or both data 210, is prepended to cells.

[Procedural Amendment] Submission of translation of Article 34 Amendment of the Patent Cooperation Treaty

[Submission date] January 11, 2000 (2000.1.11)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0001

[Correction method] Deleted

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

──────────────────────────────────────────────────続 き Continuation of front page (81) Designated country EP (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE ), OA (BF, BJ, CF, CG, CI, CM, GA, GN, ML, MR, NE, SN, TD, TG), AP (GH, GM, KE, LS, MW, SD, SZ, UG, ZW), EA (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM), AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY, CA, CH, CN, CU, CZ, DE, DK, EE, ES, FI, GB, GE, GH, GM, GW, HU, ID, IL, IS, JP, KE, KG, KP, KR , KZ, LC, LK, LR, LS, LT, LU, LV, MD, MG, MK, MN, MW, MX, NO, NZ, PL, PT, RO, RU, SD, SE, SG, SI, SK, SL, TJ, TM, TR, TT, UA, UG, UZ, VN, YU, ZW.

Claims (20)

[Claims] 1. An asynchronous transfer mode (ATM) switch, comprising: a controller for augmenting ATM cells with buffered data; and a buffer circuit connected to the controller for receiving the augmented ATM cells. A buffer for storing the ATM cell according to data;
An asynchronous transfer mode switch, comprising: the buffer circuit having a memory. 2. The apparatus further comprising a database connected to the controller, the database having a reference table, wherein the controller determines buffering data using the reference table and performs a reference operation. An apparatus according to claim 1. 3. The apparatus of claim 1, further comprising a switch core through which said ATM cells are passed when deriving. 4. The apparatus of claim 3, wherein the reference operation performed by the controller is the only reference operation performed on the ATM cell before being derived through the switch core. 5. The apparatus of claim 3, wherein said buffer circuit is directly connected to said controller and said switch core. 6. The system further comprising a second buffer circuit connected to receive enhanced ATM cells from the switch core, the second buffer circuit storing the ATM cells in response to the buffered data. 4. The apparatus of claim 3, further comprising: 7. The apparatus of claim 6, further comprising a data base memory for storing VPI / VCI information accessed by said second buffer circuit for inclusion in a multicast ATM cell. 8. The apparatus according to claim 1, wherein the buffering data is at least one of a threshold value, queue data of the buffer circuit, and connection type data. 9. An asynchronous transfer mode (ATM) switch at the entry side of the switch for enhancing ATM cells with buffered data, and at the exit side of the switch for receiving the enhanced ATM cells. A buffer circuit for storing the ATM cells in accordance with the buffering data.
A buffer circuit having a memory, and an asynchronous transfer mode switch comprising: 10. The apparatus of claim 9, further comprising a data base memory for storing VPI / VCI information accessed by said buffer circuit for inclusion in a multicast ATM cell. 11. The apparatus according to claim 9, wherein said buffering data is at least one of a threshold value, queue data of said buffer circuit, and connection type data. 12. The system according to claim 9, further comprising a switch core through which said ATM cell is passed when deriving said ATM cell, wherein said buffer circuit receives said enhanced ATM cell from said switch core.
The described device. 13. A method of operating an Asynchronous Transfer Mode (ATM) switch, comprising: enhancing ATM cells with buffered data; transmitting the enhanced ATM cells to a buffer circuit and responding to the buffer data. Storing the ATM cells in a cell buffer memory. 14. Before augmenting the ATM cell with the buffered data, the method comprises:
14. The method of claim 13, further comprising: performing a lookup operation using the contents of the ATM cell header to obtain the buffered data for the ATM cell. 15. The method of claim 13, further comprising the step of deriving said ATM cell via a switch core after transmitting said enhanced ATM cell to said buffer circuit. 16. The method of claim 15, wherein said reference operation is the only reference operation performed on said ATM cell before deriving through said switch core. 17. Transmitting the enhanced ATM cells from the switch core to a second buffer circuit, wherein the ATM cells are stored in a second cell buffer memory according to the buffering data. The method of claim 15, comprising the step of: 18. In order to include VPI / VCI information in a multicast ATM cell, a VPI
18. The method of claim 17 including the step of accessing a database memory where / VCI information is stored. 19. A method of operating an Asynchronous Transfer Mode (ATM) switch, comprising: augmenting an ATM cell with buffered data; deriving the ATM cell through a switch core; Transmitting a cell from said switch core to a buffer circuit, wherein said ATM cell is stored in a cell buffer memory in response to said buffering data. 20. In order to include VPI / VCI information in a multicast ATM cell,
20. The method of claim 19, comprising the step of accessing a database memory where / VCI information is stored.