JP2001358590A - Analogue-digital converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a double-integrated analogue-digital converter which is less affected by external noise. SOLUTION: An integral voltage V14 provided by continuously integrating an input voltage Vi and a reference voltage VRn is compared with a standard voltage GND by a voltage comparator 17, and a time required for inversion of its comparison result is counted by a counter 23 with the counting result outputted as a digital signal OUT. At the same time, the integral signal V14 is compared with a high voltage and a low voltage which are higher or lower by a specified voltage than the standard voltage GND using voltage comparators 17p and 17n. A difference in time required for inversion of comparison results from the voltage comparators 17 and 17p is measured with a subtracter 24p, a difference in time required for inversion of comparison results from voltage comparators 17 and 17n is measured with a subtracter 24n. If a difference between measurement results of the subtracters 24p and 24n is within a tolerable value, the change rate of the integral voltage 14 is assumed as constant for no effect of noise.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog-to-digital converter (hereinafter referred to as "ADC") for converting an analog voltage into a digital signal, and more particularly to a technique for preventing an error of a double integration type ADC due to external noise. .

[0002]

2. Description of the Related Art FIG. 2 is a configuration diagram of a conventional double integral type ADC. This double integration type ADC has an analog switch 1 for switching and inputting an input voltage Vi to be converted and a reference voltage -Vr. Analog switch 1
Is connected to an operational amplifier 2 constituting a voltage follower. The output side of the operational amplifier 2 is connected via a resistor 3 to an inverting input terminal of an operational amplifier 4. Between the inverting input terminal and the output terminal of the operational amplifier 4,
The capacitor 5 and the analog switch 6 are connected in parallel. The non-inverting input terminal of the operational amplifier 4 is connected to the reference voltage GN.
D, and the output side of the operational amplifier 4 is connected to the first input terminal of the voltage comparator 7. The second input terminal of the voltage comparator 7 is connected to the reference voltage GND, and the output side is connected to the control circuit 8. The control circuit 8 outputs control signals C1 and C6 to the analog switches 1 and 6, and outputs a counter 9 based on the output signal S7 of the voltage comparator 7.
Is output. The counter 9 counts a clock signal (not shown) based on the control signal C9, and the count value of the counter 9 is output as a digital signal OUT corresponding to the input voltage Vi.

FIG. 3 is a signal waveform diagram showing the operation of FIG. In FIG. 3, the integrated voltage V4 on the output side of the operational amplifier 4 when the input voltage Vi is high is indicated by a solid line, and the integrated voltage V4 when the input voltage Vi is low is indicated by a broken line.
First, during the reset period from time 0 to time T0, the analog switch 6 is short-circuited and the capacitor 5 is discharged by the control signal C6 output from the control circuit 8. Since the non-inverting input terminal of the operational amplifier 4 is connected to the reference voltage GND, the potential of the inverting input terminal also becomes the reference voltage GND, and the integrated voltage V4 becomes the reference voltage GND (that is, 0 V). Next, at time T0, the analog switch 6 is opened by the control signal C6, and the control signal C1
Thus, the input voltage Vi side of the analog switch 1 is selected. Accordingly, the current flowing from the output side of the operational amplifier 2 to the resistor 3 is Vi / R (where R is the resistance value of the resistor 3).
Becomes In the ideal operational amplifier 4, the potential of the inverting input terminal is the reference voltage GND and the input impedance is infinite, so that all the current flowing through the resistor 3 is charged in the capacitor 5. Therefore, the integrated voltage V4 after a fixed time t1 of the first integration period becomes-(1 / CR) Vi.t1 (where C is the capacitance of the capacitor 5).

The time T1 when the time t1 has elapsed from the time T0
, The second integration period is started. The control circuit 8 outputs a control signal C9 for starting the counting operation to the counter 9 and switches the analog switch 1 to the reference voltage -Vr side by the control signal C1. As a result, the output of the operational amplifier 2
, A current of -Vr / R flows. Time t2 from time T1
Is obtained as shown in the equation (1). V4 = − (1 / CR) Vi · t1 + (1 / CR) Vr · t2 (1) When the integrated voltage V4 becomes equal to the reference voltage GND, the signal S7 is output from the voltage comparator 7 to the control circuit 8. Then, the control circuit 8 stops the control signal C9 and stops the operation of the counter 9. From the equation (1), the time t2 is as shown in the equation (2). t2 = (Vi / Vr) t1 (2) Since Vr and t1 are predetermined constant values, the time t2 is proportional to the input voltage Vi, and the digital signal OUT output from the counter 9 is , The input voltage Vi.

[0005]

However, the conventional double integration type ADC has the following problems. When noise is input from outside during the conversion operation, the voltage charged in the capacitor 5 is affected. Since the first integration period is set to a predetermined time in advance, if a period that is an integral multiple of a period of assumed power supply noise or the like is set, the positive component and the negative component of the noise cancel each other. It is possible. However, since the second integration period changes in proportion to the input voltage Vi, external noise cannot be canceled. For this reason, there is a problem that a conversion error occurs due to external noise. An object of the present invention is to solve the problems of the prior art and to provide a double integration type ADC which is less affected by external noise.

[0006]

According to a first aspect of the present invention, there is provided an ACD in which an analog voltage to be converted and a reference voltage having a polarity different from that of the analog voltage are switched. Switching means for sequentially outputting, an integration means for continuously integrating the analog voltage and the reference voltage output from the switching means to generate an integrated voltage, and a first means for comparing the integrated voltage with a reference voltage First comparing means for outputting a comparison result; second comparing means for comparing the integrated voltage with a voltage higher than the reference voltage by a constant voltage to output a second comparison result; A third comparing means for outputting a third comparison result by comparing the voltage with a voltage lower than the reference voltage by a constant voltage, and a time period from the start of integration of the reference voltage by the integrating means to inversion of the first comparison result. Time Counting means for counting the time and outputting a counting result as a digital signal corresponding to the analog voltage; first measuring means for measuring a difference between times when the first and second comparison results are inverted; And second measuring means for measuring a difference between times when the third comparison result is inverted,
Comparing means for comparing the measurement results of the first and second measuring means and determining whether or not the difference is an allowable value.

[0007] According to the first invention, as described above, the ADC
, The following operation is performed. First, an analog voltage to be converted is output from the switching means and integrated by the integrating means. Subsequently, the reference voltage is output from the switching means, and is continuously integrated by the integrating means. The integration voltage generated by the integration means is compared with the reference voltage by the first comparison means, and a first comparison result is output. The time from the start of integration of the reference voltage by the integrating means to the inversion of the first comparison result is counted by the counting means, and the counting result is output as a digital signal. On the other hand, the integrated voltage is compared with a voltage higher than the reference voltage by a fixed voltage by the second comparing means, and a second comparison result is outputted. A voltage lower than the reference voltage by the fixed voltage is outputted by the third comparing means. And a third comparison result is output. The first measuring means measures the time difference between the inversion of the first and second comparison results, and the second measuring means measures the difference between the first and third times.
The difference between the times when the result of the comparison is inverted is measured. The measurement results of the first and second measuring means are compared by the comparing means, and it is determined whether or not the difference is an allowable value. An ADC according to a second aspect of the present invention includes a switching unit, an integrating unit, first, second, and third comparing units, a counting unit, and a second or third comparing result similar to those of the first aspect. And external control means for outputting a control signal for stopping operation to an external circuit serving as a noise generation source after the inversion and before the first comparison result is inverted.

According to the second aspect, the following operation is performed. First, an analog voltage to be converted is output from the switching means and integrated by the integrating means. Subsequently, the reference voltage is output from the switching means, and is continuously integrated by the integrating means. The integration voltage generated by the integration means is compared with the reference voltage by the first comparison means, and a first comparison result is output. The time from the start of integration of the reference voltage by the integrating means to the inversion of the first comparison result is counted by the counting means, and the counting result is output as a digital signal. On the other hand, the integrated voltage is compared with a voltage higher than the reference voltage by a fixed voltage by the second comparing means, and a second comparison result is outputted. A voltage lower than the reference voltage by the fixed voltage is outputted by the third comparing means. And a third comparison result is output. The second and third comparison results are given to an external control means, and the first or second comparison result is inverted and the first and second comparison results are inverted.
Until the comparison result is inverted, a control signal for stopping an external circuit serving as a noise generation source is output.

[0009]

FIG. 1 is a block diagram of a double integration type ADC showing an embodiment of the present invention. This double integral type AD
C is switching means (for example, an analog switch) for switching and inputting the analog input voltage Vi to be converted and the positive reference voltage VRp (for example, +10 V) or the negative reference voltage VRn (for example, -10 V). ) 11. The output side of the analog switch 11 is connected to an operational amplifier 12 constituting a voltage follower, and the output side of the operational amplifier 12 is connected to integrating means (for example, a resistor 1).
3, the operational amplifier 14, and the resistor 13 of the capacitor 15)
, Is connected to the inverting input terminal of the operational amplifier 14. A capacitor 15 and an analog switch 16 are connected in parallel between the inverting input terminal and the output terminal of the operational amplifier 14. The non-inverting input terminal of the operational amplifier 14 is connected to a reference voltage GND (for example, 0 V), and the output side of the operational amplifier 14 is a comparator (for example, a voltage comparator).
17, 17p, and 17n are commonly connected to the first input terminals.

The second input terminal of the voltage comparator 17 is connected to the reference voltage GND. A second input terminal of the voltage comparator 17p has a reference voltage VRpp (for example, +1 V) generated by dividing the reference voltage VRp by the resistors 18a and 18b.
And a second input terminal of the voltage comparator 17n is supplied with a reference voltage VRnn (for example, -1 V) generated by dividing the reference voltage VRn by the resistors 19a and 19b. These reference voltages VRpp and VRnn are set to voltages having opposite polarities and equal absolute values to the reference voltage GND. A control processing circuit 20 and an external control means (for example, an external control circuit) 30 are connected to the output sides of the voltage comparators 17, 17p, and 17n. Control processing circuit 20
Is an exclusive OR gate (hereinafter, referred to as “EOR”) 2
1, 21p, and 21n, and the output sides of the voltage comparators 17, 17p, and 17n are connected to these first input terminals, respectively. The second of EOR21, 21p, 21n
A selection signal SL2 to be described later is commonly supplied to the input terminals, and these EORs 21, 21p, and
The output side of 21n is connected to first input terminals of AND gates 22, 22p, and 22n each having two inputs. AND22, 22p, 22n
Is supplied with an enable signal EN.

The output sides of the ANDs 22, 22p and 22n are:
Each of the counting means (for example, a counter) 23, 23p, and 23n is connected to an enable terminal E. The reset terminals R of the counters 23, 23p, 23n have reset signals RS for resetting their count values to 0.
T is commonly given. Counter 2
3, 23p, 23n are AND22, 22p,
22n applied to the enable terminal E from the
According to S22p and S22n, a common clock signal (not shown) is counted, and the count value is output from the output terminal Q. The output side of the counters 23 and 23p is
It is connected to the input side of the first measuring means (for example, a subtractor) 24p. The outputs of the counters 23 and 23n are connected to the input of the second measuring means (for example, a subtractor) 24n. The subtracters 24p and 24n calculate the difference between the two values given to the input side, respectively.
The output sides of these subtracters 24p and 24n are connected to the input side of a comparison means (for example, a comparator) 25. The comparator 25 determines whether or not the difference between the two values given to the input side is an allowable value. The comparison result of the comparator 25 and the count value of the counter 23 are given to the data latch 26. Data latch 26
Holds and outputs given data based on the latch signal LAT.

The control processing circuit 20 has a control unit 27 for controlling processing timing based on a common clock signal. The control unit 27 closes the analog switch 16 to discharge the capacitor 15 prior to the conversion process, and resets the count values of the counters 23, 23p, and 23n to an initial value (that is, 0).
T is output. Further, the control unit 27 switches the analog switch 11 to the input signal Vi by the selection signal SL1.
Side to start the first integration period.
The control unit 27 selects a reference voltage to be used in the second integration period based on the polarity of the voltage charged in the capacitor 15 in the first integration period, and also controls the comparators 17, 17p, and 17n.
Has a function of outputting a selection signal SL2 for performing inversion control of the output signal. Further, the control unit 27 has a function of outputting an enable signal EN for operating the counters 23, 23p, and 23n, and a latch signal LAT for holding data of a conversion result and outputting it as a digital signal OUT. I have. The external control circuit 30 has a stop signal ST for stopping the operation of the external circuit only in a minimum time zone in which the count operation is easily affected in order to avoid a malfunction at the time of counting due to external noise.
P is output. The external control circuit 30
31 and a two-input AND 32. EOR3
The input side of 1 is connected to the output side of the comparators 17p and 17n. The output side of EOR31 and AND22 is AND3
The stop signal STP is output from the output side of the AND 32 and supplied to the external circuit 40.

FIG. 4 is a signal waveform diagram showing the operation of each section in FIG. Hereinafter, the operation of FIG. 1 will be described separately with reference to FIG. 4 as (I) the operation of the control processing circuit 20 and (II) the operation of the external control circuit 30. Note that the input voltage V
It is assumed that i is a positive voltage. (I) Operation of Control Processing Circuit 20 During the reset period from time 0 to time T0, the control unit 27
Outputs a reset signal RST from the counters 23 and 2
3p and 23n are reset, the analog switch 16 is short-circuited, and the capacitor 15 is discharged. Since the non-inverting input terminal of the operational amplifier 14 is connected to the reference voltage GND, the potential of the inverting input terminal also becomes the reference voltage GND, and the integrated voltage V14 on the output side of the operational amplifier 14 becomes the reference voltage GND (that is, 0 V). Becomes At time T0, the reset signal RST is released, the analog switch 16 is opened, and the input voltage Vi of the analog switch 11 is selected by the selection signal SL1. As a result, a current flows from the output side of the operational amplifier 12 to the resistor 13. Assuming that the operational amplifier 14 is ideal,
The potential of the inverting input terminal is the reference voltage GND, and the input impedance is infinite.
Then, the current flowing through the resistor 13 has a constant value of Vi / R. The current flowing through the resistor 13 charges the capacitor 15. Assuming that the capacitance of the capacitor 15 is C, the integrated voltage V14 after a fixed time t1 in the first integration period becomes −
Vi · t1 / CR.

Time T1 when time t1 has elapsed from time T0
In this case, since the integrated voltage V14 is a negative value, the output signals of the voltage comparators 17, 17p, and 17n have the level "L".
Becomes The output signal of voltage comparator 17 is applied to control unit 27, which determines that input voltage Vi is positive. Thereby, the selection signal SL1 for switching the analog switch 11 to the negative reference voltage VRn.
And a selection signal SL2 of “L” for inverting the output signals of the voltage comparators 17, 17p, and 17n is output from the control unit 27. At the same time, the control unit 27 outputs an enable signal EN for starting the counting operation of each of the counters 23, 23p, 23n. Each AND22,
Signals S22, S22p,
S22n attains the level "H" and the counters 23, 23
p and 23n start counting the common clock signal.

When the second integration period is started in this way, the output voltage of the operational amplifier 12 becomes the negative reference voltage VRn, and a current of VRn / R flows through the resistor 13. Therefore,
The integrated voltage V14 after the time t has elapsed from the time T1 is
It is expressed as the following equation (3). V14 = − (1 / CR) Vi · t1 + (1 / CR) VRn · t (3) As shown in the equation (3), the integrated voltage V14 keeps increasing at a constant increasing rate. When the integrated voltage V14 reaches the reference voltage VRnn at time T2, the output signal of the voltage comparator 17n is inverted, the output signal S22n of the AND 22n becomes "L", and the operation of the counter 23n stops. When the integrated voltage V14 becomes the reference voltage GND at time T3, the output signal of the voltage comparator 17 is inverted, the output signal S22 of the AND 22 becomes "L", and the operation of the counter 23 stops. Time T
Assuming that the elapsed time from 1 to time T3 is t2, time t
2 is obtained from equation (3) as follows. t2 = (Vi / VRn) t1 Here, since VRn and t1 are predetermined constant values, the time t2 is proportional to the input voltage Vi, and the counter 23
Is a value corresponding to the input voltage Vi.

At time T4, the integrated voltage V14 becomes equal to the reference voltage VR.
When pp reaches pp, the output signal of the voltage comparator 17p is inverted, the output signal S22p of the AND 22p becomes "L", and the operation of the counter 23p stops. Counter 23n, 2
The count value of 3 is given to the subtractor 24n, and the difference, that is, the value corresponding to the time t21 from time T2 to time T3 is calculated. Further, the count values of the counters 23 and 23p are given to a subtractor 24p, and a difference between them, that is, a value corresponding to a time t22 from time T3 to time T4 is calculated. Further, the values calculated by the subtracters 24n and 24p are provided to a comparator 25 to determine whether or not the value is an allowable value, and the result of the comparison is provided to a data latch 26. At time T5, when the latch signal LAT is output from the control unit 27, the data latch 26 holds the comparison determination result of the comparator 25 and the count value of the counter 23,
It is output as a digital signal OUT.

Here, if there is no influence of external noise, the second
The rate of increase of the integration voltage V14 during the integration period is constant. Further, the integrated voltage V14 from time T2 to time T3.
(That is, the reference voltage VRnn) and the rise of the integrated voltage V14 from time T3 to time T4 (that is, the reference voltage VRpp) are set to be equal. Therefore, according to the comparison determination result of the comparator 25, the time t21 and the time t22
Are determined to be different, it can be considered that the influence of external noise occurs during this period, and the count value of the counter 23 is affected by the external noise. On the other hand, if it is determined that the difference between the time t21 and the time t22 is an allowable value, it can be considered that the count value of the counter 23 is not affected by external noise. It should be noted that the absolute value of the input voltage Vi is small and the voltage at the time T1 is equal to the reference voltage V14, like the integral voltage V14 shown by the broken line in FIG.
If it is higher than Rnn, the valid time t21 cannot be counted, and the comparator 25 determines that it is out of the allowable value. In this case, since the count value of the counter 23 is a small value corresponding to the input voltage Vi, the count value may be regarded as a conversion result without referring to the comparison determination result of the comparator 25.

(II) Operation of External Control Circuit 30 At time T2 in FIG.
When the voltage reaches Rnn, the output signal of the voltage comparator 17n is inverted, and the output signal of the EOR 31 in the external control circuit 30 becomes "H". At this time, since the output signal S22 of the AND 22 is "H", the output signal of the AND 32 is "H", which is used as the stop signal STP in the external circuit 4.
0 is given. As a result, the operation of the external circuit 40 is temporarily stopped, and the influence of external noise is completely eliminated. Time T
In 3, when the second integration period ends and the output signal S22 of the AND 22 becomes "L", the output signal of the AND 32 becomes "L" and the stop signal STP is released. Thus, the operation of the external circuit 40 is restarted. In the above description of the operation, the input voltage Vi has been described as a positive voltage, but substantially the same operation is performed with a negative voltage. However, during the first integration period, the integration voltage V14 is charged to a positive voltage.
Thereby, in the second integration period, the positive reference voltage VRp is selected by the selection signal SL1 and the selection signal S
L2 is set to "H" and the voltage comparators 17, 17p,
The 17n output signal is not inverted, and
2, 22p, 22n. Other operations are the same as the case where the input voltage Vi is a positive voltage.

As described above, the double integral type AD of this embodiment is used.
C has the following advantages (1) and (2). (1) In order to determine whether the rate of increase of the integrated voltage V14 is constant during the second integration period, in addition to the ADC original voltage comparator 17 and the counter 23, the voltage comparator 17
p, 17n, counters 23p, 23n, subtractor 24p,
24n and a comparator 25 are provided. Thus, the influence of external noise can be determined based on whether or not the rate of increase of the integrated voltage V14 is constant. (2) During the second integration period, the external circuit 40 is provided only during a predetermined voltage immediately before the integration voltage V14 reaches the reference voltage GND.
Is provided with an external control circuit 30 for stopping the operation. This makes it possible to stop the operation of the external circuit 40 only in the minimum time period in which the count operation is easily affected, and to reduce the influence on the external circuit 40 and prevent malfunction. it can.

The present invention is not limited to the above embodiment, but can be variously modified. For example, there are the following modifications (a) to (e). (A) Although the input voltage Vi having a positive or negative polarity is configured to be convertible, the present invention is also applicable to a device that converts only one of the polarities. (B) The configuration of the control processing circuit 20 is not limited to the configuration in FIG. For example, the time T in FIG.
If the time t21 from 2 to T3 is counted and the time t22 from time T3 to T4 is counted by the counter 23p, the subtracters 24n and 24p become unnecessary. (C) If it is possible to completely stop external noise by the external control circuit 30, a component for determining the influence of external noise in the control processing circuit 20 (for example,
The counters 23p and 23n, the comparator 25, etc.) can be eliminated. (D) When there is no external circuit that generates noise that affects the conversion operation, or when it is impossible to stop the external circuit 40, the external control circuit 30 is unnecessary. (E) The control processing circuit 20 and the external control circuit 30 are configured by hardware such as logic gates, but may be controlled by software using a microprocessor or the like.

[0021]

As described above in detail, according to the first aspect, the second and third comparing means for comparing the integrated voltage with a voltage higher and lower by a fixed voltage than the reference voltage, It has first and second measuring means and comparing means for determining whether or not the rate of change of the integrated voltage is constant based on the comparison result of the second and third comparing means. This makes it possible to determine whether or not the conversion result is affected by external noise. According to the second invention, the second and third comparing means for comparing the integrated voltage with a voltage higher and lower by a fixed voltage than the reference voltage, and the comparison result of the second or third comparing means is provided. An external control unit that outputs a control signal for stopping the external circuit from the inversion to the inversion of the first comparison result is provided. As a result, the influence of external noise can be suppressed, and a correct conversion result can be obtained.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a double integration type ADC showing an embodiment of the present invention.

FIG. 2 is a configuration diagram of a conventional double integration type ADC.

FIG. 3 is a signal waveform diagram showing the operation of FIG.

FIG. 4 is a signal waveform diagram illustrating an operation of each unit in FIG. 1;

[Explanation of symbols]

 11, 16 Analog switch 12, 14 Operational amplifier 13 Resistor 15 Capacitor 17, 17n, 17p Voltage comparator 23, 23n, 23p Counter 24n, 24p Subtractor 25 Comparator 30 External control circuit 40 External circuit

Claims (2)

[Claims] 1. A switching unit for switching an analog voltage to be converted and a reference voltage having a polarity different from that of the analog voltage and sequentially outputting the analog voltage, and continuously integrating the analog voltage and the reference voltage output from the switching unit. Integrating means for generating an integrated voltage by comparing the integrated voltage with a reference voltage and outputting a first comparison result; and a voltage higher than the reference voltage by a constant voltage. A second comparing unit that outputs a second comparison result by comparing with the third comparison unit; and a third comparing unit that outputs the third comparison result by comparing the integrated voltage with a voltage lower than the reference voltage by a constant voltage. Counting the time from the start of integration of the reference voltage by the integration means to the inversion of the first comparison result, and outputting the counting result as a digital signal corresponding to the analog voltage A step, a first measuring means for measuring a difference between times when the first and second comparison results are inverted, and a second measurement for measuring a difference between times when the first and third comparison results are inverted. Means for comparing the measurement results of the first and second measurement means to determine whether or not the difference is an allowable value. 2. A switching unit for switching and sequentially outputting an analog voltage to be converted and a reference voltage having a polarity different from that of the analog voltage, and continuously integrating the analog voltage and the reference voltage output from the switching unit. Integrating means for generating an integrated voltage by comparing the integrated voltage with a reference voltage and outputting a first comparison result; and a voltage higher than the reference voltage by a constant voltage. A second comparing unit that outputs a second comparison result by comparing with the third comparison unit; and a third comparing unit that outputs the third comparison result by comparing the integrated voltage with a voltage lower than the reference voltage by a constant voltage. Counting the time from the start of integration of the reference voltage by the integration means to the inversion of the first comparison result, and outputting the counting result as a digital signal corresponding to the analog voltage Wherein the stage, from the second or third comparison result is inverted first
An external control means for outputting a control signal for stopping operation to an external circuit serving as a noise generation source until the result of the comparison is inverted.