JP2001358413A - Electric circuit board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electric circuit board wherein the amount of charges accumulated between a through hole and a signal line or a ground line can be reduced without increasing impedance of the signal line or the ground line. SOLUTION: In the electric circuit board 511, a wiring pattern layer 511a is laminated via an insulating layer 511b, and through holes 511c insulated from the wiring pattern layer 511a via the insulating layer 511b are arranged. An outer peripheral edge of the through hole 511c is circular, and an insulating layer outer peripheral edge 511a1 of the wiring pattern layer 511a is not circular. A part βsandwiched by the insulating layer outer peripheral edges 511a1 is formed with almost constant width D.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed circuit board, a ceramic substrate and other electric circuit boards, and more particularly to an electric circuit board capable of reducing the amount of electric charge accumulated between a through hole and a signal line or a ground line.

[0002]

2. Description of the Related Art In an electronic component test apparatus called a handler, a large number of ICs stored in a tray are transported into the test apparatus, and each IC is pressed against a terminal of a socket connected to a test head. Test equipment (tester, test
er) to perform the test. When the test is completed,
By unloading C from the test process and replacing it on a tray according to the test result, sorting into categories such as non-defective products and defective products is performed.

Here, the test head is provided with a large number of printed boards, and is used for transmitting and receiving test signals between the tester and the test head when the IC is pressed against the socket.

A conventional printed circuit board P is, as shown in FIG.
As shown in FIG. 10 and FIG. 10, a large number of pattern layers P1 including signal lines and / or power lines (including ground lines; the same applies hereinafter) are laminated via an insulating layer P2,
A through hole P3 is provided as needed.

[0005]

However, in the conventional printed circuit board P, the gap d between the through hole P3 and the pattern layer P1 including the signal line or the power supply line is narrow, and the gap d serves as a capacitor, and electric charge is generated. There is a problem that the waveform of the test signal fluctuates as a result.

If the gap d is increased, the accumulation of electric charges is prevented. However, the gap D between the outer peripheral edges P4 of the adjacent insulating layers in the pattern layer P1 is reduced.
This causes an increase in impedance in the pattern layer P1 of the signal line or the pattern layer P1 of the power supply line, causing a problem that noise is generated.

[0007]

SUMMARY OF THE INVENTION The present invention provides an electric circuit board capable of reducing the amount of electric charge accumulated between a through-hole and a signal or power supply line without increasing the impedance of the signal or power supply line. The purpose is to do.

According to a first aspect of the present invention, a pattern layer including a signal line and / or a power supply line is laminated via an insulating layer, and a through hole insulated from the pattern layer via the insulating layer is formed. An electric circuit board having an irregular interval between an outer edge of the through hole and an inner edge of the pattern layer.

According to a second aspect of the present invention, a pattern layer including a signal line and / or a power supply line is laminated via an insulating layer, and the through layer is insulated from the pattern layer via the insulating layer. An electric circuit board having holes, wherein an outer peripheral edge of the through hole is circular, and an outer peripheral edge of an insulating layer between the pattern layer and the through hole is non-circular.

Further, according to a third aspect of the present invention, a plurality of pattern layers including signal lines and / or power supply lines are laminated via an insulating layer, and are insulated from the pattern layer via the insulating layer. An electric circuit board having a through hole, wherein an outer peripheral edge of the insulating layer between the pattern layer and the through hole, and a portion sandwiched between the outer peripheral edge of the insulating layer adjacent thereto are substantially constant. An electrical circuit board formed with a width is provided.

In the above invention, although not particularly limited, it is more preferable that the insulating layer contains polytetrafluoroethylene as a main component.

[0012]

A pseudo capacitor made of an insulating layer is formed between the through hole and the pattern layer including the signal line and / or the power supply line, and the electric charge is stored here by the current flowing through the signal line and / or the power supply line. . The capacitance C of this charge is proportional to the dielectric constant ε of the insulating layer and the facing area S between the through hole and the pattern layer, and is inversely proportional to the distance d between the through hole and the pattern layer. That is, if the dielectric constant ε of the insulating layer and the facing area S between the through hole and the pattern layer are small and the distance d between the through hole and the pattern layer is large, the amount of accumulated charges can be suppressed, and the signal waveform varies. Can be prevented.

On the other hand, in a pattern layer including a signal line and / or a power supply line, an interval between a portion between an outer peripheral edge of the insulating layer between the pattern layer and the through hole and an outer peripheral edge of the insulating layer adjacent thereto. The larger the value of D, the lower the impedance of the pattern layer and the more the occurrence of noise can be prevented.

According to the present invention, in the pattern layer including the signal line and / or the power supply line, a portion sandwiched between the outer peripheral edge of the insulating layer between the pattern layer and the through hole and the outer peripheral edge of the insulating layer adjacent thereto. Is increased as much as possible, and at the same time, the distance d between the through hole and the pattern layer is increased as much as possible. Furthermore, the dielectric constant ε of the insulating layer is reduced by forming the insulating layer from a material containing polytetrafluoroethylene as a main component.

[0015] Accordingly, noise caused by a small interval D between the outer peripheral edges of adjacent insulating layers can be suppressed, and at the same time, electric charges are accumulated in the insulating layer between the through hole and the pattern layer. The variation of the signal waveform caused by the above can also be suppressed.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a side view showing an electronic component test apparatus to which the electric circuit board of the present invention is applied, FIG. 2 is a detailed sectional view of the test head shown in FIG. 1, and FIG. FIG. 3 is a sectional view taken along line II-III of FIG.

As shown in FIG. 1, an electronic component test apparatus to which the electric circuit board of the present invention is applied is, for example, an IC under test.
, A test head 5 that makes electrical contact with the IC under test, and a tester 6 that sends a test signal to the test head 5 and executes a test on the IC under test. . This electronic component testing device is
IC with high or low temperature stress applied to C
Is a device that tests (inspects) whether the IC operates properly and classifies ICs according to the test results.

As shown in FIGS. 2 and 3, the test head 5 has a connector 5
A base board 502 is mounted via a base plate 02a, and a spacing frame 503 is provided above the base board 502 via a space column 502b capable of slightly moving up and down in the Z-axis direction.

A socket board 505 is provided above the spacing frame 503 via a socket board spacer 504, and a sub socket board 511 is provided above the spacing frame 503 via a sub socket board spacer 513. I have.

The base board 502 and the socket board 505 are connected by a plurality of coaxial cables 506, and the socket board 505 and the sub-socket board 511 are connected by a relay terminal 512.

FIG. 2 is a sectional view of the test head 5 as viewed in the X-axis direction. In FIG. 2, two sets of the socket board 505 and the sub-socket board 511 are shown in the Y-axis direction.
Although only the actual test head 5 of 4 rows × 16 columns is shown, four sets of socket boards 505 and sub socket boards 511 are provided in the Y-axis direction.

FIG. 3 is a sectional view of the test head 5 as viewed in the Y-axis direction. In FIG. 3, a set of a socket board 505 and a sub-socket board 511 are arranged in the X-axis direction.
Although only the actual test head 5 of 4 rows × 16 columns is shown, eight sets of socket boards 505 and sub socket boards 511 are provided in the X-axis direction.

At the top of each sub-socket board 511,
An IC socket 510 and a socket guide 514 are provided as needed. The IC socket 510 has a plurality of contact pins that contact input / output terminals of the IC under test, and is connected to lands or the like formed on the upper surface of the sub socket board 511. Also, the socket guide 514 is
A guide for positioning the IC under test when the IC under test contacts the contact pins of the IC socket 510, and may be omitted in some cases.

FIG. 4 is a view showing an example of a wiring pattern layer 511a of a sub-socket board 511 which is an electric circuit board of the present invention. FIG. 5 is an enlarged view of an outer peripheral edge 511a1 of the wiring pattern layer 511a shown in FIG. FIG. 6 is a cross-sectional view (corresponding to a VI-VI line in FIG. 7) showing a sub-socket board 511 which is an electric circuit board of the present invention. FIG. 7 is a cross-sectional view taken along the line VII-VII in FIG. FIG. 8 shows VIII-VIII in FIG.
It is sectional drawing which follows a line. Hereinafter, the electric circuit board of the present invention will be described with reference to FIGS.
An embodiment of the present invention will be described with reference to an example applied to FIG.

As shown in the cross-sectional view of FIG. 6, the sub-socket board 511 has a wiring pattern layer on which a wiring pattern including a signal line and / or a power supply line (including a ground line) is formed via an insulating layer. 511a in the same figure indicates a wiring pattern layer including signal lines and / or power supply lines, and 511bc indicates an insulating layer. Also, a large number of through holes 511c penetrating the front and back of the sub-socket board 511 are formed, and an insulating layer 511b is interposed between the through hole 511c and the wiring pattern layer 511a to form the through hole 511c.
And the wiring pattern layer 511a are electrically insulated.

The insulating layer 511b can be made of an insulating material such as glass or epoxy. However, if the insulating layer 511b is made of, for example, polytetrafluoroethylene having a lower dielectric constant than that of these materials, the insulating layer 511b will The capacitance of the pseudo capacitor formed therebetween is reduced, and thereby, the fluctuation of the waveform of the test signal can be further suppressed.

FIG. 4 is a plan view showing an example of the wiring pattern layer 511a, and 511a1 is an outer peripheral edge of the insulating layer, which is enlarged in FIG.

In the wiring pattern layer 511 of the sub socket board 511 of this embodiment, the outer peripheral edge 511a1 of the insulating layer is non-circular. This shape maximizes the width D between the adjacent insulating layer outer peripheral edges 511a1 and 511a1 shown in FIG. 5, and minimizes the distance d1 between the through hole 511c and the insulating layer outer peripheral edge 511a1 shown in FIGS. What is necessary is just a shape which becomes large.

In this embodiment, when the outer peripheral edge 511a1 of the insulating layer is formed as a circle having a radius R as shown by a dotted line in FIG. 5, the width between the outer peripheral edges 511a1 and 511a1 of the adjacent insulating layer becomes D1.
The portion β is formed as a straight line so that the width β becomes larger and the width D becomes constant. This is because the width between the adjacent insulating layer outer peripheral edges 511a1 and 511a1 is D
1, the wiring pattern layer 511 is formed in this portion β.
This is because the impedance of “a” increases, and particularly in an electric circuit board used for the test head 5 of the electronic component test apparatus, noise may be generated in a precise and severe test signal, and an accurate test may not be performed. In that sense, the shape of the insulating layer outer peripheral edge 511a1 of the present invention is not limited to that shown in FIG. 5, and the width D between the adjacent insulating layer outer peripheral edges 511a1 and 511a1 is equal to the wiring pattern layer 511a. What is necessary is just to be formed large enough not to increase the impedance. At this time, the shape does not have to maintain the constant width D.

Further, the insulating layer outer peripheral edge 511a1 of this embodiment is formed linearly at the portion β where the adjacent insulating layer outer peripheral edge 511a1 exists as described above, but the insulating layer outer peripheral edge 511a1 is not adjacent. As for the portion α, the distance from the through hole 511c is as large as possible.
It consists of a circle with a larger radius than the conventional one. That is, assuming that the radius of the conventional insulating layer outer peripheral edge 511a1 shown in FIG. 10 is r and the radius of the present example is R, it is desirable that r <R. This is because the pseudo capacitor formed of the through hole 511c, the wiring pattern layer 511a, and the insulating layer 51b therebetween has a through hole 511c.
By increasing the distance d2 between c and the wiring pattern layer 511a (see FIG. 7 and FIG. 8), the capacitance of the pseudo capacitor is reduced, thereby suppressing the fluctuation of the test signal waveform. is there.

As described above, in the sub-socket board 511 of this embodiment, the outer peripheral edge 511a1 of the insulating layer and the outer peripheral edge 51 of the insulating layer adjacent thereto in the wiring pattern layer 511a.
1a1, the distance D between the portions β sandwiched between the through holes 511c and the wiring pattern layer 511 is increased.
The distances d1 and d2 with respect to “a” are made as large as possible. Furthermore, the dielectric constant ε of the insulating layer 511b is reduced by forming the insulating layer 511b from a material containing polytetrafluoroethylene as a main component.

Thus, the outer peripheral edge 511 of the adjacent insulating layer is formed.
Noise generated due to a small interval D between a1 and 511a1 can be suppressed, and at the same time, a signal waveform fluctuation caused due to accumulation of charges in the insulating layer 511b between the through hole 511c and the wiring pattern layer 511a. Can also be suppressed.

The embodiments described above are described for the purpose of facilitating the understanding of the present invention, but are not described for limiting the present invention. Therefore, each element disclosed in the above embodiment is intended to include all design changes and equivalents belonging to the technical scope of the present invention.

In the above-described embodiment, an example in which the present invention is applied to the sub-socket board 511 has been described. However, the electric circuit board of the present invention is not limited to the sub-socket board 511 and can be applied to other substrates. Furthermore, it is not limited only to the electric circuit board used in the electronic component test apparatus,
The present invention can be applied to general printed boards, ceramic boards, and other electric circuit boards.

[0035]

As described above, according to the present invention, it is possible to suppress noise generated due to a small interval D between the outer peripheral edges of adjacent insulating layers, and at the same time, to suppress the insulating layer between the through hole and the pattern layer. In addition, it is possible to suppress the fluctuation of the signal waveform caused by the accumulation of the electric charges.

[Brief description of the drawings]

FIG. 1 is a side view showing an electronic component test apparatus using an electric circuit board of the present invention.

FIG. 2 is a detailed sectional view showing the test head of FIG.

FIG. 3 is a sectional view taken along line II-III in FIG.

FIG. 4 is a diagram showing an example of a wiring pattern layer of the electric circuit board of the present invention.

FIG. 5 is a partially enlarged view of the wiring pattern layer shown in FIG.

FIG. 6 is a sectional view showing an electric circuit board of the present invention.

FIG. 7 is a sectional view taken along the line VII-VII in FIG. 6;

FIG. 8 is a sectional view taken along the line VIII-VIII in FIG. 7;

FIG. 9 is a cross-sectional view showing a conventional electric circuit board.

FIG. 10 is a sectional view taken along line XX of FIG. 9;

[Explanation of symbols]

 511: Sub socket board (electric circuit board) 511a: Wiring pattern layer (pattern layer) 511a1: Outer edge of insulating layer 511b: Insulating layer 511c: Through hole

Claims (5)

[Claims] 1. An electric circuit board comprising: a pattern layer including a signal line and / or a power supply line laminated via an insulating layer; and a through hole insulated from the pattern layer via the insulating layer. An electric circuit board in which the distance between the outer periphery of the through hole and the inner periphery of the pattern layer is not constant. 2. An electric circuit board, comprising: a pattern layer including a signal line and / or a power supply line laminated via an insulating layer; and a through hole insulated from the pattern layer via the insulating layer. An electric circuit board, wherein an outer peripheral edge of a through hole is circular, and an outer peripheral edge of an insulating layer between the pattern layer and the through hole is non-circular. 3. An electric circuit board comprising: a plurality of pattern layers including signal lines and / or power supply lines laminated via an insulating layer; and a plurality of through holes insulated from the pattern layer via the insulating layer. An electric circuit board, wherein a portion sandwiched between an outer peripheral edge of an insulating layer between the pattern layer and the through hole and an outer peripheral edge of an insulating layer adjacent thereto is formed with a substantially constant width. 4. The electric circuit board according to claim 1, wherein said insulating layer contains polytetrafluoroethylene as a main component. 5. An electronic component test apparatus having the electric circuit board according to claim 1.