JP2001350389A - Synchronous clock generator and image forming device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To flexibly cope with the subsequent set up hold to which a synchronous clock signal and synchronous image data are supplied. SOLUTION: A first clock selecting part 4 inputs a BD signal to generate a first synchronous clock signal SCK1 which is synchronous with the BD signal. A second synchronous clock signal generating part 5 generates a second synchronous clock signal SCK2 which is controlled to have a predetermined phase deference from the first signal SCK1 based on a selection signal RP. The predetermined phase difference can be selected for each 1/N (N is natural number) of a cycle of the first synchronous clock signal SCK1. An SW6 supplies an FIFO7 with the first synchronous clock signal SCK1 or second synchronous clock signal SCK2 as a read clock. Image data Do is read according to the read clock.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous clock generator and an image forming apparatus, and more particularly, to a synchronous clock generator for generating a clock signal synchronized with a trigger signal and reading out an image from a storage means, and using the generator. The present invention relates to an image forming apparatus.

[0002]

2. Description of the Related Art In an apparatus (hereinafter, referred to as an electrophotographic apparatus) for forming an image by an electrophotographic method such as a digital copying machine or a laser beam printer (LBP), a beam detect (BD) signal as paper end information is transmitted. An image is formed by outputting the image in synchronization with. An electrophotographic image forming system will be briefly described with reference to FIG.

FIG. 14 shows an example of a laser beam printer. A photodiode 140 in FIG. 14 monitors a laser beam output from a semiconductor laser 141 as a laser light source. The light amount control unit 142 controls the current applied to the semiconductor laser 141 based on the monitored light amount, as described below, and controls the output from the photodiode 140 to be a predetermined value.

The polygon mirror 143 is a semiconductor laser 14
14 for deflecting the laser beam I emitted from the light source 1 and driven by being fixed to a motor shaft, rotating clockwise in FIG. Form a latent image. f-θ lens 1
44, a laser beam I deflected by the photosensitive drum 145;
It converges on top.

A beam detector 146 composed of a light receiving diode receives the laser beam I, detects the information writing start position on the photosensitive drum 145, and supplies a detection signal to a horizontal synchronizing signal generation circuit 147. The horizontal synchronizing signal generation circuit 147 generates a horizontal synchronizing signal HSync based on the detection signal of the beam detector 146.

A blanking circuit 148 generates an unblanking signal UNBL for turning on the semiconductor laser 141 at the next timing when the beam detector 146 should detect the laser beam I, based on the horizontal synchronizing signal HSync. 149.

[0007] The pixel modulation circuit 151 is based on the pixel modulation data generated from the pixel modulation data source 150, and is a pulse width modulated image signal synchronized with the pixel clock SCK generated in synchronization with the horizontal synchronization signal HSync. Generate DV.

The pulse width modulated image signal DV supplied from the pixel modulation circuit 151 is also input to the OR circuit 149. The output from the OR circuit 149 is the laser driver 15
2, whereby the applied current set by the light quantity control unit 142 is supplied to the semiconductor laser 141.

The pixel modulation data source 150 outputs pixel modulation data (image signal) DV representing, for example, 8 bits of pixel gradation in synchronization with a pixel clock generated in synchronization with the horizontal synchronization signal HSync. Is output.

FIG. 15 shows an example of a block configuration of the pixel modulation data source 150.

In FIG. 15, reference numeral 155 denotes an X'TAL oscillator for oscillating the same frequency as the pixel clock, and the above-mentioned horizontal synchronizing signal H is inputted as a trigger signal as a BD signal.
Sync. Synchronous clock generation IC 156
The TAL oscillator 155 internally generates a clock signal asynchronous with the BD signal, and generates a synchronous clock SCK synchronized with the trigger edge of the BD signal. As the synchronization accuracy J of this synchronization clock with respect to the phase of the BD signal (FIG. 16),
It is said that, for example, a color printer or the like needs about 画素 of the pixel clock cycle in order to obtain a desired image quality.

If digital processing is to be performed at a clock cycle, a clock signal eight times the pixel clock frequency is required as a processing reference in order to obtain a synchronization accuracy of 1/8 of the pixel clock cycle. In recent years, the image clock is required to be 50 MHz or more for high speed and high image quality.
Since a gate array that can be processed by z cannot be realized, a dedicated LSI is used.

The synchronous clock SCK is input to a read clock input terminal of the storage element 157. Storage element 1
57 can be composed of, for example, a FIFO memory. A WCK signal is input to a write clock of the storage element 157, and Din of, for example, 8 bits is input to input data.
The video data written to the storage element 157 by WCK and Din is speed-converted at the timing of the synchronous clock SCK and output. As described above, the pixel modulation data generation source 150 can be configured using the two LSIs of the synchronous clock generation IC 156 and the storage element 157.

FIG. 16 shows the relationship between the BD signal, the synchronous clock SCK and the output video data Do.

When a BD signal, which is a horizontal synchronization signal, is input, a synchronization clock SCK is output with a delay time width of (constant time Tx) + (synchronization accuracy J). Tx may be a fixed value. Video data Do output from the storage element 157 is output with a time delay of Td with respect to the synchronous clock SCK. The delay time Td includes at least the delay time of the read clock input buffer in the storage element 157, the clock-output delay time of the data latch flip-flop, and the delay time of the video data output buffer. This delay time Td is
Variations in the manufacturing process of the storage element 157, power supply voltage,
The MIN and MAX values vary greatly depending on the temperature characteristics.

[0016]

With the recent increase in pixel clock speed, these variations cause a problem that the setup and hold of the next-stage pixel modulator 151 cannot be satisfied. In addition, even when the variation in the phase relationship between the video data Do and the synchronous clock SCK is small, a problem still occurs if the setup and hold time of the next-stage pixel modulation unit 151 is long.

For the purpose of high-speed output, one photosensitive drum 145 shown in FIG. 14 is used, and as shown in FIG.
4, 55, polygon mirrors 56, 57, 58, 59, B
There has been proposed a four-drum type electrophotographic apparatus which includes D mirrors 60, 61, 62, 63 and the like and obtains a color image in one pass of paper.

In FIG. 17, BD mirrors 60, 61,
Distances Lc, Lm, Ly, Lk from 62, 63 to paper edge
Causes an error between the YMCK colors. Therefore, FIG.
, The pixel clocks YSCK, MSC for each color
K, CSCK, KSCK are converted to BD signals YBD, MBD, C
Even when synchronized with BD and KBD, the pixel alignment of each color is shifted due to the above-mentioned errors of Lc, Lm, Ly and Lk.

In order to correct this color shift, a synchronous clock is generated for each of the photosensitive drums 52, 53, 54 and 55, and video data is output in synchronization with these synchronous clocks. A method of correcting a positional shift between the respective drums by delaying a clock or the like is employed.

However, although the synchronous clock delay means can be realized by tap selection using a delay line, since the selected tap is fixed, automatic adjustment or the like corresponding to environmental changes or the like was impossible.

An object of the present invention is to provide a synchronous clock generator and an image forming apparatus which can solve the above-mentioned problems and can flexibly cope with a next-stage setup and hold to which a synchronous clock signal and synchronous image data are supplied. With the goal.

[0022]

According to a first aspect of the present invention, there is provided a synchronous clock generator for reading out image data stored in a storage unit based on a synchronous signal serving as a reference of an image forming position. A first synchronization clock generating means for receiving the synchronization signal and generating a first synchronization clock signal synchronized with the synchronization signal;
Means for generating a second synchronous clock signal controlled to a predetermined phase difference from said synchronous clock signal, wherein said predetermined phase difference is calculated every 1 / N (N is a natural number) of a cycle of said first synchronous clock signal. A second synchronous clock generating means, which can be selected as a read clock, and a read means for supplying either one of the first or second synchronous clock signal to the storage means as a read clock. A synchronous clock generator for reading the image data from the means is provided.

According to a second aspect of the present invention, in the synchronous clock generating apparatus according to the first aspect, the first synchronous clock generating means includes an N-phase clock having a uniform phase difference and the synchronous signal. A synchronous clock generator that generates the first synchronous clock signal having a phase difference with respect to the synchronous signal at a fixed timing based on the first synchronous clock signal.

According to a third aspect of the present invention, in the synchronous clock generating device according to the first aspect, the second synchronous clock generating means receives the first synchronous clock signal and receives each of the first synchronous clock signals. A synchronous clock generator comprising: means for outputting an N-phase clock having a phase difference; and selection output means for selecting one of the N-phase clocks having the predetermined phase difference and outputting the selected clock as the second synchronous clock signal. Provide equipment.

According to a fourth aspect of the present invention, in the synchronous clock generating apparatus according to the first aspect, the read means supplies the first synchronous clock signal to the storage means as the read clock as the read clock. A synchronous clock generating device for reading data and outputting the first synchronous clock signal or the second synchronous clock signal with 1 / N accuracy with respect to the read image data.

According to a fifth aspect of the present invention, in the synchronous clock generating apparatus according to the third aspect, a plurality of the synchronous signals are prepared as a reference for a plurality of image forming positions, and the selection output means includes a plurality of the selective output means. Selecting and outputting the N-phase clock having a phase difference corresponding to an image forming position, reading the image data by supplying the second synchronous clock signal to the storage unit as the read clock as the read clock; The first synchronous clock signal or the second synchronous clock signal;
And a synchronous clock generator for outputting the synchronous clock signal.

According to a sixth aspect of the present invention, in the synchronous clock generating device according to the first aspect, the storage means, the first synchronous clock generating means, the second synchronous clock generating means, and the reading means are provided. Are provided on the same semiconductor chip.

According to a seventh aspect of the present invention, there is provided a means for reading out image data stored in a storage means based on a synchronization signal serving as a reference for an image forming position. First synchronizing clock signal generating means for generating a first synchronizing clock signal synchronized with the first synchronizing clock signal, and means for generating a second synchronizing clock signal controlled at a predetermined phase difference from the first synchronizing clock signal, A second synchronous clock generating means capable of selecting the predetermined phase difference for every 1 / N (N is a natural number) of a cycle of the first synchronous clock signal; A reading means for supplying any one of the reading means as the reading clock to the storage means, a synchronous clock generating means for reading the image data from the storage means according to the reading clock, A light source that emits light in accordance with the image data from the synchronous clock generator, a photosensitive member that forms a latent image by deflecting and irradiating a beam from the light source, and a nearby position of the photosensitive member in the deflection direction. And a synchronizing means for receiving the beam and generating the synchronizing signal.

According to an eighth aspect of the present invention, in the image forming apparatus according to the seventh aspect, the first synchronous clock generating means outputs the N-phase clock having a uniform phase difference and the synchronous signal. An image forming apparatus that generates the first synchronization clock signal having a phase difference with respect to the synchronization signal at a fixed timing based on the synchronization signal.

According to a ninth aspect of the present invention, in the image forming apparatus according to the seventh aspect, the second synchronous clock generating means receives the first synchronous clock signal and receives the first synchronous clock signal. Means for outputting an N-phase clock having
A selection output unit that selects one of the N-phase clocks having the predetermined phase difference and outputs the selected one as the second synchronization clock signal.

According to a tenth aspect of the present invention, in the image forming apparatus according to the first aspect, the readout unit supplies the first synchronous clock signal to the storage unit as the readout clock as the readout clock. And outputting the first synchronous clock signal or the second synchronous clock signal with 1 / N precision with respect to the read image data.

According to an eleventh aspect of the present invention, in the image forming apparatus of the ninth aspect, the light source, the photosensitive member, and the synchronizing means are provided for each of a plurality of images, and the synchronizing signal is A plurality of reference positions for forming the plurality of images are prepared, the selection output means selects and outputs the N-phase clocks having a phase difference corresponding to the plurality of image formation positions, and the reading means sets An image forming apparatus that reads out the image data by supplying the second synchronous clock signal to the storage unit as the read clock and outputs the first synchronous clock signal or the second synchronous clock signal.

According to a twelfth aspect of the present invention, in the image forming apparatus according to the seventh aspect, the storing means, the first synchronous clock generating means, the second synchronous clock generating means, and the reading means are provided. Provided is an image forming apparatus provided on the same semiconductor chip.

[0034]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIG. 1 is a block diagram showing a first embodiment of a synchronous clock generator according to the present invention. The embodiment of FIG. 1 is formed on the same LSI chip through the same manufacturing process, and is an example in which the synchronization accuracy is designed to be 1/16 of the pixel clock cycle.

In FIG. 1, reference numeral 1 denotes an X'TAL (crystal) oscillator (XO) which generates a clock signal CKX having a frequency corresponding to the oscillation frequency of the X'TAL oscillator 2. The clock signal CKX is supplied to a multi-phase clock generator (DLY1) 3, which is a first synchronous clock signal generator.

FIG. 2 shows an example of the configuration of the multi-phase clock generator 3. Clock signal C input to polyphase clock generator 3
KX is supplied to the variable delay group 20, and the logic gates 11 and 12. The variable delay group 20 includes variable delay circuits (Δ1) 201 to (Δ15) 215 each having the same configuration and the same delay amount.
Are connected in series 15 times.

FIG. 3 shows a configuration example of the variable delay circuit.
In FIG. 3, Q1 and Q4 are current source transistors that generate currents of the same current value, and are formed by field effect transistors (hereinafter, transistors). This current value is
It is controlled by the voltage values of the control reference voltages VBP and VBN.

The clock signal CK input to the input terminal IN
X is inverted by an inverter composed of transistors Q2 and Q3. At this time, the drive current of the transistors Q2 and Q3 is determined by the current value of the constant current source transistors Q1 and Q4, and the charge / discharge time of the parasitic capacitance at the point A can be changed by the current value. The voltage at the point A is inverted again by the inverter composed of the transistors Q5 and Q6, shaped into a waveform, and output to the variable delay circuit at the subsequent stage. Clock signal CKX is delayed for a predetermined time by the above configuration.

The variable delay circuit 20 of the variable delay group 20 shown in FIG.
Control reference voltages VBP and VBN are supplied to 1 to 215, respectively, and the predetermined times are controlled to the same delay amount. Hereinafter, the delay amount control will be described.

The logic gates 11 and 12 detect the amount of delay. The logic gate 11 is a NAND gate, and one input terminal has an input clock CKX (= SCK).
1 (0)) and the inverted signal of the output SCK1 (1) of the first variable delay circuit 201 is input to the other input terminal. The logic gate 12 is an AND gate. One input terminal receives an inverted signal of the input clock CKX (= SCK1 (0)), and the other input terminal outputs the output SCK1 (15) of the fifteenth variable delay circuit 215. Is entered. Outputs C and P of logic gates 11 and 12 are coupled to charge pump circuit (CP) 13.

FIG. 5 shows a configuration example of the charge pump circuit 13.
FIG. 6 shows a timing chart of waveforms at various parts of the circuit for explaining the operation. In FIG. 5, Q10 is a constant current source transistor driven by the control reference voltage VB2.

The output signal C of the NAND gate 11 is supplied to the gate of the transistor Q21. The transistor Q21 is turned on during a period when the signal C is at a low level, that is, for a time corresponding to the delay amount of the first variable delay circuit 201. ,
The capacitor C1 is charged (FIG. 6). Further, the output signal P of the AND gate 12 is supplied to the gate of the transistor Q22, and corresponds to a section where the signal P is at a high level, that is, the phase difference between the output of the fifteenth variable delay circuit 215 and the input clock signal CKX. Time, transistor Q2
2 turns on and discharges the charge of the capacitor C1 (FIG. 6).

The transistors Q16, Q17, Q1 shown in FIG.
8, Q19 are transistors Q20, Q2, respectively.
It is manufactured as a copy of the same size as 1, Q22, Q23. The common gate voltage of transistors Q23 and Q19 is determined by the current value of constant current source transistor Q10. The gate and source of the transistor Q15 are connected to the gates of the transistors Q20 and Q16. A differential amplifier is formed by the transistors Q12 and Q13, and an amplified output is obtained at the transistor Q15.
Transistors Q17 and Q18 are connected to this differential amplifier input.
And Vcc / 2 as a reference voltage.

The common drain voltage of transistors Q17 and Q18 is equal to the current of transistor Q16 and transistor Q1.
The current changes according to the current relationship of No. 9 and rises when I16> I19 and falls when I16 <I19. That is,
Feedback is applied so as to be stable at the point of I16 = I19, whereby the charge / discharge current of the charge pump circuit 13 is made equal.

Therefore, the output signal Vcp of the charge pump circuit 13 includes the “time T1 corresponding to the delay amount of the first variable delay circuit 201” and the “15th variable delay circuit 2”.
When the time T2 corresponding to the phase difference between the output of No. 15 and the input clock signal CKX is equal, control is performed so as to be stable.

Here, the variable delay circuits 201 to 215 have the same delay amount as described above. Therefore, the fact that the phase difference between the output of the final delay circuit 215 and the input clock CKX is controlled to be equal to the variable delay circuit delay amount means that the 15 variable delay circuits 201 to 2 with respect to the input clock CKX.
15 is 1/1 of the input clock cycle
6 is controlled.

The output Vcp of the charge pump circuit 13 is smoothed by a low-pass filter (LPF) 14 and is controlled by a bias conversion circuit (Ierr) 15 to control a reference voltage VB.
It is converted to P, VBN. Control reference voltages VBP, VBN
Is input to the variable delay group 20, the delay amount of each variable delay circuit can be controlled.

FIG. 7 shows a configuration example of the bias conversion circuit (Ierr) 15. 7, Ve input from LPF 14 is converted into an error current by a voltage-current conversion amplifier, and this error current is added or subtracted by the current of constant current source transistor Q10 given by control reference voltage VB2.

The current I11 obtained by adding or subtracting the error current flows through the transistor Q11, passes through a circuit having the same configuration as the circuit shown in FIG. 5, and is controlled so that the same current flows through the transistors Q17 and Q18. Channel control reference voltage VBP is applied to the gate of transistor Q16, and N-channel control reference voltage VBN is applied to transistor Q1.
9 is output to the gate.

Returning to FIG. 1, the multi-phase clock groups (SCK1 (0) to SCK (1)
5)) are supplied to a first clock selection unit (SEL) 4.

FIG. 8 shows an example of the configuration of the first clock selection unit 4, and FIG. 9 shows details of the output unit.

In the first clock selection unit 4 of FIG.
The multiphase clock signals CK0 to CK15 are supplied to D input terminals of D flip-flops (DFF) 17 to 32 and input terminals of three-input AND gates 33 to 48, respectively. The non-inverted output Q of the DFF to which the N-th multi-phase clock is supplied is also the N-th multi-phase clock SCK1 (N-
1) is supplied to another input terminal of the three-input AND gate to which is input. The remaining input terminals of the AND gate are N
The inverted output / Q of the D flip-flop is provided.

The 16th (last) AND gate 48 has the 16th polyphase clock SCK1 (15), the non-inverted output Q of the 16th D flip-flop 32, and 1
The inverted output / Q of the DFF 17 is combined.

Each of the clock input terminals of the D flip-flops 17 to 32 is supplied with a synchronization signal BD (horizontal synchronization signal HSync) from a horizontal synchronization signal generator (not shown). Using the rising edge of the BD signal as a trigger input, the D flip-flops 17 to 32 output a latch result corresponding to the state of each D input terminal from the non-inverting output terminal Q.

Multi-phase clocks SCK1 (0) to SCK1
(15) exists with a phase difference as shown in FIG. That is, the Nth and (N + 1) th phase differences of 16
Since the double time is one cycle of each phase clock, B
The latch result of the D flip-flop by the trigger edge of the D signal is as shown in FIG. In FIG. 11, Q
(N) represents the state of the output Q of the (N-16) th D flip-flop in FIG.

According to the configuration of FIG. 8, when Q (N) = 1 (high level) and Q (N + 1) = 0 (low level), the N-th multi-phase clock SCK1 (N-1) becomes N The signal is output from the SK (N-1) output of the AND gate, and 0 is output from the other AND gate outputs. Here, N
= 1 to 16 and N + 1 = 17 when N + 1 = 17
= 1.

Therefore, each output SK from the AND gates 33 to 48 is controlled by the OR gate 49 (FIG. 9) of the output section.
By taking the logical sum of 0 to SK15, a clock is selected within an error range of 1/16 of the pixel clock cycle with respect to the input phase of the BD signal, and the selected first synchronous clock signal SCK1 is converted to the first clock. Output from the selection unit 4. The first synchronous clock signal SCK1 is, as shown in FIG.
Of the synchronous clock signal generator (DLY2) 5 and the input terminal 6a of the switch SW6.

The second synchronous clock signal generator 5 has the configuration shown in FIG.
As shown in FIG. 2, a second variable delay group 120 formed as a copy having exactly the same configuration as the variable delay group 20 in FIG.
And a second clock selection unit (SEL) 125.
The second clock selection unit (SEL) 125 is configured by a multiplexer.

Similarly, control reference voltages VBP and VBN are supplied to the second variable delay group 120 as delay amount control voltages, and the variable delay circuits (Δ0) 1201 to (Δ15) 1
The amount of delay at 215 is uniformly set to 1/16 of the pixel clock cycle. Therefore, the second variable delay group 120
Clock outputs SCK2 (0) to SCK2 (1
5) is (To / 16) * with respect to the input phase of SCK1.
There are N phase differences (N = 0, 1, 2,..., 15).
Here, To represents the period of each synchronous clock.

The second clock selector 125 of the second synchronous clock signal generator 5 has the second synchronous signal,
The selection signal RP for selecting an arbitrary phase in the multi-phase clock group is input. The RP signal is a selection signal composed of 4 bits, and the second clock selection unit 125 generates a second multi-phase clock group SCK2 according to the selection signal RP.
(0) to SCK2 (15), and the 16-phase second synchronous clock signal SCK whose delay is controlled as described above with respect to the input first synchronous clock signal SCK1.
Output as 2.

The second synchronous clock signal SCK2 is the first synchronous clock signal SCK2.
Is supplied to the input terminal 6b of SW6 to which the synchronous clock signal SCK1 is supplied. SW6 is switched by the clock selection signal S. In this embodiment, S = 0. At this time, SW6 connects input terminal 6a to output terminal 6c.
, And selectively outputs the first synchronous clock signal SCK1 having a fixed phase for each color BD signal. SW6
Is coupled to the read clock input terminal of the FIFO memory 7, and the first synchronous clock signal SCK1 is supplied as the FIFO read clock.

The FIFO memory 7 stores 8 bits from the Din terminal.
The video data written with the bit input data according to the write clock WCK is read at the timing of the synchronous clock of the output of SW6. Output data Do from the FIFO memory 7 is output to the outside of the LSI via the output buffer 8. On the other hand, the first synchronous clock SCK1 has the same delay time τ via the output buffer 9 having the same configuration as the output buffer 8, and the second synchronous clock SCK has the same delay time τ via the output buffer 10 having the same configuration as the output buffer 8. The output is added to the outside of the LSI. The phase of the output second synchronous clock SCK2 is controlled with To / 16 precision by selecting the 4-bit selection signal RP as described above.

According to the present embodiment having the above configuration,
Since the delay time in the switch SW6 can be almost ignored, the synchronous clock signal SCK output outside the LSI
1, SCK2 and output data Do from FIFO memory 7
The phase difference between them is only the read clock-output delay time of the FIFO memory 7 and can be minimized.
Therefore, it is possible to flexibly cope with the setup and hold time of the data clock of the next-stage pixel modulator (not shown).

(Second Embodiment) FIG. 13 is a timing chart for explaining a synchronous clock generator according to a second embodiment of the present invention.

In a four-drum type electrophotographic apparatus,
It is necessary to perform color misregistration correction between each color (YMCK). The timing chart of FIG. 18 shows that a color shift occurs when the pixel clock is synchronized with the BD signal for each color.

Therefore, in the present embodiment, in the configuration shown in FIG. 1, the selection signal S of the switch SW6 is set to the high level to make the input terminal 6b conductive with the output terminal 6c, and the phase delay of each color BD signal is controlled. 2 synchronous clock signal SCK
2 is selectively output. In the phase control in the first clock selection unit 4, since the phase can be controlled with the To / 16 precision as described above by selecting the 4-bit selection signal RP to a predetermined value, the BD signal YBD for each color as shown in FIG. , M
Delay amounts dY, dM, d for BD, CBD, KBD
C and dK can be controlled with To / 16 accuracy.

Therefore, according to the present embodiment, it is possible to correct a color shift for each color due to a BD mirror position error in the four-drum system. Further, according to the method of the present embodiment, for example, the color misregistration can be electrically corrected by the 4-bit selection signal RP, so that it can be applied to an automatic adjustment system or the like according to an environmental change or the like.

[0068]

According to the synchronous clock generating apparatus and the image forming apparatus of the present invention, the first synchronous clock signal synchronized with the synchronous signal serving as the reference of the image forming position is generated, and the first synchronous clock is generated. A second synchronous clock signal having a predetermined phase difference is generated every 1 / N (N is a natural number) of the signal period, and any one of these clocks can be used as a read clock from the storage means to read image data. The phase of the synchronous clock signal and the synchronous image data synchronized with the synchronous signal can be set to 1 / N, and it is possible to flexibly cope with the next-stage setup and hold to which the synchronous clock signal and the synchronous image data are supplied.

Further, according to the apparatus of the present invention, in which a plurality of light sources, photosensitive members, and synchronization means are provided for each of a plurality of image colors, and a plurality of synchronization signals are prepared as a reference for the formation positions of a plurality of images, Color shift that is synchronized with the synchronization signal can be electrically selected and adjusted with 1 / N precision of the synchronization clock period, so that a high quality image without color shift can be obtained. A synchronous clock generator for a forming apparatus and a color image forming apparatus can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of a synchronous clock generator according to the present invention.

FIG. 2 is a block diagram of a first multi-phase clock generation unit according to the first embodiment.

FIG. 3 is a circuit diagram of a variable delay circuit in a first multi-phase clock generator in the first embodiment.

FIG. 4 is a timing chart illustrating the operation of the first embodiment.

FIG. 5 is a circuit diagram of a charge pump circuit in the first multi-phase clock generator in the first embodiment.

FIG. 6 is a timing chart of the charge pump circuit according to the first embodiment.

FIG. 7 is a circuit diagram of a bias conversion circuit in the first multi-phase clock generation unit according to the first embodiment.

FIG. 8 is a block diagram of a clock selection unit according to the first embodiment.

FIG. 9 is a block diagram of an output unit of a clock selection unit according to the first embodiment.

FIG. 10 is a timing chart of a first multiphase clock in the first embodiment.

FIG. 11 is an explanatory diagram illustrating a result of latching a first multi-phase clock by a clock selection unit according to the first embodiment.

FIG. 12 is a block diagram of a second synchronous clock signal generator in the first embodiment.

FIG. 13 is a timing chart illustrating a second embodiment of the synchronous clock generator according to the present invention.

FIG. 14 is a configuration diagram illustrating a configuration of an electrophotographic apparatus.

FIG. 15 is a block diagram illustrating a conventional example.

FIG. 16 is a timing chart illustrating a conventional example.

FIG. 17 is an explanatory diagram for explaining a problem of a four-drum system in a conventional example.

FIG. 18 is a timing chart for explaining a problem of the method shown in FIG. 17;

[Explanation of symbols]

 Reference Signs List 1 X'TAL oscillator (XO) 2 X'TAL oscillator 3 Multi-phase clock generator (DLY1) 4 First clock selector (SEL) 5 Second synchronous clock signal generator 6 Switch SW 7 FIFO memory 8, 9, 10 output buffer 11 NAND gate 12 AND gate 13 charge pump circuit (CP) 14 low-pass filter 15 bias conversion circuit (Ierr) 20, 120 variable delay group 125 second clock selection unit (SEL) 145 photosensitive drum 146 beam detector 147 Horizontal synchronization signal generation circuit 148 Blanking circuit 150 Pixel modulation data generation source 151 Pixel modulation circuit

Claims (12)

[Claims] 1. A synchronous clock generator for reading out image data stored in a storage unit based on a synchronous signal serving as a reference of an image forming position, wherein the synchronous signal is inputted, and a first synchronous clock synchronized with the synchronous signal is inputted. First synchronous clock generating means for generating a synchronous clock signal; and means for generating a second synchronous clock signal controlled to have a predetermined phase difference from the first synchronous clock signal. 1 / cycle of the cycle of the first synchronous clock signal
A second synchronous clock generating means which can be selected for each N (N is a natural number); and a read means for supplying either the first or second synchronous clock signal as a read clock to the storage means. A synchronous clock generator for reading the image data from the storage unit in accordance with the read clock. 2. The synchronous clock generating device according to claim 1, wherein said first synchronous clock generating means generates said synchronous signal based on an N-phase clock having a uniform phase difference and said synchronous signal. Wherein the first synchronous clock signal having a phase difference with respect to the first synchronous clock signal is generated. 3. The synchronous clock generating apparatus according to claim 1, wherein said second synchronous clock generating means receives said first synchronous clock signal, and receives said first synchronous clock signal, and each of said N-phase clocks has a uniform phase difference. And a selection output means for selecting one of the N-phase clocks having the predetermined phase difference and outputting the selected one as the second synchronization clock signal. 4. The synchronous clock generating device according to claim 1, wherein the read unit reads the image data by supplying the first synchronous clock signal to the storage unit as the read clock. A synchronous clock signal, or the second synchronous clock signal having 1 / N accuracy with respect to the read image data. 5. The synchronous clock generating device according to claim 3, wherein a plurality of said synchronous signals are prepared as a reference for a plurality of image forming positions, and said selection output means is a position corresponding to said plurality of image forming positions. Selecting and outputting the N-phase clock having a phase difference; the reading means reading out the image data by supplying the second synchronous clock signal to the storage means as the readout clock; the first synchronous clock signal; Alternatively, the synchronous clock generator outputs the second synchronous clock signal. 6. The synchronous clock generating device according to claim 1, wherein the storage unit, the first synchronous clock generating unit, the second synchronous clock generating unit, and the reading unit are provided on a same semiconductor chip. A synchronous clock generator. 7. A means for reading out image data stored in a storage means on the basis of a synchronization signal serving as a reference for an image forming position, wherein said synchronization signal is input and a first synchronization synchronized with said synchronization signal is provided. First synchronous clock generating means for generating a clock signal; and means for generating a second synchronous clock signal controlled to have a predetermined phase difference from the first synchronous clock signal, wherein the predetermined phase difference is determined by the second synchronous clock signal. A second synchronous clock generating means which can be selected every 1 / N (N is a natural number) of the cycle of one synchronous clock signal, and wherein either one of the first or second synchronous clock signal is used as a read clock and A synchronous clock generator for reading the image data from the memory in accordance with the read clock; and a synchronous clock generator. A light source that emits light in accordance with the image data from the light source; a photosensitive member that forms a latent image by deflecting and irradiating a beam from the light source; and a photosensitive member that is provided at a position near the photosensitive member in the deflection direction; An image forming apparatus comprising: a synchronizing means for receiving the beam and generating the synchronizing signal. 8. The image forming apparatus according to claim 7, wherein the first synchronization clock generation unit generates the synchronization signal based on an N-phase clock having a uniform phase difference and the synchronization signal. An image forming apparatus for generating the first synchronous clock signal having a phase difference at a constant timing. 9. The image forming apparatus according to claim 7, wherein said second synchronous clock generating means receives said first synchronous clock signal and outputs an N-phase clock having a uniform phase difference. An image forming apparatus comprising: an output unit; and a selection output unit that selects one of the N-phase clocks having the predetermined phase difference and outputs the selected one as the second synchronous clock signal. 10. The image forming apparatus according to claim 1, wherein the read unit reads the image data by supplying the first synchronous clock signal to the storage unit as the read clock as the read clock. An image forming apparatus for outputting a synchronous clock signal or the second synchronous clock signal having 1 / N precision with respect to the read image data. 11. The image forming apparatus according to claim 9, wherein the light source, the photoconductor, and the synchronization unit are provided for each of a plurality of images, and the synchronization signal is used for forming the plurality of images. A plurality of positions are prepared as a reference for the position, the selection output unit selects and outputs the N-phase clock having a phase difference corresponding to the plurality of image forming positions, and the reading unit outputs the second synchronous clock signal. The image forming apparatus reads the image data by supplying the image data to the storage unit as a read clock and outputs the first synchronous clock signal or the second synchronous clock signal. 12. The image forming apparatus according to claim 7, wherein said storage means, said first synchronous clock generating means, said second synchronous clock generating means, and said reading means are provided on the same semiconductor chip. An image forming apparatus comprising: