JP2001308462A - Method of manufacturing nitride semiconductor element - Google Patents

Method of manufacturing nitride semiconductor element

Info

Publication number
JP2001308462A
JP2001308462A JP2000120757A JP2000120757A JP2001308462A JP 2001308462 A JP2001308462 A JP 2001308462A JP 2000120757 A JP2000120757 A JP 2000120757A JP 2000120757 A JP2000120757 A JP 2000120757A JP 2001308462 A JP2001308462 A JP 2001308462A
Authority
JP
Japan
Prior art keywords
conductive film
gan
ridge
layer
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000120757A
Other languages
Japanese (ja)
Inventor
Isao Kidoguchi
勲 木戸口
Takeshi Sugawara
岳 菅原
Ryoko Miyanaga
良子 宮永
Akihiko Ishibashi
明彦 石橋
Yuzaburo Ban
雄三郎 伴
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2000120757A priority Critical patent/JP2001308462A/en
Publication of JP2001308462A publication Critical patent/JP2001308462A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide a GaN semiconductor laser which is reduced in defect, such as the dislocation density, etc., and, at the same time, in driving current and driving voltage. SOLUTION: After an n-type GaN layer is caused to deposit on an n-type SiC substrate, the GaN semiconductor laser is manufactured by working the GaN layer to a ridge-like shape until the formed ridge reaches the substrate and covering at least the side faces of the ridge with TiN/SiNx. Since the stripe-like current injecting area of the laser is provided above a recess section, the laser is not affected by a defect such as the dislocation, etc., and, in addition, the series resistance of the laser can be reduced and anisotropic distortion can be added to an active layer. Consequently, the threshold current of the laser can be reduced, because the optical gain of the laser can be increased. Therefore, the characteristics of the GaN bluish purple semiconductor laser can be improved.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は光情報処理分野など
への応用が期待されている半導体レーザなどのGaN系
半導体発光素子および製造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a GaN-based semiconductor light emitting device such as a semiconductor laser expected to be applied to the field of optical information processing and the like, and a method of manufacturing the same.

【0002】[0002]

【従来の技術】V族元素に窒素(N)を有する窒化物半
導体は、そのバンドギャップの大きさから、短波長発光
素子の材料として有望視されている。中でも窒化ガリウ
ム系化合物半導体(GaN系半導体:AlxGayInz
N(0≦x, y, z≦1、x+y+z=1))は研究が
盛んに行われ、青色発光ダイオード(LED)、緑色L
EDが実用化されている。また、光ディスク装置の大容
量化のために、400nm帯に発振波長を有する半導体
レーザが熱望されており、GaN系半導体を材料とする
半導体レーザが注目され現在では実用レベルに達しつつ
ある。
2. Description of the Related Art A nitride semiconductor having nitrogen (N) as a group V element is considered to be promising as a material for a short wavelength light emitting device because of its large band gap. Of these gallium nitride-based compound semiconductor (GaN-based semiconductor: Al x Ga y In z
N (0 ≦ x, y, z ≦ 1, x + y + z = 1) has been actively studied, and a blue light emitting diode (LED) and a green L
ED has been put to practical use. In addition, a semiconductor laser having an oscillation wavelength in the 400 nm band has been eagerly desired for increasing the capacity of the optical disk device, and a semiconductor laser using a GaN-based semiconductor as a material has attracted attention and is now reaching a practical level.

【0003】図9はレーザ発振が達成されているGaN
系半導体レーザの構造断面図である。サファイア基板9
01上に有機金属気相成長法(MOVPE法)によりG
aNバッファー層902、n-GaN層903、n−Al
GaNクラッド層904、n−GaN光ガイド層90
5、Ga1-xInxN/Ga1-yInyN (0<y<x<
1)から成る多重量子井戸(MQW)活性層906、p
−GaN光ガイド層907、p−AlGaNクラッド層
908、p−GaNコンタクト層909が成長される。
そしてp−GaNコンタクト層909上に幅3から10
ミクロン程度の幅のリッジストライプが形成され、その
両側はSiO2911によって埋め込まれる。その後リ
ッジストライプおよびSiO2911上に例えばNi/
Auから成るp電極910、また一部をn−GaN層9
03が露出するまでエッチングした表面に例えばTi/
Alから成るn電極912が形成される。本素子におい
てn電極912を接地し、p電極910に電圧を印加す
ると、MQW活性層906にキャリアが注入され、前記
MQW活性層906内で利得を生じ、発振波長400n
m帯のレーザ発振を起こす。MQW活性層906の材料
であるGa1-xInxN/Ga1-yInyN薄膜の組成や膜
厚によって発振波長は変化する。
FIG. 9 shows GaN in which laser oscillation has been achieved.
1 is a structural sectional view of a semiconductor laser. Sapphire substrate 9
01 on a metalorganic vapor phase epitaxy (MOVPE) method.
aN buffer layer 902, n-GaN layer 903, n-Al
GaN clad layer 904, n-GaN optical guide layer 90
5, Ga 1-x In x N / Ga 1-y In y N (0 <y <x <
1) Multiple quantum well (MQW) active layer 906, p
A -GaN light guide layer 907, a p-AlGaN cladding layer 908, and a p-GaN contact layer 909 are grown.
Then, a width of 3 to 10 is formed on the p-GaN contact layer 909.
A ridge stripe having a width of about a micron is formed, and both sides are buried with SiO 2 911. On subsequent ridge stripe and SiO 2 911, for example, Ni /
Au p-electrode 910 and a part of n-GaN layer 9
For example, Ti /
An n electrode 912 made of Al is formed. In this device, when the n-electrode 912 is grounded and a voltage is applied to the p-electrode 910, carriers are injected into the MQW active layer 906, a gain is generated in the MQW active layer 906, and an oscillation wavelength of 400 n
The laser oscillation in the m band occurs. The oscillation wavelength changes depending on the composition and thickness of the Ga 1-x In x N / Ga 1-y In y N thin film which is the material of the MQW active layer 906.

【0004】このレーザはリッジストライプの幅と高さ
を制御することによって、水平方向の横モードにおいて
基本モードでレーザ発振するような工夫が成される。す
なわち、基本横モードと高次モード(1次以上のモー
ド)の光閉じ込め係数に差を設けることで、基本横モー
ドでの発振を可能としている。
By controlling the width and height of the ridge stripe, the laser is designed to oscillate in the fundamental mode in the horizontal transverse mode. That is, by providing a difference in the light confinement coefficient between the fundamental transverse mode and the higher-order mode (first-order or higher mode), oscillation in the fundamental transverse mode is enabled.

【0005】GaN系結晶の基板には、サファイア、S
iC、Siなどが用いられるが、いずれの基板もGaN
と格子整合せず、コヒーレント成長を得ることが難し
い。その結果、転位(刃状転位、らせん転位、混合転
位)が多く、例えばサファイア基板やSiC基板を用い
た場合、約1×109cm-2の転位が存在する。その結
果、半導体レーザのしきい値電流の増大や信頼性の低下
を引き起こす。
[0005] Sapphire, S
iC, Si, etc. are used, and all substrates are made of GaN.
It is difficult to obtain coherent growth without lattice matching. As a result, there are many dislocations (edge dislocations, screw dislocations, and mixed dislocations). For example, when a sapphire substrate or a SiC substrate is used, dislocations of about 1 × 10 9 cm −2 exist. As a result, the threshold current of the semiconductor laser increases and the reliability decreases.

【0006】転位密度低減の方法として選択横方向成長
(ELO)が提案されている。これは格子不整合が大き
い系において、貫通転位を低減させる方法として有効で
ある。
[0006] Selective lateral growth (ELO) has been proposed as a method of reducing dislocation density. This is effective as a method for reducing threading dislocations in a system having a large lattice mismatch.

【0007】図7はELOによって形成したGaN結晶
の転位の分布を模式的に表したものである。まず、サフ
ァイア基板701上にMOVPE法などによりGaN結
晶702を堆積する。SiO2703をCVDなどで堆
積した後、フォトリソグラフィーとエッチングによって
ストライプ状にSiO2703を加工する。GaN70
2の露出した部分を種結晶として選択成長によってGa
N層704を堆積する。成長方法としてMOVPE法や
HVPE法を用いる。種結晶の上部は約1×109cm
-2と転位の多い領域706が存在するが、横方向成長し
た部分は転位密度が1×107cm-2程度まで低減でき
ている。
FIG. 7 schematically shows the distribution of dislocations in a GaN crystal formed by ELO. First, a GaN crystal 702 is deposited on a sapphire substrate 701 by MOVPE or the like. After depositing SiO 2 703 by CVD or the like, the SiO 2 703 is processed into a stripe shape by photolithography and etching. GaN70
2 as a seed crystal by selective growth
An N layer 704 is deposited. MOVPE or HVPE is used as a growth method. The upper part of the seed crystal is about 1 × 10 9 cm
Although there is a region 706 having many dislocations at −2 , the dislocation density can be reduced to about 1 × 10 7 cm −2 in the laterally grown portion.

【0008】この転位の少ない領域705の上部に活性
領域、つまり電流注入領域を形成することで信頼性を向
上させようとしている。
An active region, that is, a current injection region is formed above the region 705 having a small number of dislocations to improve reliability.

【0009】[0009]

【発明が解決しようとする課題】ところが、この方法で
は選択成長用マスクSiO2703上に多結晶が堆積す
ることで、結晶性の悪い領域が部分的に生じ、歩留まり
や生産性を低下させる恐れが生じる。
However, in this method, a polycrystal is deposited on the selective growth mask SiO 2 703, and a region having poor crystallinity is partially formed, which may lower the yield and productivity. Occurs.

【0010】また、pおよびn電極を同一面上に形成す
る必要があるため、レーザ作製の際の工程数が増えると
いう欠点もある。
In addition, since the p and n electrodes need to be formed on the same plane, there is a disadvantage that the number of steps in laser fabrication increases.

【0011】本発明は上記の事情を鑑みてなされたもの
であり、信頼性の高い窒化物半導体素子を歩留まり良く
作製する方法を提供するものである。特に光ディスク用
青紫色半導体レーザへの応用において効果的である。
The present invention has been made in view of the above circumstances, and provides a method of manufacturing a highly reliable nitride semiconductor device with a high yield. It is particularly effective in application to a blue-violet semiconductor laser for optical disks.

【0012】[0012]

【課題を解決するための手段】本発明のGaN系半導体
の製造方法は、導電性の基板上にAluGavInwN(u
+v+w=1)を堆積する工程と、AluGavInwNを
凹状に基板に達するまでエッチングしてリッジを形成す
る工程と、少なくともリッジの側面を高融点の導電性膜
で被覆する工程と、AluGavInwNの導電性膜で被
覆されていない領域のC面を種結晶としてAlxGay
zN(x+y+z=1)結晶を成長させる工程とを有
している。
GaN-based semiconductor manufacturing method of the present invention SUMMARY OF] is on a conductive substrate Al u Ga v In w N ( u
A + v + w = 1) depositing and forming a ridge by etching the Al u Ga v In w N to reach the substrate into a concave shape, a step of covering at least the side surface of the ridge of a refractory conductive film , Al u Ga v in w N Al the C-plane of a region that is not covered with the conductive film as a seed crystal x Ga y I
n z N (x + y + z = 1) and a step of growing crystal.

【0013】本発明のGaN系半導体の製造方法は、導
電性の基板上にAluGavInwN(u+v+w=1)を堆
積する工程と、AluGavInwNを凹状に基板に達す
るまでエッチングしてリッジを形成する工程と、エッチ
ング底面とリッジの側面を高融点の導電性膜で被覆する
工程と、AluGavInwNの導電性膜で被覆されてい
ない領域のC面を種結晶として第一のクラッド層、活性
層、第二のクラッド層を積層する工程と、導電性膜の上
部の活性層にキャリアが注入されるように電流狭窄構造
を形成する工程とを有している。
The method of manufacturing a GaN-based semiconductor of the present invention includes the steps of depositing an Al u Ga v In w N ( u + v + w = 1) on a conductive substrate, a substrate Al u Ga v In w N concavely forming an etched ridge to reach a step of coating the side surfaces of the etched bottom surface and a ridge with a high melting point of the conductive film, Al u Ga v in w N region that is not covered with the conductive film C A step of laminating a first cladding layer, an active layer, and a second cladding layer using the surface as a seed crystal, and a step of forming a current confinement structure so that carriers are injected into the active layer above the conductive film. Have.

【0014】本発明のGaN系半導体の製造方法は、導
電性の基板上にAluGavInwN(u+v+w=1)を堆
積する工程と、レジストをマスクとしてAluGavIn
wNを凹状に基板に達するまでエッチングしてリッジを
形成する工程と、高融点の導電性膜を堆積する工程と、
リフトオフによってレジストおよびレジスト上の導電性
膜を除去する工程と、AluGavInwNの表面に露出
した部分を種結晶としてさらにGaN系結晶を再成長さ
せる工程とを有している。
[0014] GaN-based semiconductor manufacturing method of the present invention, on a conductive substrate Al u Ga v In w N ( u + v + w = 1) depositing a, Al u using the resist as a mask Ga v an In
w forming a ridge by etching N in a concave shape to reach the substrate; and depositing a high melting point conductive film;
It has a step of removing the conductive film on the resist and the resist, and a step of further regrown GaN group crystal part exposed on the surface of the Al u Ga v In w N as a seed crystal by a lift-off.

【0015】さらに本発明のGaN系半導体の製造方法
は、高融点の導電性膜の上部がさらに非晶質絶縁膜で被
覆されている。
Further, in the method of manufacturing a GaN-based semiconductor according to the present invention, the upper portion of the high melting point conductive film is further covered with an amorphous insulating film.

【0016】また、高融点の導電性膜の堆積方法に電子
サイクロトロン共鳴(ECR)プラズマ、特にECRス
パッタを用いている。
In addition, electron cyclotron resonance (ECR) plasma, particularly ECR sputtering, is used as a method for depositing a conductive film having a high melting point.

【0017】高融点の導電性膜が例えばTi、Ta、T
iN、TaN、W、WSixなどのようにTiまたはT
aまたはWを含有している。
The high melting point conductive film is made of, for example, Ti, Ta, T
iN, TaN, W, such as WSi x Ti or T
a or W is contained.

【0018】誘電体膜がSiO2、SiNx、Al23
AlNまたはそれらの化合物(例えば、SiONやAl
NOなど)や多層膜からなる。
The dielectric film is made of SiO 2 , SiN x , Al 2 O 3 ,
AlN or a compound thereof (for example, SiON or Al
NO) and a multilayer film.

【0019】[0019]

【発明の実施の形態】以下、本発明の実施の形態につい
て図面を用いて詳細に説明する。本発明の製造方法は、
窒化物半導体の成長方法はMOVPE法に限定するもの
ではなく、ハイドライド気相成長法(H?VPE法)や
分子線エピタキシー法(MBE法)など、GaN系半導
体層を成長させるためにこれまで提案されている全ての
方法に適用できる。
Embodiments of the present invention will be described below in detail with reference to the drawings. The production method of the present invention
The nitride semiconductor growth method is not limited to the MOVPE method, but has been proposed for growing a GaN-based semiconductor layer such as a hydride vapor phase epitaxy method (H-VPE method) or a molecular beam epitaxy method (MBE method). The method can be applied to all methods.

【0020】また、ここで言うGaN系半導体とはIII
族元素としてGaを含む窒化物半導体のことを言い、G
aの他にB、Al、Inを含有するものも含まれる。
The GaN-based semiconductor referred to here is III
A nitride semiconductor containing Ga as a group III element
In addition to a, those containing B, Al, and In are also included.

【0021】(実施の形態)図1および図2(図1のn
型GaN103付近の拡大図)は本発明の実施例を示す
GaN系半導体レーザの構造断面図である。このレーザ
の作製方法を図3から図5に示す。
(Embodiment) FIGS. 1 and 2 (n in FIG. 1)
(Enlarged view in the vicinity of the type GaN 103) is a structural cross-sectional view of a GaN-based semiconductor laser showing an example of the present invention. FIGS. 3 to 5 show a method of manufacturing this laser.

【0022】図1に示すレーザの作製方法は以下の通り
である。
The method of manufacturing the laser shown in FIG. 1 is as follows.

【0023】まず、導電性のn型SiC基板101上に
1030℃でTMA(トリメチルアルミニウム)とNH
3(アンモニア)とを供給して高抵抗AlNバッファ層
102を堆積する。その後、1000℃に温度を変え、
TMG(トリメチルガリウム)とNH3とSiH4(モノ
シラン)を供給しn型GaN層103を堆積する(図
3)。この時、GaN層の主面(表面)はC面になって
いる。次にフォトリソグラフィー技術によってレジスト
をストライプ状に加工し、続いてレジストをマスクとし
ドライエッチングによってGaN層103とAlNバッ
ファ層102とn型SiC基板101の一部をリセス状
(凹状)に加工する。この時、リセス部の幅は約20ミ
クロン、リッジ部(レジストのある部分)の幅は約3ミ
クロンである。
First, on a conductive n-type SiC substrate 101, TMA (trimethylaluminum) and NH
3 (ammonia) to deposit the high-resistance AlN buffer layer 102. Then change the temperature to 1000 ° C,
TMG (trimethylgallium), NH 3 and SiH 4 (monosilane) are supplied to deposit the n-type GaN layer 103 (FIG. 3). At this time, the main surface (surface) of the GaN layer is a C-plane. Next, the resist is processed into a stripe shape by photolithography, and then the GaN layer 103, the AlN buffer layer 102, and a part of the n-type SiC substrate 101 are processed into a recessed shape (concave shape) by dry etching using the resist as a mask. At this time, the width of the recess is about 20 microns, and the width of the ridge (the part with the resist) is about 3 microns.

【0024】続いてECRスパッタ法を用いてTiN1
04(厚さ20nm)とSiNx105(厚さ20n
m)を堆積し、リフトオフによってリッジストライプ上
のレジストとレジスト上のTiNおよびSiNxを除去
する(図4)。
Subsequently, TiN1 is deposited by using the ECR sputtering method.
04 (thickness: 20 nm) and SiN x 105 (thickness: 20 n)
m) is deposited, and the resist on the ridge stripe and the TiN and SiN x on the resist are removed by lift-off (FIG. 4).

【0025】露出したn型GaN層103のC面を種結
晶としてMOVPE法によってn型GaN層107、n
型Al0.07Ga0.93Nクラッド層108、n型GaN光
ガイド層109、InGaN多重量子井戸(MQW)活
性層110、p―GaN光ガイド層111、p―Al
0.07Ga0.93Nクラッド層112、p―GaN層113
を順次堆積する(図5)。この時、隣同士のリッジは合
体しなくてもよい。
Using the exposed C-plane of the n-type GaN layer 103 as a seed crystal, the n-type GaN layer 107, n
-Type Al 0.07 Ga 0.93 N clad layer 108, n-type GaN light guide layer 109, InGaN multiple quantum well (MQW) active layer 110, p-GaN light guide layer 111, p-Al
0.07 Ga 0.93 N cladding layer 112, p-GaN layer 113
Are sequentially deposited (FIG. 5). At this time, the adjacent ridges do not have to be combined.

【0026】その後、p―GaN層113とp―Al
0.07Ga0.93Nクラッド層112をさらにリッジストラ
イプ状に加工し、リッジの両脇を絶縁膜114で覆い、
電流注入領域を形成する。ストライプ幅は2.5ミクロ
ン程度である。また、リッジ部はエアギャップ106の
上部の転位の少ない領域に形成されている。
Thereafter, the p-GaN layer 113 and the p-Al
The 0.07 Ga 0.93 N clad layer 112 is further processed into a ridge stripe shape, and both sides of the ridge are covered with an insulating film 114.
A current injection region is formed. The stripe width is about 2.5 microns. Further, the ridge portion is formed in a region above the air gap 106 where dislocations are small.

【0027】絶縁膜114の開口部のp―GaN層11
3表面と、絶縁膜114の一部はp電極115が設けら
れている。また、n型SiC基板の裏面にはn電極11
6が形成されている。
The p-GaN layer 11 at the opening of the insulating film 114
The p-electrode 115 is provided on the three surfaces and a part of the insulating film 114. An n-electrode 11 is provided on the back surface of the n-type SiC substrate.
6 are formed.

【0028】このようにして図1に示される半導体レー
ザを作製する。
Thus, the semiconductor laser shown in FIG. 1 is manufactured.

【0029】本素子においてn電極116とp電極11
5の間に電圧を印加すると、MQW活性層110にキャ
リアが注入され、活性層で利得を生じ、402nmの波
長でレーザ発振を起こす。MQW活性層110は厚さ3
nmのGa0.8In0.2N井戸層と厚さ6nmのGaNバ
リア層から構成されている。
In this device, the n-electrode 116 and the p-electrode 11
5, carriers are injected into the MQW active layer 110, a gain is generated in the active layer, and laser oscillation occurs at a wavelength of 402 nm. The MQW active layer 110 has a thickness of 3
It has a Ga 0.8 In 0.2 N well layer with a thickness of 6 nm and a GaN barrier layer with a thickness of 6 nm.

【0030】図2に示すように、n型GaN層103と
n型SiC基板101との間には高抵抗のAlNバッフ
ァー層102がある。n電極116から注入された電子
にとってAlN層102は障壁となり、抵抗の上昇を招
いてしまう。しかし、本発明では、リッジストライプ状
のn型GaN層103、AlN層102、n型SiC基
板101の少なくとも側壁を導電性のTiN104で短
絡してあり、抵抗の上昇を著しく抑制できる。TiNは
融点が高いために、n型GaN層107およびその上部
の多層間膜を積層する際に、分解することはない。本発
明では蒸発をより抑制するために、TiN104の上に
SiNx105を被覆してある。また、TiNはn型S
iCとn型GaN層の双方にとって低抵抗のコンタクト
抵抗が得られるために、デバイスの低抵抗化には有効で
ある。
As shown in FIG. 2, between the n-type GaN layer 103 and the n-type SiC substrate 101, there is a high-resistance AlN buffer layer 102. The AlN layer 102 acts as a barrier for electrons injected from the n-electrode 116, and causes an increase in resistance. However, in the present invention, at least the side walls of the ridge stripe-shaped n-type GaN layer 103, the AlN layer 102, and the n-type SiC substrate 101 are short-circuited by the conductive TiN 104, so that the rise in resistance can be significantly suppressed. Since TiN has a high melting point, it does not decompose when stacking the n-type GaN layer 107 and the multilayer interlayer film thereon. In the present invention, SiN x 105 is coated on TiN 104 to further suppress evaporation. TiN is n-type S
Since a low-resistance contact resistance is obtained for both the iC and the n-type GaN layer, it is effective for reducing the resistance of the device.

【0031】図1の本発明のGaN系半導体レーザは、
リッジストライプに垂直方向に、すなわち面内で異方的
な歪みが加わっており、その結果、光学利得を増大させ
ることが可能となって、著しくしきい値電流を低減させ
ることができる。
The GaN semiconductor laser of the present invention shown in FIG.
Anisotropic distortion is applied to the ridge stripe in the vertical direction, that is, in the plane, so that the optical gain can be increased and the threshold current can be significantly reduced.

【0032】図6に示すようにn型GaN103種結晶
の上部は約1×109cm-2と転位の多い領域603が
存在するが、横方向成長した部分は転位密度が1×10
6cm-2程度まで低減できている。
As shown in FIG. 6, the upper portion of the n-type GaN 103 seed crystal has a region 603 having a large number of dislocations of about 1 × 10 9 cm −2.
It has been reduced to about 6 cm -2 .

【0033】この転位の少ない領域604の上部に活性
領域、つまり電流注入領域を形成することで信頼性を向
上させることが可能となる。
By forming an active region, that is, a current injection region, above the region 604 having a small number of dislocations, reliability can be improved.

【0034】本発明では、n型GaN層103、AlN
層102、n型SiC基板101をリッジ状に加工し、
リッジストライプの側壁とリセス底部にTiN104/
SiNx103を形成した後、MOVPE法によってn
型GaN層107以降の再成長層601を成長させる。
その際、従来と同様に多結晶GaN602が析出する場
合がある(図6)。しかし、段差があるために、多結晶
GaN602は上部の結晶に影響を及ぼすことはない。
その結果、特性のばらつきを大きく低減でき、歩留まり
を向上させることができる。
In the present invention, the n-type GaN layer 103, AlN
The layer 102 and the n-type SiC substrate 101 are processed into a ridge shape,
TiN104 / TiN104 /
After forming SiN x 103, n is formed by MOVPE.
The regrown layer 601 after the type GaN layer 107 is grown.
At that time, polycrystalline GaN 602 may be precipitated as in the conventional case (FIG. 6). However, due to the steps, the polycrystalline GaN 602 does not affect the upper crystal.
As a result, variations in characteristics can be significantly reduced, and the yield can be improved.

【0035】半導体レーザを作製する際、共振器を形成
する必要がある。共振器は主としてへき開によって作製
するが、時として基板に傷、クラックが生じることがあ
る。図7の従来の方法では、基板と最下部のGaN層7
04が接触しているために、傷は半導体素子の層まで達
し、特性を大きく損ねるといった不具合を生じる。本発
明のようにエアギャップ106が形成されると、傷はこ
こで停止するので半導体素子への影響を著しく低減でき
る。
When manufacturing a semiconductor laser, it is necessary to form a resonator. The resonator is mainly made by cleavage, but sometimes the substrate may be scratched or cracked. In the conventional method shown in FIG. 7, the substrate and the lowermost GaN layer 7 are formed.
Due to the contact with the semiconductor chip 04, the damage reaches the layer of the semiconductor element, causing a problem that the characteristics are greatly impaired. When the air gap 106 is formed as in the present invention, the damage stops here, so that the influence on the semiconductor element can be significantly reduced.

【0036】本発明では種結晶としてGaNを用いた場
合について説明したが、GaNを主として含む化合物、
例えばAlGaNやInGaN等でも構わない。
In the present invention, the case where GaN is used as the seed crystal has been described.
For example, AlGaN or InGaN may be used.

【0037】本発明では導電性の膜および誘電体膜の堆
積にECRスパッタを用いている。TiNの場合、原料
として固体Ti、反応性ガスにN2、プラズマガスにA
rを用いる。また、SiNxの場合、原料として固体S
i、反応性ガスにN2、プラズマガスにArを用いてい
る。これらの膜の堆積にECRスパッタを用いること
で、低温で良質の膜を得ることができる。
In the present invention, ECR sputtering is used for depositing a conductive film and a dielectric film. In the case of TiN, solid Ti is used as a raw material, N 2 is used as a reactive gas, and A is used as a plasma gas.
Use r. In the case of SiN x , solid S
i, N 2 is used as a reactive gas, and Ar is used as a plasma gas. By using ECR sputtering for depositing these films, a high-quality film can be obtained at a low temperature.

【0038】また、本発明では融点の高い導電性膜とし
て、TiNを用いて説明したが、Ti、Ta、TaNや
W、WSixなど融点が高く、n型GaNやn型SiC
へのコンタクト抵抗が低い材料であればよい。
Further, as a highly conductive film with a melting point in the present invention has been described with reference to TiN, Ti, Ta, TaN and W, a high melting point such as WSi x, n-type GaN or n-type SiC
Any material may be used as long as it has a low contact resistance to the substrate.

【0039】また、本発明では誘電体膜としてSiNx
を用いているが、その他の誘電体膜または非晶質絶縁
膜、例えばSiO2、SiON、Al23、AlNO、
TiO2、ZrO2、Nb25、アモルファスSi、ある
いはこれらの多層膜でも構わない。
In the present invention, SiN x is used as the dielectric film.
Is used, but other dielectric films or amorphous insulating films such as SiO 2 , SiON, Al 2 O 3 , AlNO,
TiO 2 , ZrO 2 , Nb 2 O 5 , amorphous Si, or a multilayer film of these may be used.

【0040】これらの膜はECRスパッタを用いること
で比較的容易に得ることができる。基板にサファイアを
用いた場合について説明したが、その他の基板、例えば
ZnO、GaN等を用いても本発明の効果は大きい。
These films can be obtained relatively easily by using ECR sputtering. Although the case where sapphire is used for the substrate has been described, the effect of the present invention is great even if another substrate, for example, ZnO, GaN, or the like is used.

【0041】本実施例では、種結晶となるn型GaN層
103はバッファー層を介した2段階の成長によって形
成した場合について説明したが、単結晶となる種結晶で
あれば他の方法を用いてもよい。
In this embodiment, the case where the n-type GaN layer 103 serving as a seed crystal is formed by two-stage growth via a buffer layer has been described. You may.

【0042】本実施例では、種結晶のリッジ形成にリフ
トオフ・プロセスを用いたが、リッジストライプを作製
できる方法であれば、他の方法を用いても構わない。
In this embodiment, a lift-off process is used for forming the ridge of the seed crystal. However, another method may be used as long as a ridge stripe can be formed.

【0043】[0043]

【発明の効果】以上説明したように、本発明のGaN系
半導体の製造方法は、導電性の基板上にAluGavIn
wN(u+v+w=1)を堆積する工程と、AluGavIn
wNを凹状に基板に達するまでエッチングしてリッジを
形成する工程と、少なくともリッジの側面を高融点の導
電性膜で被覆する工程と、AluGavInwNの導電性
膜で被覆されていない領域のC面を種結晶としてAlx
GayInzN(x+y+z=1)結晶を成長させる工程
とを有しており、良質のAlxGayInzN結晶を歩留
まりよく作製することができる。
As described above, according to the present invention, a method of manufacturing GaN-based semiconductor of the present invention, Al on a conductive substrate u Ga v an In
depositing a w N (u + v + w = 1), Al u Ga v In
forming a ridge by etching the w N to reach the substrate into a concave shape, a step of covering at least the side surface of the ridge of a refractory conductive film is coated with a conductive film of Al u Ga v In w N Al x
And a step of growing a Ga y In z N (x + y + z = 1) crystal, whereby a high-quality Al x Ga y In z N crystal can be produced with a high yield.

【0044】また、本発明のGaN系半導体素子の製造
方法は、導電性の基板上にAluGavInwN(u+v+w
=1)を堆積する工程と、AluGavInwNを凹状に
基板に達するまでエッチングしてリッジを形成する工程
と、エッチング底面とリッジの側面を高融点の導電性膜
で被覆する工程と、AluGavInwNの導電性膜で被
覆されていない領域のC面を種結晶として第一のクラッ
ド層、活性層、第二のクラッド層を積層する工程と、導
電性膜の上部の活性層にキャリアが注入されるように電
流狭窄構造を形成する工程とを有しており、転位密度の
低減によって信頼性が高くすることができ、また直列抵
抗および駆動電圧を低減でき、さらに異方的な歪みを活
性層に加えることができるために光学利得を増大させる
ことが可能となって著しくしきい値電流及び駆動電流を
低減させることが可能となり、GaN系青紫色半導体レ
ーザの特性を向上させることができる。
[0044] Further, the method of manufacturing GaN-based semiconductor device of the present invention, on a conductive substrate Al u Ga v In w N ( u + v + w
= 1) depositing a, Al u Ga v In w a step N by etching to reach the substrate concavely to form a ridge, the step of coating the side surfaces of the etched bottom surface and a ridge with a high melting point of the conductive film When, Al u Ga v in w N conductive film in the first cladding layer C surface area which is not covered as a seed crystal, the active layer, and laminating a second cladding layer, the conductive film Forming a current confinement structure so that carriers are injected into the upper active layer, whereby the reliability can be increased by reducing the dislocation density, and the series resistance and drive voltage can be reduced. Further, since anisotropic strain can be applied to the active layer, the optical gain can be increased, and the threshold current and the drive current can be significantly reduced. Characteristics It is possible to above.

【0045】また本発明のGaN系半導体の製造方法
は、導電性の基板上にAluGavIn wN(u+v+w=
1)を堆積する工程と、レジストをマスクとしてAlu
GavIn wNを凹状に基板に達するまでエッチングして
リッジを形成する工程と、高融点の導電性膜を堆積する
工程と、リフトオフによってレジストおよびレジスト上
の導電性膜を除去する工程と、AluGavInwNの表
面に露出した部分を種結晶としてさらにGaN系結晶を
再成長させる工程とを有しており、良質のGaN系結晶
を歩留まりよく作製することができる。
Also, a method for manufacturing a GaN-based semiconductor according to the present invention
Is the Al on the conductive substrateuGavIn wN (u + v + w =
1) a step of depositing, and using a resist as a mask Alu
GavIn wEtch N until it reaches the substrate in a concave shape
Step of forming ridge and depositing high melting point conductive film
Process and lift-off by resist and on resist
Removing the conductive film of AluGavInwTable of N
The part exposed on the surface is used as a seed crystal to further add a GaN-based crystal.
A GaN-based crystal of good quality
Can be manufactured with high yield.

【0046】さらに本発明のGaN系半導体の製造方法
は、高融点の導電性膜の上部がさらに非晶質絶縁膜で被
覆されており、低抵抗のデバイスを再現性良く作製する
ことができる。
Further, in the method of manufacturing a GaN-based semiconductor according to the present invention, the upper portion of the high-melting-point conductive film is further covered with an amorphous insulating film, so that a low-resistance device can be manufactured with good reproducibility.

【0047】また、ECRスパッタによってTiNやS
iNxのみならず、その他の膜、例えばSiO2、SiO
N、Al23、AlNO、TiO2、ZrO2、Nb
25、アモルファスSi、Ti、Ta、TaN、W、W
Sixなどの良質の膜を低温で比較的簡便に得ることが
できる。
Further, TiN or S
Not only iN x but also other films such as SiO 2 , SiO
N, Al 2 O 3 , AlNO, TiO 2 , ZrO 2 , Nb
2 O 5 , amorphous Si, Ti, Ta, TaN, W, W
Good quality films such as Si x can be obtained relatively easily at low temperatures.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施の形態を示すGaN系半導体レー
ザの素子断面図
FIG. 1 is a sectional view of an element of a GaN-based semiconductor laser showing an embodiment of the present invention.

【図2】本発明の実施の形態を示すGaN系半導体レー
ザの素子断面図
FIG. 2 is a sectional view of a GaN-based semiconductor laser according to an embodiment of the present invention;

【図3】本発明の実施の形態を示すGaN系半導体レー
ザの製造方法を工程順に示した構造断面図
FIG. 3 is a structural sectional view showing a method of manufacturing a GaN-based semiconductor laser according to an embodiment of the present invention in the order of steps;

【図4】本発明の実施の形態を示すGaN系半導体レー
ザの製造方法を工程順に示した構造断面図
FIG. 4 is a structural sectional view showing a method of manufacturing a GaN-based semiconductor laser according to an embodiment of the present invention in the order of steps;

【図5】本発明の実施の形態を示すGaN系半導体レー
ザの製造方法を工程順に示した構造断面図
FIG. 5 is a structural cross-sectional view showing a method of manufacturing a GaN-based semiconductor laser according to an embodiment of the present invention in the order of steps;

【図6】本発明の効果を示すための図で、2回目の成長
でGaN単結晶が成長する様子を示した図
FIG. 6 is a diagram for illustrating the effect of the present invention, showing a state in which a GaN single crystal grows in the second growth.

【図7】従来のGaN系量子井戸半導体レーザの素子断
面図
FIG. 7 is a cross-sectional view of a device of a conventional GaN-based quantum well semiconductor laser.

【符号の説明】[Explanation of symbols]

101 n型SiC基板 102 AlNバッファー層 103 n型GaN層 104 TiN膜 105 SiNx膜 106 エアギャップ 107 n型GaN層 108 n-Al0.07Ga0.93Nクラッド層 109 n-GaN光ガイド層 110 MQW活性層 111 p-GaN光ガイド層 112 p-Al0.07Ga0.93Nクラッド層 113 p-GaN層 114 絶縁膜 115 p電極 116 n電極 601 再成長層 602 多結晶 603 転位の多い領域 604 転位の低減された領域 701 サファイア基板 702 GaN層 703 SiO2 704 GaN層 705 n-GaN層 706 n-AlGaNクラッド層 707 n-GaN光ガイド層 708 活性層 709 p-GaN光ガイド層 710 p-AlGaNクラッド層 711 p-GaNコンタクト層 712 p電極 713 SiO2 714 n電極Reference Signs List 101 n-type SiC substrate 102 AlN buffer layer 103 n-type GaN layer 104 TiN film 105 SiN x film 106 air gap 107 n-type GaN layer 108 n-Al 0.07 Ga 0.93 N cladding layer 109 n-GaN optical guiding layer 110 MQW active layer 111 p-GaN optical guide layer 112 p-Al 0.07 Ga 0.93 N cladding layer 113 p-GaN layer 114 insulating film 115 p electrode 116 n electrode 601 regrowth layer 602 polycrystal 603 region with many dislocations 604 region with reduced dislocation 701 Sapphire substrate 702 GaN layer 703 SiO 2 704 GaN layer 705 n-GaN layer 706 n-AlGaN cladding layer 707 n-GaN light guide layer 708 Active layer 709 p-GaN light guide layer 710 p-AlGaN cladding layer 711 p-GaN Contact layer 712 p electrode 713 SiO 2 714 n electrode

───────────────────────────────────────────────────── フロントページの続き (72)発明者 宮永 良子 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 石橋 明彦 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 伴 雄三郎 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 Fターム(参考) 5F041 AA40 CA04 CA05 CA34 CA40 CA74 FF16 5F073 AA13 AA45 AA55 AA74 CA07 CB04 CB07 DA05 DA24 DA35 EA29  ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Ryoko Miyanaga 1006 Kadoma Kadoma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. 72) Inventor Yuzaburo Ban 1006 Kazuma Kadoma, Osaka Prefecture F-term (reference) 5F041 AA40 CA04 CA05 CA34 CA40 CA74 FF16 5F073 AA13 AA45 AA55 AA74 CA07 CB04 CB07 DA05 DA24 DA35 EA29

Claims (8)

【特許請求の範囲】[Claims] 【請求項1】導電性の基板上にAluGavInwN(u+
v+w=1)を堆積する工程と、AluGavInwNを凹
状に基板に達するまでエッチングしてリッジを形成する
工程と、少なくともリッジの側面を高融点の導電性膜で
被覆する工程と、AluGavInwNの該導電性膜で被
覆されていない領域のC面を種結晶としてAlxGay
zN(x+y+z=1)結晶を成長させる工程とを有
する窒化物半導体素子の製造方法。
To 1. A conductive substrate Al u Ga v In w N ( u +
v depositing a + w = 1), forming a ridge by etching the Al u Ga v In w N to reach the substrate into a concave shape, a step of covering at least the side surface of the ridge of a refractory conductive film , Al u Ga v in w Al the C-plane of a region that is not covered with the conductive film of N as a seed crystal x Ga y I
n z N (x + y + z = 1) A process for fabrication of a nitride semiconductor device and a step of growing a crystal.
【請求項2】導電性の基板上にAluGavInwN(u+
v+w=1)を堆積する工程と、AluGavInwNを凹
状に基板に達するまでエッチングしてリッジを形成する
工程と、エッチング底面とリッジの側面を高融点の導電
性膜で被覆する工程と、AluGavInwNの該導電性
膜で被覆されていない領域のC面を種結晶として第一の
クラッド層、活性層、第二のクラッド層を積層する工程
と、該導電性膜の上部の活性層にキャリアが注入される
ように電流狭窄構造を形成する工程とを有することを特
徴とする窒化物系半導体素子の製造方法。
To 2. A conductive substrate Al u Ga v In w N ( u +
v depositing a + w = 1), Al u Ga v In a step of the w N is etched to reach the substrate concavely to form the ridge to cover the side surfaces of the etched bottom surface and a ridge with a high melting point of the conductive film a step, a step of laminating Al u Ga v in w N first cladding layer C surface area that is not covered with the conductive film as a seed crystal, the active layer, a second clad layer, conductive Forming a current confinement structure such that carriers are injected into the active layer above the conductive film.
【請求項3】導電性の基板上にAluGavInwN(u+
v+w=1)を堆積する工程と、レジストをマスクとして
AluGavInwNを凹状に基板に達するまでエッチン
グしてリッジを形成する工程と、高融点の導電性膜を堆
積する工程と、リフトオフによってレジストおよびレジ
スト上の該導電性膜を除去する工程と、AluGavIn
wNの表面に露出した部分を種結晶としてさらにGaN
系結晶を再成長させる工程とを有する窒化物系半導体素
子の製造方法。
To 3. A conductive substrate Al u Ga v In w N ( u +
v depositing a + w = 1), a step of etching the Al u Ga v In w N to reach the substrate concavely to form a ridge a resist as a mask, depositing a high melting point of the conductive film, removing the conductive film on the resist and the resist by a lift-off, Al u Ga v in
w The part exposed on the surface of N is used as a seed crystal and
Regrowing a base crystal.
【請求項4】高融点の導電性膜の上部がさらに非晶質絶
縁膜で被覆されている請求項1から3のいずれかに記載
の窒化物系半導体素子の製造方法。
4. The method for manufacturing a nitride semiconductor device according to claim 1, wherein an upper portion of the high melting point conductive film is further covered with an amorphous insulating film.
【請求項5】高融点の導電性膜の堆積方法に電子サイク
ロトロン共鳴(ECR)プラズマを用いることを特徴と
する請求項1から3のいずれかに記載の窒化物系半導体
素子の製造方法。
5. The method for manufacturing a nitride-based semiconductor device according to claim 1, wherein electron cyclotron resonance (ECR) plasma is used as a method for depositing a conductive film having a high melting point.
【請求項6】導電性膜の堆積方法にECRスパッタを用
いることを特徴とする請求項5に記載の窒化物系半導体
素子の製造方法。
6. The method for manufacturing a nitride-based semiconductor device according to claim 5, wherein ECR sputtering is used as a method for depositing the conductive film.
【請求項7】導電性膜がTiまたはTaまたはWを含有
することを特徴とする請求項1から6のいずれかに記載
の窒化物系半導体素子の製造方法。
7. The method for manufacturing a nitride semiconductor device according to claim 1, wherein the conductive film contains Ti, Ta, or W.
【請求項8】誘電体膜がSiNx、SiO2、SiON、
Al23、AlNOを含有する請求項1から3のいずれ
かに記載の窒化物系半導体素子の製造方法。
8. The dielectric film is made of SiN x , SiO 2 , SiON,
Al 2 O 3, a method of manufacturing a nitride-based semiconductor device according to claim 1, any three of which contain AlNO.
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