JP2001308026A - Method for manufacturing silicon carbide semiconductor element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a silicon carbide semiconductor element, capable of maintaining an ion implanted impurity profile, by preventing external or internal diffusion of the ion implanted impurities or particularly a boron (B) at a high-temperature annealing time. SOLUTION: The method for manufacturing the silicon carbide semiconductor element comprise the steps of generating silicon(Si) holes near an impurity ion implanted region, and reducing Si interstitial atoms. The method further comprises the steps of (1) ion implanting an argon(Ar) deeper than G and high temperature annealing, before or after the ion implantation, (2) carbon(C) ion implanting a surface layer, (3) high-temperature annealing in a state without silicon carbide container, after the Ar ion implanting, and (4) epitaxially growing a surface vicinity part in a state in which an Si/C ratio is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to silicon carbide (hereinafter referred to as S)
iC) as a material.

[0002]

2. Description of the Related Art In recent years, SiC has attracted attention as one of semiconductor materials replacing silicon (hereinafter referred to as Si). S
iC has a band gap of 3.25 eV in 4H-SiC.
And approximately three times as large as that of Si (1.12 eV), so that the operating upper limit temperature can be increased. In addition, since the breakdown electric field strength of 4H-SiC is 3.0 MV / cm, which is about one digit larger than that of Si (0.25 MV / cm), the effect is obtained by the reciprocal of the cube of the breakdown electric field strength. On-resistance (= forward voltage / current in energization) is reduced, and loss in a steady state can be reduced. Furthermore, the thermal conductivity of 4.9 W / cmK for 4H-SiC is 3 times that of Si (1.5 W / cmK).
Since it is more than twice as high, there is an advantage that the heat cooling effect is high and the cooling device can be downsized. 2 × 1 saturation drift speed
As large as 0 ⁷ cm / s, it is excellent in high speed operation.

[0003] For these reasons, SiC is expected to be applied to power semiconductor elements (hereinafter referred to as power devices), high-frequency devices, high-temperature operating devices, and the like.
At present, MOSFETs, pn diodes, Schottky diodes, and the like have been prototyped, and devices that exceed the characteristics of Si semiconductors in terms of withstand voltage and on-resistance continue to appear.

[0004] In order to produce such an element, a technique for controlling the conductivity type and carrier concentration in a selected region or forming a junction is required. The methods include a thermal diffusion method and an ion implantation method. Several μm for Si semiconductor devices
In the case of forming a deep junction as described above, the thermal diffusion method uses a depth of 1
When a relatively shallow junction of μm or less is formed, an ion implantation method is generally used. However, in SiC, the diffusion coefficient of impurities is very small, so it is difficult to apply the thermal diffusion method. In almost all cases, the ion implantation method is used at present.

[0005] As a p-type dopant for ion implantation,
Aluminum (hereinafter referred to as Al) or boron (hereinafter referred to as B
Is often used. Since B has a smaller atomic weight than Al, deeper implantation can be performed. However, in the case of B, it is known that the annealing temperature required for electrically activating must be about 200 ° C. higher than that of Al and about 1700 ° C. or higher [for example,
T.Kimoto, A.Itoh, N.Inoue, O.Takemura, T.Yamamot
o, T. Nakajima and H. Matsunami: Materials Science
Forum vols. 264-268, pp. 675-680 (1998)].

Further, when the distribution of B or Al ions implanted into SiC is measured by the RBS method or the like, it is known that B has less damage to the crystal at the time of implantation than Al. T.Kimoto, A.Itoh, H.Matsunami,
T.Nakata and M.Watanabe: J.Electron.Mater., Vol.2
5, no. 5, pp. 879-884 (1996)]. On the other hand, from the viewpoint of device characteristics, for example, in a pn diode,
The diode implanted with B has a slightly higher on-resistance than the diode implanted with Al, but has a higher dielectric strength,
It is characterized by low leakage current [for example, T.Kimo
to, O.Takemura, H.Matsunami, T.Nakata and M.Inoue
: J. Electron. Mater., Vol.27, no.4, pp.358-364 (199
8)].

As described above, since both Al and B have advantages, both are required as p-type dopants, and it is prudent to use two types depending on the application. As described above, after the ion implantation, in order to electrically activate the implanted B, it is necessary to perform high-temperature annealing at 1700 ° C. or more.

At the time of the high-temperature annealing, an SiC crystal plate is usually placed in a container made of polycrystalline SiC in order to prevent atoms near the surface of the SiC substrate from evaporating and causing surface roughness and composition deviation. Perform high temperature annealing. Also,
During the high temperature annealing, if there is an oxide film on the SiC substrate surface,
Since the surface is etched by reacting with oxygen in the oxide film, it is important to remove the oxide film on the surface in advance to prevent the etching.

[0009]

In the case where B is ion-implanted into a SiC crystal plate, B is desorbed from the substrate surface due to outward diffusion during the high-temperature annealing, or generates a small amount of inward diffusion. . Because of these diffusion phenomena,
There is a problem that it is difficult to obtain a uniform concentration distribution in the depth direction, to form a shallow junction, and to form a high-concentration p-type layer.

Regarding the diffusion of B during high-temperature annealing, a kick-out mechanism has been proposed [M. Laube,
G. Pensl and H. Itoh: Appl. Phys. Lett., Vol. 74, no. 1
6, pp.2292-2294 (1999)]. This mechanism is expressed by the following equilibrium equation. B (S) + Si (I) ⇔B (I) [Equation 1] Here, (I) is (Interstitial = interstitial), and (S) is (Sub)
B (I) is the B at the interstitial position.
, Si (I) is Si at the interstitial position, and B (S) is B substituted for the Si position in the SiC substrate. The meaning of this equation is that the B atom that is electrically active by replacing the Si position in the SiC substrate, that is, B (S) is:
The position is driven out by the interstitial Si (I),
That is, B (I) of an interstitial atom having a large diffusion coefficient is obtained.

This mechanism can occur regardless of the type of the implanted impurity. Particularly, in the case of an atom having a relatively small atomic weight, such as B, during the high-temperature annealing after the ion implantation, the outward / inward diffusion occurs. The problem of doing so is big. If the ion implantation depth is shallow, impurity atoms easily escape from the surface into vacuum due to outward diffusion. In view of such a problem, an object of the present invention is to provide a method for manufacturing a device having excellent characteristics while suppressing diffusion of impurities during annealing and maintaining a concentration profile.

[0012]

In order to suppress the diffusion of impurity atoms such as B from [Equation 1] described above, it is effective to reduce Si (I) at interstitial positions. Conceivable. Therefore, in order to solve the above problems, the present invention
In a method for manufacturing a silicon carbide semiconductor device in which an impurity region is formed by ion implantation of impurities and subsequent annealing in a surface layer of an epitaxial layer of a silicon carbide epitaxial crystal plate, ion implantation of impurities is performed before or after ion implantation of impurities. Means for reducing the concentration of interstitial atoms in the vicinity of the region shall be provided.

As a means for lowering the interstitial atom concentration near the impurity ion implantation region, it is effective to increase the vacancy concentration of silicon atoms near the impurity ion implantation region. A second impurity ion, for example, a rare gas element as an impurity,
For example, if ions are implanted deeper than the ion implantation region of B,
It is known that Si and C vacancies are generated in a region shallower than the range in the direction of ion implantation (hereinafter referred to as Rp), and Si and C are generated at interstitial positions in a region deeper than Rp. [For example, MVRao, JAGardner, PHC
hi, OWHolland, G. Kelner, J. Kretchmer and M. Ghezz
o: J. Appl. Phys., 81, no.10, 6635-6641, (1997
Year)].

Therefore, if the implantation depth of the rare gas element is made sufficiently deeper than the implantation depth of B, the periphery of the implanted B becomes
Since many Si and C vacancies are present and B can be stably present at the Si lattice position without being knocked out by Si atoms at interstitial positions, outward and inward diffusion of B is suppressed. . Before or after the ion implantation of the second impurity, C may be implanted into the surface layer of the epitaxial layer.

By C ion implantation, C vacancies can be reduced and impurities can be stably introduced into electrically active Si lattice positions. As a method for increasing the vacancy concentration of silicon atoms in the vicinity of the impurity ion-implanted region, high-temperature annealing may be performed in the absence of a polycrystalline SiC container after the second impurity ions are implanted into the SiC substrate. .

The Si—C bond is broken by ion implantation,
Thereafter, by annealing at a high temperature, Si having a higher saturated vapor pressure than C evaporates from the ion implantation region, so that Si vacancies are formed in the ion implantation region. After that, if ion implantation of impurities is performed, impurities of interstitial atoms, S
Both i are often captured by these Si vacancies, and the probability of knocking out the impurities replacing the Si positions by Si at interstitial positions is reduced, thereby suppressing the diffusion of the impurities.

As a method for increasing the vacancy concentration of silicon atoms in the vicinity of the impurity ion-implanted region, a method of increasing the concentration of silicon only in the vicinity of the surface of the epitaxial layer during epitaxial growth.
The gas flow rate may be controlled so as to lower the / C ratio. Si
By lowering the / C ratio, Si vacancies are formed, and Si at interstitial positions are trapped therein, so that Si atoms at interstitial positions are reduced as a result and impurities ejected at interstitial positions Is reduced and diffusion is suppressed.

The second impurity ion is preferably a rare gas element. Rare gas elements are relatively heavy and tend to generate atomic vacancies. On the other hand, it is easily desorbed by high-temperature annealing. Furthermore,
Boron ion is an element which has the most remarkable effect by the method of the present invention since it has a small atomic radius and is easily diffused.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below based on examples. [Embodiment 1] FIG. 1 is a sectional view for explaining a first manufacturing method of the present invention. As the wafer, an epitaxial crystal plate in which the epitaxial layer 2 was grown on an n-type 4H—SiC base substrate 1 at a plane 8 ° off the (0001) Si plane was used.
The carrier concentration of the underlying substrate 1 is 1 × 10 ¹⁸ cm ⁻³ , the carrier concentration of the epitaxial layer 2 is 1 × 10 ¹⁶ cm ⁻³ ,
The thickness is 10 μm.

At room temperature, argon (hereinafter referred to as Ar) ions are implanted into the substrate at a dose of 5 × 10 ¹⁴ cm ⁻² and an implantation energy of 1 MeV. At this time, the range (hereinafter referred to as Rp) in the Ar injection direction is about 1 μm, and Rp
Deeper regions include Si and C interstitial atoms Si (I) and C
In the interstitial atomic layer 3 in which many (I) exist, an atomic vacancy layer 4 in which many Si and C vacancies Si (V) and C (V) exist in a region shallower than Rp is formed. The boundaries of these implanted layers can be seen from the peak positions of Ar in the impurity depth direction analysis by secondary ion spectrometry (SIMS).

Next, B ion implantation was performed at room temperature so as to be shallower than the boundary between the interstitial atomic layer 3 and the atomic vacancy layer 4. The implantation energy and dose are 100 keV / 2.
^{8 × 10 13 cm -2, 60keV} /1.4×10 13 cm -2, 30
This is a three-stage injection of keV / 8 × 10 ¹² cm ⁻² . The B layer 5 was formed by this ion implantation. The Rp of B at 100 keV is about 0.3 μm.

Thereafter, in order to activate B, polycrystalline Si
Annealing was performed in a C container at 1700 ° C. for 30 minutes in an Ar atmosphere at normal pressure. For the B ions implanted by the above method, the concentration distributions in the depth direction immediately after the ion implantation and after the activation annealing were measured by SIMS analysis. FIG. 4 shows the results. The horizontal axis is the depth from the surface of the SiC substrate, and the vertical axis is the logarithmic B concentration. For comparison, the same figure also shows the concentration distribution according to the conventional method without performing Ar ion implantation.

Immediately after ion implantation, the concentration is 2 × 10 ¹⁸ cm ⁻³ ,
It was a box profile having a depth of 0.3 μm [FIG. 4 (a)]. When the Ar ion implantation is not performed, the distribution after the activation annealing is such that only a very thin high-concentration layer is found immediately below the surface, and the impurity concentration therebelow is lower than 10 ¹⁷ cm ^−3. [(C) in the same figure]. This distribution is due to the remarkable outward / inward diffusion.

However, when the method of the present invention was used, it was found that the diffusion of B was suppressed even after the activation annealing, and the box-shaped profile was maintained [FIG. As a precaution, whether or not the implanted B atoms were electrically activated was measured by the CV (capacitance-voltage) method. As a result, the acceptor concentration was 1.5 × 10 ¹⁸ cm ⁻³ , and the activation rate was 1.5%. Was found to be quite high at 83%.

Similar results were obtained when Ar ion implantation was performed after B ion implantation. [Example 2] Using the same substrate as in Example 1 and performing Ar ion implantation under the same conditions, prior to B ion implantation, C ion implantation was performed at an acceleration voltage of 130 keV and a dose of 2. ^{8 × 10 13 cm -2, 80keV} /1.4×10 13 cm -2,
The test was performed under the conditions of 40 keV / 8 × 10 ¹² cm ⁻² . Subsequent B implantation conditions and activation annealing conditions are the same as in the first embodiment. [FIG. 2] It was confirmed that the box profile of B implanted in the same manner as in Example 1 was maintained almost as it was even after the high-temperature annealing, and was activated by nearly 100% to form a high concentration region.

[Embodiment 3] On the same substrate as in Embodiment 1, A
r ion implantation is performed at an accelerating voltage of 200 keV and a dose of 5 × 10
^Performed at ¹⁴ cm ^-2 . The projection range at this time is about 0.2 μm
become. Subsequently, the condition of B ion implantation is 30 keV / 1.
A shallow ion implantation of × 10 ¹⁴ cm ⁻² was performed. The projection range at this time is about 0.07 μm.

Then, annealing was performed in a vacuum at 1700 ° C. for 30 minutes in an annealing furnace without using a polycrystalline SiC container. At this time, Si having a high vapor pressure is selectively desorbed from the Ar ion implanted layer, and a large number of Si (V), which are vacancies of Si, are generated in the ion implanted layer. Although the effect was less than that of Example 1, the box profile of B was more likely to be maintained than before. There is an advantage that the method is simple and can be easily implemented.

Example 4 An epitaxial layer was grown on the same substrate as in Example 1 by further reducing the Si / C ratio by about 1 μm. Usually, Si / C ratio = 0.25-0.
5, while in this example the Si / C ratio =
0.1. The specific gas flow rate is propane (C ₃ H
₈ ): Monosilane (SiH ₄ ) = 1: 0.3 sccm, growth temperature 1500 ° C. By this method, an epitaxial growth layer 7 containing a lot of Si vacancies is formed [FIG. 3]. Subsequent B ion implantation conditions and activation annealing conditions are the same as in the first embodiment.

Although the effect was less than that of Example 1, the box-shaped profile of B was maintained and the activation rate was higher than before. This method also has an advantage that it can be easily implemented. The mechanism of this example is understood as follows. Controlling the gas flow rate,
By lowering the Si / C ratio only near the surface of the epitaxial growth layer, the concentration of vacancies Si (V) of silicon atoms in the vicinity of the impurity ion-implanted region can be increased.
Numerous Si (V) are formed, and Si (V)
Since (I) is captured, Si (I) is reduced as a result.
Then, the amount of B, ie, B (I), knocked out from the replacement position to the interstitial position is reduced, and diffusion is suppressed.

[0030]

As described above, according to the present invention, the concentration of silicon vacancies in the vicinity of the impurity region is increased by, for example, implanting rare gas ions before and after the impurity ion implantation, and the It has been shown that, as a result, the number of impurity interstitial atoms is reduced, and the diffusion of impurities outward and inward can be greatly reduced.

In particular, in the case of boron doping, which is likely to be an interstitial atom due to a small atomic radius and is hard to be activated, the box-shaped profile after ion implantation is substantially maintained even after high-temperature annealing, and the activation rate , And it was confirmed that a high concentration could be realized. Other methods for increasing the silicon vacancy concentration include a method of annealing at a high temperature without using a SiC container, and a method of growing the epitaxial layer under a gas condition with a low Si / C ratio.

Thus, the present invention makes a great contribution to the development and spread of silicon carbide semiconductor devices.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a SiC semiconductor device according to a method of a first embodiment of the present invention.

FIG. 2 is a sectional view of a SiC semiconductor device according to a method of a second embodiment of the present invention.

FIG. 3 is a sectional view of a SiC semiconductor device according to a method of a fourth embodiment of the present invention.

FIG. 4 shows a B concentration profile obtained by a SIMS method, (a) before the annealing, (b) by the method of the first embodiment of the present invention, and (c) by a conventional manufacturing method.

[Explanation of symbols]

1 ... base substrate (10 ¹⁸ cm ^-3) 2 ... epitaxial layer ^{(10 16 cm -3 -10 μm)} 3 ... interstitial layer 4 ... vacancies layer 5 ... B ion implanted layer 6 ... C ion implantation layer 7 … Epitaxial layer containing many Si vacancies

Claims (8)

[Claims] In a method for manufacturing a silicon carbide semiconductor device in which an impurity region is formed in a surface layer of an epitaxial layer of a silicon carbide epitaxial crystal plate by ion implantation of impurities and subsequent annealing, before or after ion implantation of impurities. And means for reducing the concentration of interstitial atoms in the vicinity of the ion-implanted region of the impurity. 2. The method according to claim 1, wherein the means for lowering the interstitial atomic concentration in the vicinity of the impurity ion-implanted region is a method of increasing the vacancy concentration of silicon atoms in the vicinity of the impurity ion-implanted region. A method for manufacturing a silicon carbide semiconductor device. 3. The method for manufacturing a silicon carbide semiconductor device according to claim 2, wherein a different second impurity ion is implanted into a region deeper than the impurity ion implantation region of the epitaxial layer. 4. The method for manufacturing a silicon carbide semiconductor device according to claim 3, wherein carbon atoms are ion-implanted into the surface layer of the epitaxial layer before and after the ion implantation of the second impurity ions. 5. After the second impurity ions are implanted,
5. The method for manufacturing a silicon carbide semiconductor device according to claim 3, wherein high-temperature annealing is performed in a state where the polycrystalline silicon carbide container does not exist. 6. The method for manufacturing a silicon carbide semiconductor device according to claim 3, wherein a rare gas element is used as the second impurity ion. 7. The method of manufacturing a silicon carbide semiconductor device according to claim 2, wherein during epitaxial growth, the gas flow rate is controlled so as to lower the silicon / carbon atomic ratio only in the surface layer of the epitaxial layer. 8. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the impurity ions are boron ions.