JP2001306415A - Input/output device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an input/output(I/O) device capable of easily executing a test and shortening the test time by eliminating the necessity of a DC test. SOLUTION: The I/O device is provided with a pull-up control register 1, a port latch 2, an I/O control register 3, a CMOS/NOD switching register 4, a selector 5, an internal bus 6, an input buffer 7, an output buffer 8, a pull-up circuit 9, an external terminal 10, an NAND gate 11, an AND gate 12, an OR gate 13, and a test circuit 16.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output circuit, and more particularly, to an input / output circuit whose test is facilitated.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram showing a conventional input / output circuit. A conventional input / output circuit includes a port latch 2 and
I / O control register 3, internal bus 6, input buffer 7, output buffer 8, external terminal 10, selector 1
8 and a selector 50. The port latch 2 receives the port latch write signal W (P
L) holds and outputs the written port data. Similarly, the I / O control register 3 holds output control data which is written by the I / O control register write signal W (PM) via the internal bus 6 and controls the output enable / disable of the output buffer 8. Output. The output buffer 8 is a three-state output buffer, and outputs the port data held by the port latch 2 to the external terminal 10 when the output control data is at the logical (L) level, and outputs the data at the logical (H) level. At this time, the output is turned off, and a high impedance state is set. The input buffer 7 outputs data input from the external terminal 10 to the selector 18. The selector 18 outputs the port data held by the port latch 2 to the selector 50 when the output control data is at the logic (L) level, and outputs the data output from the input buffer 7 when the output control data is at the logic (H) level. Output to selector 50. The selector 50 outputs the data output from the selector 18 to the internal bus 6 according to the port latch selection signal S (PL), and outputs the I / O control register selection signal S (PM).
Outputs the output control data output from the I / O control register 3 to the internal bus 6. In the test of this input / output circuit, the port latch 2 and the I / O 2 are input from an external tester through an input terminal (not shown) and the internal bus 6.
The test pattern is written to the control register 3 and the external terminal 1
The function operation of the output buffer 8 has been confirmed by comparing the data output from 0 with the expected value.

[0003]

However, in the conventional input / output circuit, when the output buffer 8 is in a test pattern in which the output buffer 8 becomes active, a pattern of a logic level is output from the external terminal 10. The test on the output control data can be performed by directly collating with the expected value while running the test pattern. However, when a test pattern such that the output of the output buffer 8 is in a high impedance state is input, the direct pattern collation is performed. Cannot perform a test on the output control data.
The test pattern running is temporarily stopped, a logic (H) level is first written into the I / O control register 3, the output of the output buffer 8 is set to a high impedance state, and
A logical (H) level or a logical (L) level is statically applied to the output buffer 8, and the leak current of the external terminal 10 is measured to confirm the functional operation of the output control data of the output buffer 8. A typical DC test requires a longer measurement time for each test pattern or for each external terminal than a test using only a test pattern. In particular, the configuration of the input / output circuit is not simple. When the operation mode or the pull-up function is provided, the number of control registers increases and the output control data logic becomes more complicated. There was a problem that a long test time was required.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to provide an input / output circuit which facilitates a test by eliminating a direct current test, thereby shortening a test time.

[0005]

An input / output circuit according to the present invention comprises:
A port latch to which data is written from an internal bus, a three-state output buffer for outputting an output of the port latch to an output terminal, an input buffer for receiving data from the output terminal, and a test circuit; Is configured to switch between the output of the port latch or the output of the input buffer and the detection result data indicating that the output of the three-state output buffer is in a high impedance state and output the data to the internal bus.

[0006] The present invention is characterized in that the fact that the output of the three-state output buffer is in a high impedance state is detected at least based on the state of output control data of the three-state output buffer.

Further, the test circuit includes a detection circuit for detecting a state of the output control data.

Further, the test circuit comprises: the detection circuit; a first selector for switching and outputting between the output of the port latch and the output of the input buffer; an output of the detection circuit and an output of the first selector. And a second selector for switching and outputting the signals.

Further, the switching of the second selector is controlled by a test enable signal.

The output of the second selector is the third output.
And output to the internal bus according to a port latch selection signal input to the third selector.

[0011]

Next, the configuration of an input / output circuit according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a configuration diagram of an input / output circuit according to a first embodiment of the present invention. As shown in FIG. 1, an input / output circuit according to a first embodiment of the present invention includes a pull-up control register 1 and a port latch 2.
, An I / O control register 3 and a CMOS / Nch open drain (hereinafter referred to as NOD) switching register 4
, A selector 5, an internal bus 6, an input buffer 7,
Output buffer 8, pull-up circuit 9, external terminal 10
, NAND gate 11, AND gate 12, OR
A gate 13 and a test circuit 16 are provided.

The pull-up control register 1 has an internal bus 6
Holds and outputs data for controlling the pull-up on / off of the pull-up circuit 9 written by the write signal W (PU) via. When the pull-up is set on, a logic (H) level is output, and when the pull-up is set off, a logic (L) level is output.

The pull-up circuit 9 includes a source / drain path of a transistor 9A and a resistor R having one end connected to a power supply VDD connected in series. The input control data is connected to the gate end of the transistor 9A as a control input end. 14 is input and a logic (L) level is input, the output terminal 10 is pulled up and if a logic (H) level is input, the output terminal 10 is pulled up and off.

The port latch 2 holds and outputs port data written by the write signal W (PL) via the internal bus 6.

The I / O control register 3 controls the permission and prohibition of the output of the output buffer 8 written by the write signal W (PM) via the internal bus 6 and the data for controlling the input / output direction of the external terminal 10. And output. When the input mode is set, a logic (H) level is output, and when the output mode is set, a logic (L) level is output.

The output buffer 8 is a three-state output buffer. When the output control data 15 is at a logic (L) level, it outputs the port data output from the port latch 2 to the external terminal 10, and the output control data 15 is at a logic (H). ) When the output is at the level, the output is turned off and a high impedance state is set.

The CMOS / NOD switching register 4 holds and outputs the data written by the write signal W (POM) via the internal bus 6 to switch the output buffer 8 to the CMOS mode or the NOD mode. A logic (H) level is output when the NOD mode is set as an open drain output, and a logic (L) level is output when the CMOS mode is set.

The NAND gate 11 receives an input signal only when both the output of the pull-up control register 1 and the output of the I / O control register 3 are at the logic (H) level, that is, only when the pull-up setting is ON in the input mode. The control data 14 is set to the logic (L) level, and the pull-up circuit 9 is turned on.

The AND gate 12 is set to the NOD mode only when the output of the port latch 2 and the output of the CMOS / NOD switching register 4 are both at the logic (H) level, that is, when the port data is at the logic (H) level. Only when, O
The output control data 15 of the output buffer 8 output from the R gate 13 is forcibly set to a logic (H) level, the output of the output buffer 8 is turned off, and a high impedance state is set.
The output buffer 8 is switched from the CMOS mode to the NOD mode in a pseudo manner.

The OR gate 13 controls the I / O mode except when the port data is at the logic (H) level and the NOD mode is set.
The output of the / O control register 3 is output as output control data 15.

The selector 5 includes a pull-up control register 1, a test circuit 16, an I / O control register 3, and a CMO
When each output of the S / NOD switching register 4 is input and the pull-up control register selection signal S (PU) becomes a logic (H) level, the output of the pull-up control register 1 is output to the internal bus 6 and the port latch is selected. When the signal S (PL) goes to the logic (H) level, the output of the test circuit 16 is output to the internal bus 6, and the I / O control register selection signal S (PM)
Is at a logic (H) level, the output of I / O control register 3 is output to internal bus 6. When CMOS / NOD switching register selection signal S (POM) is at a logic (H) level, CMOS / NOD switching register 4 is output to the internal bus 6.

The selection signal S (PU) / write signal W (PU) and the selection signal S (PL) / write signal W (P
L), selection signal S (PM) / write signal W (PM),
The selection signal S (POM) / write signal W (POM)
Each is generated at the same decoded address in accordance with the read / write timing.

The test circuit 16 includes a detection circuit 17, a selector 18, and a selector 19.

The detection circuit 17 is in a state in which the output terminal 10, which had to be subjected to the DC test in the conventional example, becomes high impedance, that is, both the input control data 14 and the output control data 15 are at the logic (H) level. In order to detect the state, the input control data 14 is input to the input terminal 17A, the output control data 15 is input to the input terminal 17B, and the detection result data is output to the selector 19 from the output terminal 17C.

As shown in FIG. 2 as a specific example, the detection circuit 17 is constituted by an EXOR (exclusive OR) gate 17D. When both the input terminals 17A and 17B are at the logic (H) level, the output circuit 17 outputs the signal. A logic (L) level is output from the terminal 17C as detection result data, but the present invention is not limited to this configuration. For example, a detection expectation value is set using a multi-bit comparator, and an arbitrary state with an arbitrary number of bits can be detected. You may do so.

The input buffer 7 outputs data input from the external terminal 10 to the selector 18. Selector 18
Outputs the port data output by the port latch 2 to the selector 19 when the output of the I / O control register 3 is at a logical (L) level, and inputs the data when the output of the I / O control register 3 is at a logical (H) level. The data output from the buffer 7 is switched to the selector 19 and output.

The selector 19 has a test enable signal T
When ST is input and the test enable signal TST goes to a logic (H) level, the detection result data from the output terminal 17C of the detection circuit 17 is output to the selector 5, and when the test enable signal TST goes to a logic (L) level, The data output from the selector 18 is switched to the selector 5 and output.
By the test enable signal TST, the states of the input control data 14 and the output control data 15 are read out to the internal bus 6 by sharing the read path of the port data of the input buffer 7 and the output buffer 8.

Here, the test enable signal TST is
For example, it is generated by providing a test register and writing data.

Next, the operation will be described. First, the test enable signal TST is set to a logic (H) level, and the test circuit 1
6 is set to output the detection result data from the detection circuit 17 to the selector 5.

Next, for example, when the input / output circuit is in the pull-up ON and NOD output modes, the output terminal 10
Becomes a high impedance state, that is, a logic state in which both the input control data 14 and the output control data 15 are at a logic (H) level.
Is the logic (H) level, the output of the port latch 2 is the logic (H) level, the output of the I / O control register 3 is the logic (L) level, and the output of the CMOS / NOD switching register 4 is the logic (H) level. A test pattern is written from an external tester via the internal bus 6 and set.

As a result, when the control operation of the input / output circuit, that is, the input control data 14 and the output control data 15 are normal, the pull-up circuit 9 is turned off, and the output buffer 8 is turned into a high impedance state. The detection circuit 17 outputs detection result data of a logic (L) level to the selector 5 via the selector 19. If there is a failure in the input control data 14 and the output control data 15, the detection circuit 17 outputs the logic (H). The level detection result data is output to the selector 5 via the selector 19, and when the port latch selection signal S (PL) becomes a logic (H) level, the detection result data is output to the internal bus 6.

As a method of verifying the detection result data output to the internal bus 6, for example, the data is output via an external terminal of an input / output circuit which is not a test target, and is compared with an expected value by an external tester.

The failure of the input control data 14 and the output control data 15 is caused by the register generating both signals,
Detection and determination can be made by repeating the above test for all combinations of the set values of the latches.

As described above, in the input / output circuit of the present embodiment, since the test is only a function test using a test pattern, the test condition can be easily set even when the test condition is diversified. As in the example, a DC test for measuring a leak current having a long measurement time can be unnecessary, so that the test time can be shortened.

FIG. 3 is a block diagram of the input / output circuit according to the second embodiment of the present invention, and FIG. 4 is a time chart of the input / output circuit according to the second embodiment of the present invention. The configuration of the input / output circuit according to the second embodiment of the present invention shown in FIG.
Is different from the configuration of the input / output circuit according to the first embodiment of the present invention in that the test circuit 16 is changed to a test circuit 21. In the test circuit 21, the test enable signal TST and the status The signal CLK and A
The selector 19 is input to the ND gate 20 and controlled by the AND output of the AND gate 20.
The test enable signal TST is changed so as to be inverted by LK. In FIG. 3, the same components as those of the input / output circuit according to the first embodiment of the present invention shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

By the way, in the input / output circuit of the first embodiment of the present invention shown in FIG. 1, at the time of testing, data is written into a test register for generating a test enable signal TST, and the port latch 2 or the input buffer is written. 7 to read the output data of the port latch 2 or the output data of the input buffer 7 in response to one write command of the test register. And reading of the output of the detection circuit 17 cannot both be performed.

However, in the input / output circuit of this embodiment, as shown in FIG. 4, data is written once to the test register, and the test enable signal TST and the port latch selection signal S (PL) are set to logic (H). ) Even if the state remains at the level, the AND gate 2
Since the test enable signal TST output from 0 is inverted, before the time t1 when the status signal CLK changes from the logic (L) level to the logic (H) level, the output of the port latch 2 is output from the selector 5 and the status From time t1 to time t2 when the signal CLK is at the logic (H) level, the detection result data of the detection circuit 17 is output from the selector 5, and the status signal CLK changes from the logic (H) level to the logic (L) level. After the time t2, the output of the port latch 2 is output from the selector 5, so that the port latch 2 is read twice in synchronization with the logic level or the rise and fall of the status signal CLK, so that the port latch 2 The output and the detection result data of the detection circuit 17 can be read and tested.
As compared with the input / output circuit according to the first embodiment of the present invention, there is an effect that the test time can be further reduced.

[0038]

As described above, the first embodiment according to the present invention is described.
The effect of (1) is that since the test is only a function test, it is easy to set the test conditions even when the test conditions are diversified. The second effect is that the leak current measurement has a long measurement time as in the conventional example. Since the DC test can be omitted, the test time can be shortened.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an input / output circuit according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a detection circuit of FIG. 1;

FIG. 3 is a configuration diagram of an input / output circuit according to a second embodiment of the present invention.

FIG. 4 is a time chart of an input / output circuit according to a second embodiment of the present invention.

FIG. 5 is a configuration diagram of a conventional input / output circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Pull-up control register 2 Port latch 3 I / O control register 4 CMOS / NOD switching register 5, 18, 19, 50 Selector 6 Internal bus 7 Input buffer 8 Output buffer 9 Pull-up circuit 9A transistor 10 External terminal 11 NAND gate 12 , 20 AND gate 13 OR gate 16, 21 test circuit 17 detection circuit 17D EXOR gate R resistance

Claims (6)

[Claims] 1. A port latch to which data is written from an internal bus, a three-state output buffer that outputs an output of the port latch to an output terminal, an input buffer that receives data from the output terminal, and a test circuit. The test circuit switches between the output of the port latch or the output of the input buffer and the detection result data indicating that the output of the three-state output buffer is in a high impedance state, and outputs the data to the internal bus. An input / output circuit characterized by the following. 2. The input / output circuit according to claim 1, wherein the output of the three-state output buffer is in a high impedance state based on at least a state of output control data of the three-state output buffer. 3. The input / output circuit according to claim 2, wherein said test circuit includes a detection circuit for detecting a state of said output control data. 4. The test circuit includes: a detection circuit; a first selector for switching between an output of the port latch and an output of the input buffer; and an output of the detection circuit and an output of the first selector. 4. The input / output circuit according to claim 3, further comprising: a second selector for switching and outputting a signal. 5. The switching of the second selector is controlled by a test enable signal.
Input / output circuit as described. 6. The output of the second selector is input to a third selector, and is output to the internal bus according to a port latch selection signal input to the third selector. 5. The input / output circuit according to 5.