JP2001274313A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a problem such that there is provided a semiconductor device to which a semiconductor element is mounted with a printed substrate, a ceramic substrate, a flexible sheet, etc., as a support substrate, but these support substrates are not intrinsically necessary and are surplus materials, and moreover a thickness of the support substrate increases a size of the semiconductor device. SOLUTION: A first conductive path 51A is formed lower than a semiconductor element 52A, and a conductive path 51 and a semiconductor element 52 are supported by an insulating resin 50 to realize a semiconductor device. Accordingly, a top part of a metal fine wire 55A can be lowered and a thickness of a semiconductor device 53 can be thinned.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a thin semiconductor device and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, since a semiconductor device set in an electronic device is used in a portable telephone, a portable computer, and the like, a reduction in size, thickness, and weight is required.

[0003] For example, as a general semiconductor device, there is a package type semiconductor device sealed with a conventional transfer mold. This semiconductor device 1 is mounted on a printed circuit board PS as shown in FIG.

In the package type semiconductor device 1, the periphery of a semiconductor chip 2 is covered with a resin layer 3.
The lead terminal 4 for external connection is led out from the side part of FIG.

However, this package type semiconductor device 1 has
The lead terminals 4 were outside the resin layer 3, and the overall size was large, and the size, thickness and weight were not satisfied.

Therefore, various companies have competed to develop various structures in order to realize miniaturization, thinning and weight reduction, and recently called a CSP (chip size package), a wafer scale CSP equivalent to the chip size. Alternatively, a CSP having a size slightly larger than the chip size has been developed.

FIG. 25 shows a case where a glass epoxy substrate 5 is used as a supporting substrate, and the CS is slightly larger than the chip size.
It shows P6. Here, the glass epoxy substrate 5
It is assumed that the transistor chip T is mounted on the semiconductor device.

A first electrode 7, a second electrode 8, and a die pad 9 are formed on the surface of the glass epoxy substrate 5, and a first back electrode 10 and a second back electrode 11 are formed on the back surface.
Are formed. And, through the through hole TH,
The first electrode 7 and the first back electrode 10 are electrically connected, and the second electrode 8 and the second back electrode 11 are electrically connected. The bare transistor chip T is fixed to the die pad 9, and the emitter electrode of the transistor and the first electrode 7 are fixed.
Are connected via the thin metal wire 12, and the base electrode of the transistor and the second electrode 8 are connected via the thin metal wire 12. Further, a resin layer 13 is provided on the glass epoxy substrate 5 so as to cover the transistor chip T.

Although the CSP 6 employs the glass epoxy substrate 5, unlike the wafer scale CSP, the structure extending from the chip T to the back surface electrodes 10 and 11 for external connection is simple, and the CSP 6 can be manufactured at low cost. Have.

The CSP 6 is mounted on a printed circuit board PS as shown in FIG. In the printed circuit board PS,
The CSP is provided with electrodes and wiring constituting an electric circuit.
6. The package type semiconductor device 1, the chip resistor CR or the chip capacitor CC and the like are electrically connected and fixed.

The circuit constituted by the printed circuit board is mounted in various sets.

Next, a method of manufacturing the CSP will be described with reference to FIGS. 26 and 27. In FIG. 27,
Reference is made to the flow diagram entitled Central Glass Epoxy / Flexible Substrate.

First, a glass epoxy substrate 5 is prepared as a substrate (supporting substrate), and C
The u foils 20 and 21 are pressed. (See FIG. 26A above.) Subsequently, the first electrode 7, the second electrode 8, the die pad 9,
The Cu foils 20 and 21 corresponding to the first back surface electrode 10 and the second back surface electrode 11 are coated with an etching resistant resist 22, and the Cu foils 20 and 21 are patterned. The patterning may be performed separately on the front and the back (see FIG. 26B).
Subsequently, a hole for the through hole TH is formed in the glass epoxy substrate using a drill or a laser, and the hole is plated to form the through hole TH. The first electrode 7 and the first back electrode 1 are formed by the through hole TH.
0, the second electrode 8 and the second back electrode 10 are electrically connected. (Refer to FIG. 26C.) Further, although not shown in the drawing, the first electrode 7 and the second electrode 8 serving as the bonding posts are plated with Ni, and the die pad 9 serving as the die bonding post is formed with Au.
Plating is performed, and the transistor chip T is die-bonded.

Finally, the emitter electrode of the transistor chip T and the first electrode 7, and the base electrode and the second electrode 8 of the transistor chip T are connected via a thin metal wire 12 and covered with a resin layer 13. (See FIG. 26D above.) Then, if necessary, dicing is performed to separate individual electric elements. In FIG. 26, the glass epoxy substrate 5
Although only one transistor chip T is provided, a large number of transistor chips T are provided in a matrix. Therefore, they are finally separated individually by a dicing device.

By the above manufacturing method, a CSP type electric element using the support substrate 5 is completed. This manufacturing method
The same applies to the case where a flexible sheet is used as the support substrate.

On the other hand, a manufacturing method using a ceramic substrate is shown in a flow chart on the left side of FIG. After a ceramic substrate (green sheet) as a supporting substrate is prepared, through holes are formed, and thereafter, front and rear electrodes are printed and sintered using a conductive paste. After that, until the resin layer of the previous manufacturing method is covered, the manufacturing method is the same as that shown in FIG. 26. However, unlike a flexible sheet or a glass epoxy substrate, a ceramic substrate is very fragile and is easily chipped. There is a problem that can not be molded. For this reason, after sealing resin is potted and cured, it is polished to flatten the sealing resin, and finally separated individually using a dicing device.

[0017]

In FIG. 25, a transistor chip T, connecting means 7 to 12 and a resin layer 13 are shown.
Is a necessary component for electrical connection to the outside and protection of the transistor, but it is difficult to provide an electric circuit element that realizes reduction in size, thickness, and weight with only these components. Was.

Further, the glass epoxy substrate 5 serving as the support substrate is essentially unnecessary as described above. However, in the manufacturing method, the glass epoxy substrate 5 is used as a supporting substrate for bonding the electrodes, and the glass epoxy substrate 5 cannot be eliminated.

For this reason, the use of the glass epoxy substrate 5 increases the cost, and furthermore, the thickness of the glass epoxy substrate 5 increases the thickness of the semiconductor device, and there is a limit in reducing the size, thickness and weight of the semiconductor device. Was.

Further, there is a problem that the top of the thin metal wire 12 as the connection means is higher than the transistor chip T, and the semiconductor device 6 is correspondingly thicker.

Further, in the case of a glass epoxy substrate or a ceramic substrate, a step of forming a through hole for connecting electrodes on both surfaces is indispensable, and there has been a problem that the manufacturing process becomes long.

FIG. 28 shows a pattern diagram formed on a glass epoxy substrate, a ceramic substrate, a metal substrate or the like. In this pattern, an IC circuit is generally formed, and the transistor chip 21, the IC chip 22,
A chip capacitor 23 and / or a chip resistor 24 are mounted. A bonding pad 26 integrated with the wiring 25 is formed around the transistor chip 21 and the IC chip 22, and the chips 21, 22 and the bonding pad 26 are electrically connected via a thin metal wire 28. The wiring 29 is formed integrally with the external lead pad 30. These wirings 25, 29
Is formed while being bent in the substrate, and is formed to be the thinnest in an IC chip if necessary. Therefore, these thin wires have a very small area of adhesion to the substrate, and have a problem that the wires are peeled off or warped. The bonding pad 26 includes a power bonding pad and a small-signal bonding pad. Particularly, the small-signal bonding pad has a small bonding area and causes film peeling.

Further, the external lead is fixed to the external lead pad 30, but there is a problem that the external lead pad 30 is peeled off by an external force applied to the external lead.

[0024]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned many problems, and has a plurality of conductive paths electrically separated by separation grooves, and the conductive paths and electrodes of a semiconductor element are connected. A thin metal wire to be covered, and an insulating resin that covers the semiconductor element and is filled in the separation groove between the conductive paths to expose and support the back surface of the conductive path and the back surface of the semiconductor element integrally. Is the solution.

A plurality of conductive paths electrically separated by the separation grooves; a thin metal wire connecting the conductive paths to the electrodes of the semiconductor element; and the separation grooves covering the semiconductor element and between the conductive paths. And an insulating resin for exposing and integrally supporting the back surface of the conductive path and the conductive film formed on the back surface of the semiconductor element.

Further, a plurality of conductive paths electrically separated by the separation groove, a semiconductor element fixed on the first conductive path, and a metal connecting the electrode of the semiconductor element and the second conductive path. A thin wire, and an insulating resin that covers the semiconductor element and is filled in the separation groove between the conductive paths and exposes the back surface of the conductive path to integrally support the semiconductor element. The problem is solved by forming the first conductive path at a low height.

With this structure, the number of components can be minimized, and the top of the thin metal wire can be set low, so that the conventional problems can be solved.

Also, a conductive foil is prepared, and a groove shallower than the thickness of the conductive foil is formed in the conductive foil corresponding to a region between the conductive paths to be formed and a region where the semiconductor element is to be disposed, and the semiconductor element is disposed. Fixing the semiconductor element in the groove to be formed,
The electrode of the semiconductor element and the desired conductive path are electrically connected by a thin metal wire, and the semiconductor element and the thin metal wire are covered, and molded with an insulating resin so as to fill the groove. The problem is solved by separating a predetermined conductive path.

Also, a conductive foil is prepared, and a groove shallower than the thickness of the conductive foil is formed in the conductive foil corresponding to a region between the conductive paths to be formed and the region where the semiconductor element is to be formed by etching. Forming an eave on the conductive path to be formed with a material different from that of the conductive foil, fixing the semiconductor element in a groove in which the semiconductor element is arranged, and connecting the electrode of the semiconductor element and the desired conductive path to a thin metal wire. The problem is solved by covering the semiconductor element and the fine metal wire with each other, molding with an insulating resin so as to fill the groove, and separating the conductive path to be formed.

According to the present manufacturing method, a through hole can be made unnecessary, and at the same time, a conductive foil is used as a support substrate and a conductive path, the number of components is minimized, and the conductive path does not come off from the insulating resin. It has a structure. Moreover, since the top of the fine metal wire can be set low by forming the groove, the thickness of the semiconductor device can be reduced.

Further, an eave is formed on the surface of the conductive path,
An insulating resin that covers the eaves and fills the separation groove prevents the conductive path from coming off.

[0032]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment for Explaining Semiconductor Device First, the structure of a semiconductor device of the present invention will be described with reference to FIG.

FIG. 1 shows a first conductive path 51A supported by an insulating resin 50, a second conductive path 51B embedded in the insulating resin 50, and a third conductive path 51C. A semiconductor device 53 in which a semiconductor element 52 is fixed on the first conductive path 51A is shown.

In this structure, the semiconductor element 52A and the circuit element 5
2B, a plurality of conductive paths 51A, 51B, and 51C, and an insulating resin 50 that supports and embeds the conductive paths 51A, 51B, and 51C. Groove 5 filled with conductive resin 50
4 are provided.

As the insulating resin, a thermosetting resin such as an epoxy resin, or a thermoplastic resin such as a polyimide resin or polyphenylene sulfide can be used. As the insulating resin, any resin can be adopted as long as the resin can be hardened using a mold, or can be coated by dipping or coating. Further, as the conductive path 51, a conductive foil mainly composed of Cu, a conductive foil mainly composed of Al, a conductive foil composed of an alloy such as Fe-Ni, or the like can be used. Of course, other conductive materials are also possible. Particularly, a conductive material that can be etched and a conductive material that evaporates by laser are preferable.

The connection means of the semiconductor element 52A is a thin metal wire 55A, a brazing material such as solder, or a conductive coating 55C such as Ag paste or a conductive material. As the circuit element 52B such as a chip resistor and a chip capacitor, the solder 55B is selected.

The semiconductor element 52A and the first conductive path 51
For fixing to A, an insulating adhesive is selected if no electrical connection is required, and a conductive material 55C is employed if an electrical connection is required. Here, the conductive material may be at least one layer.

The material considered as the conductive material 55C is Ag, Au, Pt, Pd, or the like, which is deposited under low or high vacuum such as evaporation, sputtering, or CVD, plating, or sintering of a conductive paste. Coated.

For example, Ag adheres to Au and also adheres to the brazing material. Therefore, if the Au film is coated on the back surface of the chip, the chip can be thermocompression-bonded by directly covering the conductive path 51A with the Ag film, Au film, or solder film, and the chip can be fixed via a brazing material such as solder. .
Here, the conductive film may be formed on the uppermost layer of the conductive film laminated in a plurality of layers. For example, a conductive path 51 of Cu
On top of A, two layers of Ni coating and Au coating are sequentially applied, three layers of Ni coating, Cu coating and solder coating are sequentially applied, two layers of Ag coating and Ni coating are provided. Those coated in order can be formed. There are many other types and laminated structures of these conductive films, but they are omitted here.

In the present semiconductor device, since the conductive path 51 is supported by the insulating resin 50 as a sealing resin, a support substrate is not required, and the conductive path 51, the semiconductor element 52, and the circuit element 52 are not required.
B and an insulating resin 50. This configuration is a feature of the present invention. As described in the section of the related art, the conductive path of the conventional semiconductor device is supported by a support substrate or supported by a lead frame. However, the present semiconductor device has a feature that it is thin and inexpensive because it is composed of the minimum necessary components and does not require a support substrate.

In addition to the above-described structure, the semiconductor element 52A,
There is an insulating resin 50 which covers the circuit element 52B and is filled in the separation groove 54 between the conductive paths 52 and integrally supported.

A separation groove 54 is formed between the conductive paths 51.
By filling the insulating resin 50 here, there is an advantage that mutual insulation is achieved.

The semiconductor element 52A and the circuit element 52B
And insulating resin 50 which is filled in the separation groove 54 between the conductive paths 51 and exposes the back surface of the conductive path 51 and integrally supports the same.
have.

The fact that the back surface of the conductive path is exposed is one of the features of the present invention. The back surface of the conductive path can be used for connection to the outside, and has the feature that the through hole TH of the conventional structure as shown in FIG. 25 can be omitted.

Further, when the semiconductor element is directly fixed to the first conductive path 51A via a conductive film of brazing material, Au, Ag, or the like, the back surface of the first conductive path 51A is exposed, so that the semiconductor element is exposed. Heat generated from the first conductive path 5
It can be transmitted to the mounting board via 1A. In particular, the present invention is effective for a semiconductor chip capable of improving characteristics such as an increase in drive current due to heat radiation.

The back surface of the semiconductor element 52A is set lower than the front surfaces of the conductive paths 51B and 51C other than the conductive path 51A to which the semiconductor element 52A is fixed. By doing so, the surface of the semiconductor element 52A can be lowered, and the top of the thin metal wire 55A connecting the semiconductor element 52A and the conductive path 51B can be set low. In the drawing, the circuit element 52B has the fine metal wire 55
Since the height of the insulating resin 50 is higher than the top of A, the thickness of the insulating resin 50 is determined by the circuit element 52B. However, if the thickness of the circuit element 52B is thin and the top of the fine metal wire 55A is higher than the circuit element 52B, the insulating resin The thickness of 50 is determined by the thin metal wire 55A. Therefore, in this case, the thickness of the semiconductor device 53 can be reduced by an amount corresponding to a decrease in the top of the thin metal wire 55A.

On the other hand, FIG. 1C shows the back surface polished until the conductive film 55C formed on the back surface of the semiconductor element 52A is exposed. In this case, the present semiconductor device has a structure in which the back surface of the separation groove 54 and the back surface of the conductive path 51 substantially match. This structure corresponds to the back electrode 1 shown in FIG.
Since the steps 0 and 11 are not provided, the semiconductor device 53 can be moved horizontally as it is. Second Embodiment for Explaining Semiconductor Device Next, a semiconductor device 53 shown in FIG. 2 will be described.

In this structure, the wirings L1 to L
3 are formed, and the rest is substantially the same as the structure of FIG. Therefore, the wirings L1 to L3 will be described.

As described above, IC circuits range from small-scale circuits to large-scale circuits. However, here, for the sake of illustration, a small-scale circuit is shown in FIG. 2A. This circuit is frequently used in an audio amplifier circuit, and is a circuit in which a differential amplifier circuit and a current mirror circuit are connected. As shown in FIG. 2A, the differential amplifier circuit is composed of TR1 and TR2, and the current mirror circuit is mainly composed of TR3 and TR4.

FIG. 2B is a plan view when the circuit of FIG. 2A is realized as the present semiconductor device. FIG. 2C is a plan view of FIG.
FIG. 2D is a cross-sectional view taken along a line BB. A die pad 51A on which TR1 and TR3 are mounted is provided on the left side of FIG. 2B, and a die pad 51D on which TR2 and TR4 are mounted is provided on the right side. External connection electrodes 51B, 51E to 51G are provided above the die pads 51A, 51D, and 51C, 51H to 51J are provided below. still,
B and E indicate a base electrode and an emitter electrode. Since the emitter of TR1 and the emitter of TR2 are commonly connected, the wiring L2 is formed integrally with the electrodes 51E and 51G. Also the base of TR3 and T
Since the base of R4, the emitter of TR3 and the emitter of TR4 are commonly connected, the wiring L1 is connected to the electrodes 51C and 55C.
J and the wiring L3 are connected to the electrodes 55H and 5H.
It is provided integrally with 5I.

The wirings L1 to L3 have characteristics, and
In FIG. 8, the wiring 25 and the wiring 29 correspond to this. The wiring varies depending on the degree of integration of the circuit device, but has a very narrow width of 25 μm or more.
The width of 25 μm is a numerical value when wet etching is employed, and if dry etching is employed,
This width can be further reduced.

As is clear from FIG. 2D, the conductive path 51K constituting the wiring L1 has the wiring buried in the insulating resin 50, and therefore, as shown in FIGS. Is different from that where
1K can be prevented from coming off and warping. In particular,
As is apparent from the manufacturing method described later, a structure in which the conductive path does not fall out of the insulating resin due to the rough side surface of the wiring 51K, the formation of the eaves on the surface, etc. Becomes The structure having the eaves will be described with reference to FIG.

The external connection electrodes 51B, 51C, 5
Since 51E to 51J are embedded with the insulating resin as described above, even if an external force is applied from the external lead fixed here, the structure is difficult to peel off. Where the resistance R
Although 1 and the capacitor C1 are omitted, they may be mounted on a conductive path. As will be described later in an embodiment of a mounting structure, it may be mounted on the back surface of the circuit device or on the mounting substrate side. Third Embodiment Explaining Semiconductor Device Next, a semiconductor device 56 shown in FIG. 8 will be described.

This structure is substantially the same as the structure of FIG. 1 except that a conductive film 57 is formed on the surfaces of the conductive paths 51B and 51C. Therefore, the conductive film 57 will be described.

The first feature is that a conductive film 57 is provided in order to prevent the conductive path and the semiconductor device from warping.

Generally, due to the difference in the thermal expansion coefficient between the insulating resin and the conductive path material (hereinafter, referred to as a first material), the semiconductor device warps, and the conductive path is bent or peeled off. In addition, since the thermal conductivity of the conductive path 51 is superior to the thermal conductivity of the insulating resin, the conductive path 51 expands by increasing the temperature first. Therefore, by covering the second material having a smaller coefficient of thermal expansion than the first material, it is possible to prevent the conductive path from being warped or peeled off, and to prevent the semiconductor device from being warped. In particular, when Cu is used as the first material, Au, Ni, Pt, or the like is preferable as the second material. The expansion coefficient of Cu is 16.7 × 10 −6 (10 minus the sixth power).
Where Au is 14 × 10 −6 and Ni is 12.8 × 10
−6 and Pt are 8.9 × 10 −6.

The second feature is that the second material has an anchor effect. The eaves 58 are formed of the second material, and the eaves 5 are attached to the conductive paths 51.
Since 8 is embedded in the insulating resin 50, an anchor effect is generated, and a structure that can prevent the conductive paths 51B and 51C from coming off is obtained.

Although the semiconductor device in which the transistor chip 52A and the passive element 52B as a circuit element are mounted as the semiconductor device has been described above, the present invention relates to a semiconductor device in which one semiconductor chip is sealed, As shown in FIG. 21, a semiconductor device in which a face-down type element such as a CSP is mounted, or a semiconductor device in which passive elements such as a chip resistor and a chip capacitor are sealed as shown in FIG. Further, a thin metal wire may be connected between the two conductive paths and sealed. This can be used as a fuse. First Embodiment for Describing Method of Manufacturing Semiconductor Device Next, a method of manufacturing a semiconductor device 53 will be described with reference to FIGS. 3 to 7 and FIG.

First, as shown in FIG. 3, a sheet-shaped conductive foil 60 is prepared. The material of the conductive foil 60 is selected in consideration of the adhesion of the brazing material, the bonding property, and the plating property.
As the material, a conductive foil mainly containing Cu, a conductive foil mainly containing Al, a conductive foil made of an alloy such as Fe-Ni, or the like is used.

The thickness of the conductive foil is preferably about 10 μm to 300 μm in consideration of the later etching.
A 0 μm (2 oz) copper foil was employed. But 300μ
Basically, it is good even if it is more than m or less than 10 μm. As will be described later, it is only necessary that the separation groove 61 shallower than the thickness of the conductive foil 60 can be formed.

The sheet-shaped conductive foil 60 is prepared by being wound into a roll with a predetermined width, and may be conveyed to each step described later, or the conductive foil cut into a predetermined size may be used. It may be prepared and transported to each step described later. Subsequently, a region RG where the semiconductor device is mounted, this region RG
In addition, there is a step of removing the conductive foil 60 excluding the regions that become the conductive paths 51B and 51C to a thickness smaller than the thickness of the conductive foil 60. Then, the semiconductor element 52A is mounted on the region RG,
There is a step of coating the insulating resin 50 on the semiconductor element 52A, the separation groove 61 and the conductive foil 60.

First, a photoresist (etching resistant mask) PR is formed on the Cu foil 60 so that the conductive foil 60 corresponding to the region RG is exposed and the conductive paths 51B and 51 are formed.
The photoresist PR is patterned so as to expose the conductive foil 60 excluding the region to become C (see FIG. 4).
Then, etching may be performed through the photoresist PR (see FIG. 5).

The depth of the groove 61 formed by etching is, for example, 50 μm, and the side surface thereof is rough, so that the adhesiveness with the insulating resin 50 is improved.

Although the side wall of the groove 61 is schematically shown as straight, it has a different structure depending on the removing method. This removal step can employ wet etching, dry etching, laser evaporation, and dicing.
In the case of wet etching, ferric chloride or cupric chloride is mainly used as an etchant, and the conductive foil is dipped in the etchant or showered with the etchant. Here, since the wet etching is generally performed non-anisotropically, the side surface has a curved structure.

In the case of dry etching, anisotropy,
Non-anisotropic etching is possible. At present, it is said that it is impossible to remove Cu by reactive ion etching, but it can be removed by sputtering. Further, etching can be performed anisotropically or non-anisotropically depending on sputtering conditions.

In the case of a laser, a separation groove can be formed by directly irradiating a laser beam. In this case, the side surface of the separation groove 61 is formed straight.

In dicing, it is impossible to form a bent complicated pattern, but it is possible to form a lattice-shaped separation groove.

In FIG. 4, a conductive film having corrosion resistance to an etching solution may be selectively coated instead of the photoresist. When the conductive film is selectively applied to a portion to be a conductive path, the conductive film serves as an etching protective film, and the separation groove can be etched without employing a resist. Materials that can be considered as the conductive film include Ni, Ag, Au,
Pt or Pd. Moreover, these corrosion-resistant conductive films have a feature that they can be utilized as they are as die pads and bonding pads.

For example, an Ag film adheres to Au and also adheres to a brazing material. Therefore, if the Au film is coated on the back surface of the chip, the chip can be thermocompression-bonded to the Ag film on the conductive path 51 as it is, and the chip can be fixed via a brazing material such as solder. Further, since the Au thin wire can be bonded to the Ag conductive film, wire bonding is also possible. Therefore, there is an advantage that these conductive films can be used as die pads and bonding pads as they are.

Subsequently, as shown in FIG. 6, there is a step of electrically connecting and mounting the semiconductor element 52A and the circuit element 52B to the conductive foil 60 in which the separation groove 61 is formed.

The semiconductor element 52A is a semiconductor element such as a transistor, a diode, or an IC chip, and the circuit element 52B is a passive element such as a chip capacitor or a chip resistor. Also, although the thickness will be thicker, CS
Face-down semiconductor elements such as P and BGA can also be mounted.

Here, the bare transistor chip 52
A is die-bonded to the conductive path 51A, and the emitter electrode and the conductive path 51B and the base electrode and the conductive path 51B are connected via a thin metal wire 55A fixed by ball bonding by thermocompression bonding or wet bonding by ultrasonic waves. . Reference numeral 52B denotes a passive element such as a chip capacitor or a chip resistor, which is fixed with a brazing material such as solder or a conductive paste 55B.

Further, as shown in FIG.
And a step of attaching the insulating resin 50 to the separation groove 61. This can be achieved by transfer molding, injection molding, or dipping. As the resin material, a thermosetting resin such as an epoxy resin can be realized by transfer molding, and a thermoplastic resin such as a polyimide resin and polyphenylene sulfide can be realized by injection molding.

In the present embodiment, the thickness of the insulating resin coated on the surface of conductive foil 60 is, for example, about 10 mm from the top.
It is adjusted so that about 0 μm is covered. This thickness can be increased or reduced in consideration of strength.

The feature of this step is that the conductive foil 60 serving as the conductive path 51 becomes a supporting substrate until the insulating resin 50 is covered. In the related art, as shown in FIG. 26, the conductive paths 7 to 11 are formed by using the support substrate 5 which is not originally required. However, in the present invention, the conductive foil 60 serving as the support substrate is required as an electrode material. Material. Therefore, there is a merit that the operation can be performed while omitting the constituent materials as much as possible, and the cost can be reduced.

Since the separation grooves 61 are formed shallower than the thickness of the conductive foil, the conductive foils 60 are not individually separated as the conductive paths 51. Therefore, the sheet-shaped conductive foil 60
When molding insulating resin,
It has the feature that the work of transporting to the mold and mounting on the mold is very easy.

Subsequently, there is a step of chemically and / or physically removing the back surface of the conductive foil 60 and separating it as the conductive path 51. Here, the removing step is performed by polishing, grinding, etching, laser metal evaporation, or the like.

In FIG. 7, an etching resistant mask PR is formed on the conductive foil 60 corresponding to the conductive paths 51A to 51C.
When the conductive foil exposed from the etching mask PR is etched, the conductive foil has a shape as shown in FIG. 1A.

In FIG. 7, the entire surface is shaved by about 30 μm by a polishing device or a grinding device to expose the insulating resin 50 from the separation groove 61. FIG. 1C shows an example realized by this method. As a result, the conductive paths 51 having a thickness of about 40 μm are separated. In addition, insulating resin 50
Until the surface is exposed, the entire surface of the conductive foil 60 is wet-etched. Thereafter, the entire surface is ground by a polishing or grinding device.
The insulating resin 50 may be exposed.

As a result, a structure in which the surface of the conductive path 51 is exposed to the insulating resin 50 is obtained. Then, the separation groove 61 is shaved to form the separation groove 54 of FIG. (Refer to FIG. 7 above.) Finally, a conductive material such as solder is applied to the back surface of the conductive path 51 which is exposed as necessary, thereby completing a semiconductor device.

When a conductive film is applied on the back surface of the conductive path 51, the conductive film may be formed on the back surface of the conductive foil in advance. In this case, the portion corresponding to the conductive path may be selectively applied. The deposition method is, for example, plating. The conductive film is preferably made of a material (Ag, Au) having resistance to etching. When this conductive film is employed, it can be separated as the conductive path 51 only by etching without polishing.

In the present manufacturing method, only the semiconductor element and the passive element are mounted on the conductive foil 60, but these may be arranged in a matrix as one unit, or either one of the semiconductor elements may be arranged. May be arranged as a unit in a matrix. In this case, as will be described later, they are individually separated by a dicing device.

By the above manufacturing method, the insulating resin 50
The conductive paths 51B and 51C are embedded in the
The semiconductor device 53 having a reduced top portion can be realized.

The feature of the present manufacturing method is that the conductive path 51 can be separated using the insulating resin 50 as a supporting substrate. The insulating resin 50 is a material necessary as a material for embedding the conductive path 51, and does not require an unnecessary support substrate 5 unlike the conventional manufacturing method of FIG. Therefore, it has a feature that it can be manufactured with a minimum amount of material and that cost reduction can be realized.

The thickness of the insulating resin from the surface of the conductive path 51 can be adjusted when the insulating resin is adhered in the previous step. Therefore, although it differs depending on the semiconductor element to be mounted, the thickness as the semiconductor device 56 can be made thicker or thinner. Here, the insulating resin 50 having a thickness of 400 μm
A semiconductor device in which a conductive path 51 of μm and a semiconductor element having a reduced height are embedded is obtained. (Refer to FIG. 1) Second Embodiment for Describing a Method of Manufacturing a Semiconductor Device Next, a method of manufacturing a semiconductor device 56 having an eave 58 will be described with reference to FIGS. 9 to 13 and FIG. Note that, except that the second material 70 serving as an eaves is adhered, the second embodiment is substantially the same as the first embodiment, and thus detailed description is omitted.

First, as shown in FIG. 9, a second material 70 having a small etching rate is placed on a conductive foil 60 made of a first material.
A conductive foil 60 coated with is prepared.

For example, when Ni is deposited on a Cu foil, Cu and Ni can be etched at a time with ferric chloride or cupric chloride, and Ni has an eave 5 due to a difference in etching rate.
8, which is preferable. Thick solid line is Ni
And a film thickness of 1 to 10 μm.
The degree is preferred. Also, as the thickness of Ni increases, the eaves 58 increase.
Are easily formed.

The second material may be coated with a material which can be selectively etched with the first material. In this case, first, a film made of the second material is patterned so as to cover the formation region of the conductive path 51, and the first film is formed using this film as a mask.
If the conductive foil 60 made of the above material is etched, the eaves 5
8 can be formed. As the second material, Ni
Besides, Al, Ag, Au and the like can be considered. When Ag or Au is used as the second material, partial plating may be formed. (Refer to FIG. 9 above.) Subsequently, there is a step of removing the conductive foil 60 excluding the region RG where the semiconductor element 52A is to be formed and at least the regions to be the conductive paths 51B and 51C to be thinner than the thickness of the conductive foil 60.

A photoresist PR is formed on Ni70, the region RG where the semiconductor element 52A is to be formed, the conductive path 5
The photoresist PR may be patterned so as to expose the Ni 70 excluding the regions 1B and 51C, and may be etched through the photoresist.

As described above, when etching is performed by using an etchant of ferric chloride or cupric chloride or the like, since the etching rate of Ni70 is lower than the etching rate of Cu60, the eaves 58 appear as the etching proceeds.

The conductive foil 6 on which the separation groove 61 is formed
0, a step of mounting the semiconductor element 52A and the circuit element 52B (FIG. 12), covering the conductive foil 60 and the separation groove 61 with an insulating resin 50, and chemically and / or
Alternatively, the step of physically removing the conductive path 51 (FIG. 13) and the step of forming a conductive film on the rear surface of the conductive path to completion (FIG. 8) are the same as those in the previous manufacturing method. Omitted. Third Embodiment for Demonstrating Method of Manufacturing Semiconductor Element Subsequently, a manufacturing method in which the semiconductor devices 53 of FIG. 2 are arranged in a matrix and separated individually after sealing will be described with reference to FIGS. . Since this manufacturing method is almost the same as the first embodiment, the same parts will be described briefly.

First, as shown in FIG. 14, a sheet-like conductive foil 60
Prepare

The sheet-shaped conductive foil 60 is prepared by being wound into a roll with a predetermined width, and may be conveyed to each step described later, or the conductive foil cut into a predetermined size may be used. It may be prepared and transported to each step described later.

Subsequently, a region where the semiconductor element 52A is formed (here, two semiconductor elements are connected to the conductive path 51A (51)
D), it is a region where the conductive paths 51A (51D) are formed), and at least the conductive paths 51B, 51
C, the conductive foil 60 excluding the regions to be 51E to 55J,
There is a step of removing the conductive foil 60 so as to be thinner than the thickness thereof.

As shown in FIG. 15, an etching-resistant mask PR is formed on a Cu foil 60, and as described above, the region where the semiconductor element 52A is formed, at least the conductive paths 51B, 5D.
The photoresist PR is patterned so as to expose the conductive foil 60 excluding regions 1C and 51E to 55J.
Then, as shown in FIG. 16, etching may be performed via the photoresist PR.

The depth of the separation groove 61 formed by etching is, for example, 50 μm, and the side surface thereof is roughened, so that the adhesiveness to the insulating resin 50 is improved.

The side wall of the separation groove 61 is schematically shown as a straight line, but has a different structure depending on the removing method. This removal step can employ wet etching, dry etching, laser evaporation, and dicing. (Refer to the first embodiment for details.) In FIG. 15, a conductive film having corrosion resistance to an etching solution may be selectively coated instead of the photoresist PR. If selectively applied to the part that will be the conductive path,
This conductive film serves as an etching protection film, and the separation groove can be etched without using a resist.

Subsequently, as shown in FIG. 17, the semiconductor element 52A is fixed to and electrically connected to the conductive foil 60 corresponding to the RG, and the thin metal wire 55A connected to the electrode on the surface of the semiconductor element 52A is connected to the conductive path 55B. There is a step of connecting to.

The semiconductor element 52A is a semiconductor element such as a transistor, a diode, or an IC chip. In addition, a passive element such as a chip capacitor or a chip resistor may be mounted as shown in FIG.

Here, the bare transistor chip 52
A is die-bonded to the groove, and the emitter electrode and the conductive path 51B, and the base electrode and the conductive path 51C are connected via the fine metal wire 55A.

Further, as shown in FIG.
There is a step of attaching the insulating resin 50 to the separation groove 61 and the separation groove 61. This can be achieved by transfer molding, injection molding, or dipping.

In the present embodiment, the thickness of the insulating resin coated on the surface of the conductive foil 60 is adjusted so as to cover about 100 μm from the top of the semiconductor element. This thickness can be increased or reduced in consideration of strength.

The feature of this step is that, when the insulating resin 50 is coated, the conductive foil 60 serving as the conductive path 51 serves as a support substrate. In the related art, as shown in FIG. 26, the conductive paths 7 to 11 are formed by using the support substrate 5 which is not originally required. However, in the present invention, the conductive foil 60 serving as the support substrate is required as an electrode material. Material. Therefore, there is a merit that the operation can be performed while omitting the constituent materials as much as possible, and the cost can be reduced.

Since the separation grooves 61 are formed shallower than the thickness of the conductive foil, the conductive foils 60 are not individually separated as the conductive paths 51. Therefore, the sheet-shaped conductive foil 60
When molding insulating resin,
It has the feature that the work of transporting to the mold and mounting on the mold is very easy.

Subsequently, there is a step of chemically and / or physically removing the back surface of the conductive foil 60 and separating it as the conductive path 51. Here, the removing step is performed by polishing, grinding, etching, laser metal evaporation, or the like.

In the experiment, the entire surface was shaved by about 30 μm with a polishing device or a grinding device to expose the insulating resin 50. As a result, the conductive paths 51 having a thickness of about 40 μm are separated. Until the insulating resin 50 is exposed,
The entire surface of the conductive foil 60 may be wet-etched, and thereafter, the entire surface may be shaved by a polishing or grinding device to expose the insulating resin 50.

As a result, a structure in which the surface of the conductive path 51 is exposed to the insulating resin 50 is obtained.

Further, as shown in FIG.
Is coated with a conductive material CM such as solder.

Finally, as shown in FIG. 20, there is a step of separating semiconductor devices.

The separation line is indicated by an arrow and can be realized by dicing, cutting, pressing, chocolate break, or the like. When a chocolate break is adopted, a protrusion may be formed on the mold so that a groove is formed in the separation line when the insulating resin is coated.

In particular, dicing is preferred because it is frequently used in a normal method of manufacturing a semiconductor device and can separate very small objects.

The right side of FIG. 27 shows a flow chart briefly summarizing the present invention. Preparation of Cu foil, Ag or N
A semiconductor device can be realized by nine steps of plating of i, etc., half etching, die bonding, wire bonding, transfer molding, removal of backside Cu foil, backside treatment of conductive paths, and dicing. Moreover, all processes can be performed in-house without supplying a supporting substrate from a manufacturer.
Embodiments describing types of semiconductor devices and methods for mounting them.

FIG. 21 shows a semiconductor device 81 on which a face-down type semiconductor element 80 is mounted. The semiconductor element 80 corresponds to a bare semiconductor chip, a CSP or BGA having a sealed surface. FIG. 22 shows a semiconductor device 83 on which a passive element 82 such as a chip resistor or a chip resistor is mounted. Since they do not require a supporting substrate, they are thin and are sealed with an insulating resin, so that they have excellent environmental resistance.

FIG. 23A explains a real layer structure. The semiconductor device 53, 81, 83 of the present invention described so far is mounted on a conductive path 85 formed on a mounting board 84 such as a printed board, a metal board, or a ceramic board.

In particular, since the conductive path 51A to which the back surface of the semiconductor chip 52 is fixed is thermally coupled to the conductive path 85 of the mounting board 84, heat can be radiated through the conductive path 85. When a metal substrate is used as the mounting substrate 84, the heat dissipation of the metal substrate is also helped, and the temperature of the semiconductor chip 52 can be further reduced. Therefore, the driving capability of the semiconductor chip can be improved.

For example, power MOS, IGBT, SIT,
Transistor for driving large current, IC for driving large current (M
OS type, BIP type, Bi-CMOS type) memory element and the like are preferable.

As the metal substrate, an Al substrate, a Cu substrate, or an Fe substrate is preferable, and an insulating resin and / or an oxide film is formed in consideration of a short circuit with the conductive path 85.

FIG. 23B shows a case where the present semiconductor device is used as a mounting substrate. It is as if the elements are mounted on a printed circuit board. In the semiconductor device 90, since the conductive path is exposed, an element can be mounted thereon. Here, a chip capacitor 92 and a discrete semiconductor device 91 formed by this manufacturing method are mounted.

[0119]

As is apparent from the above description, according to the present invention, a semiconductor device which is constituted by the minimum required of the semiconductor element, the conductive path and the insulating resin, and has no waste of resources. Therefore, a semiconductor device which has no extra components until completion and can greatly reduce the cost can be realized. In addition, by optimizing the coating thickness of the insulating resin and the thickness of the conductive foil,
Further, by setting the back surface of the semiconductor element to be lower than the front surfaces of the other conductive paths, the semiconductor device can be made thinner, and a smaller and lighter semiconductor device can be realized. Furthermore, since the wiring in which the phenomenon of warpage or peeling is remarkable is embedded and supported in the insulating resin, these problems can be solved.

Since only the back surface of the conductive path is exposed from the insulating resin, the back surface of the conductive path can be immediately used for connection to the outside, and the back electrode and the through-hole of the conventional structure as shown in FIG. 26 are unnecessary. It has the advantage that can be.

In addition, since the semiconductor element is directly fixed to the conductive path via a conductive film such as brazing material, Au, Ag, or the like, or the back surface of the semiconductor element is exposed, heat generated from the semiconductor element is transferred to the conductive path. The heat can be directly transmitted to the mounting substrate via the heat sink. In particular, this heat dissipation makes it possible to mount a power element.

Further, since the eaves can be formed on the surface of the conductive path, an anchor effect can be generated, and the conductive path, in particular, the wiring can be prevented from being warped or removed.

In the method of manufacturing a semiconductor device according to the present invention,
When the conductive foil itself functions as a support substrate, the whole is supported by the conductive foil until the separation groove is formed or the semiconductor element is mounted and the insulating resin is attached, and when the conductive foil is separated as each conductive path, The insulating resin functions as a supporting substrate. Therefore, the semiconductor device, the conductive foil, and the insulating resin can be manufactured with the minimum necessary. As described in the conventional example, a support substrate is not required for configuring a semiconductor device, and the cost can be reduced. Also, by eliminating the need for a support substrate, the fact that the conductive paths are embedded in the insulating resin, and furthermore that the thickness of the insulating resin and the conductive foil can be adjusted,
There is also an advantage that a very thin semiconductor device can be formed.

Further, since the step of forming a through hole, the step of printing a conductor (in the case of a ceramic substrate), and the like can be omitted, there is an advantage that the manufacturing process can be greatly reduced as compared with the related art, and the entire process can be performed internally. In addition, no frame mold is required at all, and the manufacturing method has a very short delivery time.

Next, since the conductive paths can be handled without being separated, the workability is improved in the subsequent step of coating the insulating resin.

Finally, since the semiconductor device can be mounted on the exposed conductive path by utilizing the present semiconductor device as a support substrate, a high-performance substrate module can be realized. In particular, if the present semiconductor device is used as a support substrate and the present semiconductor device is mounted thereon as an element, a lighter and thinner substrate module can be realized.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a circuit device of the present invention.

FIG. 2 is a diagram illustrating a circuit device according to the present invention.

FIG. 3 is a diagram illustrating a method for manufacturing a circuit device according to the present invention.

FIG. 4 is a diagram illustrating a method for manufacturing a circuit device according to the present invention.

FIG. 5 is a diagram illustrating a method for manufacturing a circuit device according to the present invention.

FIG. 6 is a diagram illustrating a method for manufacturing a circuit device according to the present invention.

FIG. 7 is a diagram illustrating a method for manufacturing a circuit device according to the present invention.

FIG. 8 is a diagram illustrating a circuit device according to the present invention.

FIG. 9 is a diagram illustrating a method for manufacturing a circuit device according to the present invention.

FIG. 10 is a diagram illustrating a method for manufacturing a circuit device according to the present invention.

FIG. 11 is a diagram illustrating a method for manufacturing a circuit device according to the present invention.

FIG. 12 is a diagram illustrating a method for manufacturing a circuit device according to the present invention.

FIG. 13 is a diagram illustrating a method for manufacturing a circuit device according to the present invention.

FIG. 14 is a diagram illustrating a method for manufacturing a circuit device according to the present invention.

FIG. 15 is a diagram illustrating a method for manufacturing a circuit device according to the present invention.

FIG. 16 is a diagram illustrating a method for manufacturing a circuit device according to the present invention.

FIG. 17 is a diagram illustrating a method for manufacturing a circuit device according to the present invention.

FIG. 18 is a diagram illustrating a method for manufacturing a circuit device according to the present invention.

FIG. 19 is a diagram illustrating a method for manufacturing a circuit device according to the present invention.

FIG. 20 is a diagram illustrating a method for manufacturing a circuit device according to the present invention.

FIG. 21 is a diagram illustrating a circuit device of the present invention.

FIG. 22 is a diagram illustrating a circuit device according to the present invention.

FIG. 23 is a diagram illustrating a method for mounting the circuit device of the present invention.

FIG. 24 is a diagram illustrating a mounting structure of a conventional circuit device.

FIG. 25 is a diagram illustrating a conventional circuit device.

FIG. 26 is a diagram illustrating a method for manufacturing a conventional circuit device.

FIG. 27 is a diagram illustrating a method for manufacturing a circuit device according to the related art and the present invention.

FIG. 28 is a pattern diagram of an IC circuit applied to the circuit devices of the related art and the present invention.

[Explanation of symbols]

 Reference Signs List 50 Insulating resin 51A to 51C Conducting path 52A Semiconductor element 52B Passive element 53 Semiconductor device 54 Separation groove 58 Eave

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) H01L 25/00 H01L 23/12 L (72) Inventor Junji Sakamoto 2-5-2-5 Keihanhondori, Moriguchi-shi, Osaka 3 (72) Inventor Shigeaki Mashimo 2-5-5 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. (72) Katsumi Okawa 2-5-5-1 Keihanhondori, Moriguchi-shi, Osaka No. Sanyo Electric Co., Ltd. (72) Inventor Eiji Maehara 2-5-5 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. (72) Inventor Koji Takahashi 29 Kita-cho, Isesaki-shi, Gunma Kanto Sanyo F term (reference) in Electronics Co., Ltd. 4M109 AA01 BA01 CA07 CA10 CA21 DB02 EA02 EA07 EA13 GA02 5F067 AA01 AA04 AA05 AA11 AB04 BC12 CA04 DA01 DA16 DC16 DC17 DC18 EA02 EA04 EA06

Claims (19)

[Claims] 1. A plurality of conductive paths electrically separated by a separation groove, a thin metal wire connecting the conductive path and an electrode of a semiconductor element, and the separation between the conductive paths covering the semiconductor element. A semiconductor device, comprising: a groove filled with a back surface of the conductive path; and an insulating resin for exposing and integrally supporting the back surface of the semiconductor element. 2. A plurality of conductive paths electrically separated by a separating groove, a thin metal wire connecting the conductive path to an electrode of a semiconductor element, and the separation between the conductive paths covering the semiconductor element. A semiconductor device, comprising: an insulating resin that is filled in a groove and that exposes and integrally supports a back surface of the conductive path and a back surface of the semiconductor element. A semiconductor device characterized in that: 3. A plurality of conductive paths electrically separated by a separation groove, a semiconductor element fixed on a first conductive path, and a thin metal wire connecting an electrode of the semiconductor element and a second conductive path. And an insulating resin that covers the semiconductor element and fills the separation groove between the conductive paths and exposes the back surface of the conductive path to integrally support the insulating element. 1. A semiconductor device, wherein the height of the conductive path is reduced. 4. The semiconductor device according to claim 1, wherein said conductive path is formed of a conductive foil of any of copper, aluminum, and iron-nickel. 5. The semiconductor device according to claim 1, wherein a conductive film made of a metal material different from that of the conductive path is provided on an upper surface of the conductive path. 6. The semiconductor device according to claim 5, wherein said conductive film is made of nickel, gold or silver. 7. The semiconductor device according to claim 1, wherein the semiconductor element is a bare chip, and another chip circuit component is mounted on the conductive path. 8. The circuit according to claim 7, wherein at least one of the conductive paths is formed as a wiring, and the wiring forms a circuit together with the semiconductor element and the chip circuit component. Semiconductor device. 9. The semiconductor device according to claim 1, wherein a side surface of said conductive path is curved. 10. A conductive foil is prepared, and a groove shallower than the thickness of the conductive foil is formed in the conductive foil between conductive paths to be formed and in the conductive foil corresponding to a region where a semiconductor element is arranged. The semiconductor element is fixed to the groove to be arranged, an electrode of the semiconductor element is electrically connected to a desired conductive path by a thin metal wire, the semiconductor element and the thin metal wire are covered, and the groove is filled. A method of manufacturing a semiconductor device, wherein the conductive path to be formed is separated by molding with an insulating resin. 11. A conductive foil is prepared, and a groove shallower than the thickness of the conductive foil is formed by etching in the conductive foil corresponding to a region where a semiconductor element is to be arranged between conductive paths to be formed, and Forming an eave of a material different from that of the conductive foil on the conductive path to be formed by etching, fixing the semiconductor element in a groove in which the semiconductor element is arranged,
Electrically connecting an electrode of the semiconductor element and the desired conductive path with a thin metal wire, covering the semiconductor element and the thin metal wire, and molding with an insulating resin so as to fill the groove; A method for manufacturing a semiconductor device, comprising separating a predetermined conductive path. 12. The method of manufacturing a semiconductor device according to claim 10, further comprising a step of cutting the insulating resin to separate the semiconductor device into individual semiconductor devices. 13. The method according to claim 10, wherein after molding with the insulating resin, the insulating resin and the conductive foil are removed until the groove is exposed.
The method for manufacturing a semiconductor device according to any one of the above. 14. The conductive material formed on the back surface of the semiconductor element or the back surface of the semiconductor element is exposed.
4. The method for manufacturing a semiconductor device according to item 3. 15. The method of manufacturing a semiconductor device according to claim 13, wherein a back surface of said conductive path substantially coincides with a back surface of said insulating resin. 16. The conductive foil may be made of copper, aluminum or iron.
The method of manufacturing a semiconductor device according to claim 10, wherein the semiconductor device is made of nickel. 17. The method according to claim 11, wherein the eaves are formed of nickel, silver, or gold. 18. The semiconductor device according to claim 10, wherein a chip circuit component is fixed to said conductive path in addition to said semiconductor element.
A method for manufacturing a semiconductor device according to any one of claims 1 to 17. 19. The method of manufacturing a semiconductor device according to claim 10, wherein at least one of said conductive paths is a wiring, and a circuit is formed by said semiconductor element and said chip circuit component. Method.