JP2001251184A - Phase matching circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a phase matching circuit which can precisely control (adjust) a phase even if an input signal is the signal of a fast clock. SOLUTION: The phase matching circuit is provided with a phase comparator 2 comparing the phases of an input clock signal and an output clock signal and outputting a DC signal corresponding to a comparison result, an LPF 3, a phase control circuit 4 outputting a phase control signal for controlling the phase of the output clock signal, an arithmetic circuit 5 inputting and operating the DC signal from the LPF 3 and the phase control signal from the phase control circuit 4 and outputting a VCO control signal corresponding to an operated result and a VCO 6 outputting the output clock signal based on the VCO control signal from the arithmetic circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase matching circuit for performing phase control of an output signal by feeding back an output signal, and more particularly to a phase matching circuit for performing high-precision phase control (phase adjustment).

[0002]

2. Description of the Related Art As a conventional phase matching circuit, for example,
There is a "PLL circuit" disclosed in JP-A-6-164376. FIG. 9 is a diagram showing a schematic configuration of a conventional PLL circuit disclosed in Japanese Patent Laying-Open No. 6-164376. The PLL circuit 91 delays an input signal by a predetermined time and outputs the delayed signal, a frequency divider 93 that divides an output clock signal of the PLL circuit 91 and outputs the signal, and a signal and a frequency divider from the delay circuit 92. Input the signal from the device 93,
A phase comparator 94 for outputting a pulse signal corresponding to the phase difference between these input signals, a low-pass filter (LPF) 95 for time-smoothing the pulse signal from the phase comparator 94 and outputting a direct current (DC) signal; , DC from LPF95
Input the signal as the oscillation frequency control voltage, and
A voltage controlled oscillator (VCO) 96 for outputting a clock signal having a frequency corresponding to the signal.

In the operation of the PLL circuit 91, first, an input signal is delay-adjusted by a delay circuit 92. Also,
The output clock signal is divided by the divider 93. Next,
The phase comparator 94 compares the phase of the signal delay-adjusted by the delay circuit 92 with the phase of the signal frequency-divided by the frequency divider 93, and generates a pulse signal having a time width corresponding to the phase difference. The pulse signal generated by the phase comparator 94 is an LPF
At 95, the signal is time-averaged and smoothed, and becomes a DC signal containing information on the phase difference. The frequency of the output clock signal is controlled by the DC signal including the information on the phase difference.

The output clock signal whose frequency is controlled is
The signal is fed back to the phase comparator 94 via the frequency divider 93. When the phases of the two signals (the signal from the delay circuit 92 and the signal from the frequency divider 93) input to the phase comparator 94 become equal (become within a certain range), in other words, the output clock signal Is delayed by a predetermined time from the phase of the input signal, the phase of the output clock signal is fixed (locked). That is, the delay circuit 92
The phase of the output clock signal is controlled by adjusting the delay time of the input signal. Note that the signal passing through the delay circuit 92 undergoes waveform deterioration such as deterioration of the duty ratio.

[0005]

However, according to the above-mentioned prior art, the delay circuit 92 is arranged on the signal line of the input signal, and waveform deterioration such as deterioration of the duty ratio occurs. In the case of a signal of the order of gigahertz, there is a problem that this waveform deterioration cannot be ignored and the accuracy of phase control (phase adjustment) deteriorates.

The present invention has been made in view of the above, and an object of the present invention is to provide a phase matching circuit capable of performing accurate phase control (phase adjustment) even when an input signal is a high-speed clock signal. Aim.

[0007]

Means for Solving the Problems To solve the above-mentioned problems,
In order to achieve an object, in a phase matching circuit according to the present invention, in a phase matching circuit that performs phase control of an output signal based on a feedback signal, an offset is added to a signal that controls a frequency of the output signal. It is characterized by. According to the present invention, by adding an offset for controlling the phase of the output signal to the signal for controlling the frequency of the output signal, the phase of the output signal can be controlled without using a delay circuit.

In the phase matching circuit according to the next invention, in the phase matching circuit for controlling the phase of the output signal based on the feedback signal, the phase of the input signal and the phase of the feedback signal are compared. 1, a phase comparison means for outputting a comparison result signal, a phase control means for outputting a phase control signal for controlling a phase of the output signal, a first comparison result signal from the phase comparison means, and the phase control An arithmetic unit that inputs and calculates a phase control signal from the unit, outputs an operation result signal according to the operation result, and an oscillation unit that outputs the output signal based on the operation result signal from the operation unit. It is characterized by having.

According to the present invention, the phase comparing means compares the phase of the input signal with the phase of the feedback signal, and outputs a first comparison result signal according to the comparison result. A phase control signal for controlling the phase of the phase control signal, and the arithmetic means inputs the first comparison result signal from the phase comparison means and the phase control signal from the phase control means, calculates the phase control signal, and responds to the calculation result. Output the operation result signal,
The oscillating means outputs an output signal based on the operation result signal from the operation means. Thus, the phase of the output signal can be controlled without using a delay circuit.

The phase matching circuit according to the next invention further comprises a first frequency dividing means for dividing the output signal to generate a feedback signal to the phase comparing means. I do. According to this invention, the first frequency divider divides the output signal to generate a feedback signal to the phase comparator, so that the output signal can be output without using the delay circuit even when multiplying the output signal. The phase of the signal can be controlled.

The phase matching circuit according to the next invention further comprises a second frequency divider for dividing an external signal to generate an input signal to the phase comparator. And According to the present invention, the second frequency divider divides an external signal to generate an input signal to the phase comparator, thereby expanding the phase control range.

In the phase matching circuit according to the next invention, the phase comparing means compares the phases of the input signal and the feedback signal, and outputs a second signal corresponding to the comparison result.
And a second comparison result signal from the phase comparator which is time-smoothed to output the first comparison result signal.
Wherein the phase control means adjusts the phase control signal based on the first comparison result signal or the second comparison result signal from the phase comparison means. It is characterized by the following.

According to the present invention, the phase control means adjusts the phase control signal based on the first comparison result signal or the second comparison result signal from the phase comparison means, whereby the characteristics (PLL) of the phase matching circuit are adjusted. The phase control signal can be adjusted so that the phase difference is appropriately maintained even if the phase difference between the input and output signals fluctuates due to the variation in the characteristic.

In a phase matching circuit according to the next invention, the phase comparison means adjusts the phase control signal based on a calculation result signal from the calculation means. According to the present invention, the phase comparison means adjusts the phase control signal based on the operation result signal from the operation means, so that the phase difference is adjusted to an appropriate value even if the frequency of the input signal fluctuates. The control signal can be adjusted.

[0015] In the phase matching circuit according to the next invention, the phase comparison means adjusts the phase control signal based on a signal in one or a plurality of portions of a feedback loop of the phase matching circuit. I do. According to the present invention, the phase comparison means adjusts the phase control signal based on the signal in one or more parts of the feedback loop of the phase matching circuit, so that the frequency of the input signal and / or the phase difference between the input and output signals are reduced. Even if it fluctuates, the phase control signal can be adjusted so that the phase difference has an appropriate value.

The phase matching circuit according to the next invention further comprises a detecting means for detecting a state of the surrounding environment, wherein the phase comparing means detects the phase control signal based on a detection result of the detecting means. Is adjusted.
According to the present invention, the detecting means detects the state of the surrounding environment such as the ambient temperature, fluctuations in the power supply voltage, control signals from other circuits, and the like, and the phase comparing means detects the phase based on the detection result of the detecting means. Adjust the control signal. Thus, even if the phase difference between the input and output signals fluctuates due to a change in the state of the surrounding environment, the phase control signal can be adjusted so that the phase difference has an appropriate value.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a phase matching circuit according to the present invention will be described in detail with reference to the drawings.
The present invention is not limited by the embodiment.

Embodiment 1 Embodiment 1 of the present invention
In a phase matching circuit for controlling the phase of an output signal based on a feedback signal, a phase control signal for controlling the phase of the output signal is added to a signal for controlling the frequency of the output signal. . Hereinafter, first, the configuration of the first embodiment will be described with reference to FIG.
FIG. 1 is a diagram illustrating a schematic configuration of the phase matching circuit according to the first embodiment of the present invention.

The phase matching circuit 1 includes a voltage controlled oscillator (VCO) for generating an output clock signal of the phase matching circuit 1.
6, an input clock signal from the outside and an output clock signal fed back from the VCO 6 are input and compared, and a pulse signal (second comparison result signal of the present invention) having a time width according to the comparison result is output. A phase comparator 2, a low-pass filter (LPF) 3 for time-smoothing a pulse signal output from the phase comparator 2 and outputting a direct current (DC) signal (a first comparison result signal of the present invention), and an output clock signal A phase control circuit 4 for generating a phase control signal for shifting the phase of the input clock signal by a predetermined amount from the phase of the input clock signal;
3 and the phase control signal from the phase control circuit 4 are input and operated, and a VCO control signal (operation result signal of the present invention) for controlling the frequency of the output clock signal generated by the VCO 6 is output to the VCO 6 And an arithmetic circuit 5 for performing the operation.

The phase comparator 2 uses, for example, the voltage V0 of the VCO control signal such that the output clock signal has a predetermined frequency (frequency coincident with the frequency of the input clock signal) as a reference voltage, and uses this reference voltage V0 as the center. If the phase of the output clock signal is ahead of the phase of the input clock signal, a negative pulse is output, and if the phase of the output clock signal is behind the phase of the input clock signal, a positive pulse is output. The LPF 3 generates a DC signal by time-smoothing the pulse signal from the phase comparator 2. That is, the DC signal output from the LPF 3 includes information on the phase difference between the input and output clock signals. The phase control circuit 4 outputs a phase control signal of a predetermined voltage set in advance.

The phase control signal output from the phase control circuit 4 is a signal for delaying the phase of the output clock signal by a predetermined time. For example, when the phase of the output clock signal is shifted by a predetermined time, the VCO control signal is output. The voltage is set to be the reference voltage V0. The value of the VCO control signal is a PLL composed of the phase comparator 2, LPF3 and VCO6.
(Phase-locked loop). The arithmetic circuit 5 calculates and outputs, for example, a phase control signal from the phase control circuit 4 and a DC signal from the LPF 3. The operation of the arithmetic circuit 5 adjusts the offset of the VCO control signal.

The operation performed by the arithmetic circuit 5 is not particularly limited. For example, addition or subtraction is performed. VCO
6 outputs an output clock signal having a frequency corresponding to the VCO control signal from the arithmetic circuit 5. The output clock signal is
It becomes a feedback signal to the phase comparator 2. Note that L
PF3 corresponds to the smoothing means of the present invention, phase comparator 2 and LPF3 correspond to the phase comparing means of the present invention, and VCO 6 corresponds to the oscillating means of the present invention.

In the above configuration, the operation of the first embodiment will be described with reference to the timing charts of FIGS. FIG. 2 shows a phase matching circuit 1 according to the first embodiment when the phase control signal is not output (0 volt).
6 is a timing chart showing the operation of FIG. in this case,
PLL comprising phase comparator 2, LPF3 and VCO6
However, it operates in the same manner as in the conventional example described above, and the phase of the input clock signal matches the phase of the output clock signal (within a predetermined range). At this time, the pulse signal from the phase comparator 2 is constant at V0, the DC signal from the LPF is also constant at V0, and the VCO control signal from the arithmetic circuit 5 is also constant at V0. As a result, the frequency of the output clock signal becomes a predetermined value (a value that matches the frequency of the input clock signal) f0.

FIG. 3 is a timing chart showing the operation of the phase matching circuit 1 when the phase control signal according to the first embodiment is output. In the operation of the phase matching circuit 1, for example, if the phase control signal changes from 0 volts to ΔV volts when the phase control signal is 0 volt and the phases of the input and output clock signals match, The VCO control signal is offset in the positive direction.
As a result, the output clock signal from the VCO 6 is shifted to a high frequency and the phase is advanced.

The phase comparator 2 detects that the phase of the output clock signal has advanced, and outputs a pulse signal (negative pulse signal) for delaying the phase of the output clock signal. Due to the negative pulse signal from the phase comparator 2, D
The C signal decreases, the VCO control signal increased by the phase control signal decreases, and the frequency of the output clock signal from the VCO 6 decreases. When the frequency of the output clock signal matches the frequency of the input clock signal, the phase matching circuit 1 enters a steady state with the phase of the output clock signal leading the input clock signal by a predetermined amount.

The phase difference between the input and output clock signals is determined by the magnitude of the phase control signal. When the phase of the input / output clock signal is shifted by a predetermined time, the phase control signal
From the reference voltage V0 (-Δ
V) and a voltage (ΔV) of the opposite sign. When delaying the output clock signal, the phase control signal has a negative value. Alternatively, the arithmetic circuit 5 performs the subtraction. In the above example,
For the sake of explanation, the phase control signal is switched from 0 volts to ΔV volts, but it goes without saying that the phase control signal may always be ΔV volts.

As described above, according to the first embodiment,
When controlling the clock phase, the delay time of the input clock signal or the output clock signal is not directly controlled, so that loss and waveform deterioration due to insertion of a delay line for controlling the phase do not occur. Even with a high-speed input clock signal on the order of gigahertz, the phase can be controlled with a DC signal by the phase control signal, so that accurate delay adjustment can be performed.

Embodiment 2 Embodiment 2 of the present invention
In the first embodiment, a frequency divider that divides an output clock signal to generate a feedback signal is provided in the first embodiment to configure an M-multiplied PLL (M is an arbitrary integer). Hereinafter, first, the configuration of the second embodiment will be described with reference to FIG. FIG. 4 is a diagram showing a schematic configuration of the phase matching circuit according to the second embodiment of the present invention. Note that the basic configuration is the same as that of the first embodiment, and the same portions as those in FIG. 1 are denoted by the same reference numerals and description thereof is omitted, and only different portions will be described.

This phase matching circuit 11 is different from the phase matching circuit 1 of the first embodiment in that a frequency divider 12 for dividing the output clock signal from the VCO 6 by 1 / M to generate a divided clock signal is provided. Instead of a clock signal, a frequency divider 12
Is fed back to the phase comparator 2. The frequency divider 12 divides the frequency of the output clock signal by 1 / M, and outputs the frequency-divided clock signal to the phase comparator 2. The phase comparator 2, the LPF 3, the VCO 6, and the frequency divider 12 constitute an M-multiplier PLL. The frequency divider 12 corresponds to the first frequency dividing means of the present invention.

In the above configuration, the operation of the second embodiment will be described. In the second embodiment, an output clock signal having a frequency M times the input clock signal is output by feeding back the divided clock signal. Other operations are the same as those in the first embodiment, and a description thereof will be omitted.

As described above, according to the second embodiment,
In order to configure an M-multiplier PLL, the first embodiment is also used when an output clock signal faster than the input clock signal is required.
The same effect as described above can be obtained.

Embodiment 3 FIG. Embodiment 3 of the present invention
In the second embodiment, the input clock signal is not directly input to the phase comparator 2 but is input after being divided by a frequency divider. Hereinafter, first, the configuration of the third embodiment will be described with reference to FIG. FIG. 5 is a diagram showing a schematic configuration of the phase matching circuit according to the third embodiment of the present invention. Note that the basic configuration is the same as that of the second embodiment, and the same portions as those in FIG. 4 are denoted by the same reference numerals, and description thereof will be omitted. Only different portions will be described.

This phase matching circuit 21 is different from phase matching circuit 11 of the second embodiment in that the input clock signal is 1 / N
A frequency divider 22 for dividing the frequency (N is an arbitrary integer) to generate a frequency-divided clock signal is provided, and the frequency-divided clock signal from the frequency divider 22 is input to the phase comparator 2 instead of the input clock signal. It is like that. The frequency divider 22 divides the input clock signal by 1 / N and divides the frequency-divided clock signal by the phase comparator 2
Output to The frequency divider 22 corresponds to the second frequency dividing means of the present invention.

In the above configuration, the operation of the third embodiment will be described. In the third embodiment, the input clock signal is divided by 1 / N to output an output clock signal having a frequency M / N times the input clock signal. Further, since the frequency of the divided clock signal compared by the phase comparator 2 is 1 / N times that of the input clock signal, it is possible to obtain an N-fold phase control range as compared with the first and second embodiments. it can. The other operations are the same as those in the second embodiment, and a description thereof will be omitted.

As described above, according to the third embodiment,
In addition to the effects of the second embodiment, since the frequency of the input clock signal is divided, the phase difference adjustment range can be expanded, and a wider range of delay adjustment can be achieved.

Embodiment 4 FIG. Embodiment 4 of the present invention
In the first embodiment, the phase control signal is adjusted based on the pulse signal from the phase comparator 2. Hereinafter, first, the configuration of the fourth embodiment will be described with reference to FIG. FIG. 6 is a diagram showing a schematic configuration of a phase matching circuit according to the fourth embodiment of the present invention. Note that the basic configuration is the same as that of the first embodiment, and the same portions as those in FIG. 1 are denoted by the same reference numerals and description thereof is omitted.
Only different parts will be described.

The phase matching circuit 31 has the same configuration as that of the phase matching circuit 1 of the first embodiment.
, A phase control circuit 32 that receives a pulse signal from the phase comparator 2 and adjusts a phase control signal based on the input pulse signal. The phase control circuit 32 receives the pulse signal from the phase comparator 2, adjusts the phase control signal based on the input pulse signal, and outputs the adjusted signal. That is, it monitors and adjusts whether or not the phase difference between the input and output clock signals is correctly controlled.

In the above configuration, the operation of the fourth embodiment will be described. In the operation of the fourth embodiment, the PLL characteristics fluctuate due to some environmental change such as a temperature change.
When the phase difference between the input and output clock signals deviates from a predetermined value, the phase control circuit 32 detects the phase deviation based on the pulse signal from the phase comparator 2 and adjusts the value of the phase control signal to be output. . Specifically, for example, when the phase of the output clock signal is ahead of a predetermined value, the voltage of the phase control signal is lowered, and when the phase of the output clock signal is behind the predetermined value, Increase the signal voltage. Other operations are the same as those in the first embodiment, and a description thereof will be omitted.

As described above, according to the fourth embodiment,
In addition to the effects of the first embodiment, since the pulse signal from the phase comparator 2 is monitored and the phase control signal is adjusted in accordance with the pulse signal, even if the PLL characteristics fluctuate due to some environmental fluctuations, the This has the effect of automatically controlling the phase difference of the clock signal and always maintaining a predetermined phase difference.

Embodiment 5 Embodiment 5 of the present invention
In the first embodiment, the phase control signal is adjusted based on the VCO control signal from the arithmetic circuit 5. Hereinafter, first, regarding the configuration of the fifth embodiment,
This will be described with reference to FIG. FIG. 7 is a diagram showing a schematic configuration of a phase matching circuit according to the fifth embodiment of the present invention. Note that the basic configuration is the same as that of the first embodiment, and the same portions as those in FIG. 1 are denoted by the same reference numerals and description thereof is omitted.
Only different parts will be described.

The phase matching circuit 41 has the same configuration as the phase matching circuit 1 of the first embodiment,
Instead, the VCO control signal from the arithmetic circuit 5 is input,
A phase control circuit 42 is provided for adjusting the phase control signal based on the input VCO control signal. Phase control circuit 42
Inputs the VCO control signal from the arithmetic circuit 5, adjusts the phase control signal based on the input VCO control signal, and outputs the adjusted signal. That is, the frequency of the output clock signal is monitored, and appropriate phase control is performed according to the frequency.

In the above configuration, the operation of the fifth embodiment will be described. In the operation of the fifth embodiment, when the frequency of the input clock signal fluctuates and the value of the phase difference to be set changes, the phase control circuit 42 detects the fluctuation of this frequency by the VCO control signal from the arithmetic circuit 5. Detect
Adjust the value of the output phase control signal. Specifically, for example, when delaying the phase of the output clock signal, the voltage of the phase control signal is lowered, and when advancing the phase of the output clock signal, the voltage of the phase control signal is raised. Other operations are the same as those in the first embodiment, and a description thereof will be omitted.

As described above, according to the fifth embodiment,
In addition to the effects of the first embodiment, in order to monitor the frequency of the output clock signal and adjust the phase control signal according to the frequency, the input clock signal fluctuates, and the value of the phase difference of the input / output clock signal to be set Even if the value changes, the phase difference between the input and output clock signals is automatically controlled, and the phase difference can always be controlled appropriately. The signal monitored by the phase control circuit is not particularly limited, and a signal is extracted from another portion or a plurality of portions of the feedback loop including the phase comparator 2, the LPF 3, the arithmetic circuit 5, and the VCO 6, and based on the extracted signal. The phase control signal may be adjusted.

Embodiment 6 FIG. Embodiment 6 of the present invention
In the first embodiment, a surrounding environment that affects the phase difference between the input and output clock signals is detected, and the phase control signal is adjusted based on the detection result. Hereinafter, first, the configuration of the sixth embodiment will be described with reference to FIG. FIG. 8 is a diagram showing a schematic configuration of a phase matching circuit according to a sixth embodiment of the present invention. Note that the basic configuration is the same as that of the first embodiment, and the same portions as those in FIG. 1 are denoted by the same reference numerals and description thereof is omitted.
Only different parts will be described.

The phase matching circuit 51 has a temperature sensor 52 for detecting the ambient temperature and outputting a detection signal in addition to the configuration of the phase matching circuit 1 of the first embodiment. Further, instead of the phase control circuit 4, a phase control circuit 53 that receives a detection signal from the temperature sensor 52 and adjusts the phase control signal based on the input detection signal is provided. The temperature sensor 52 detects the temperature around the phase matching circuit 51,
A detection signal corresponding to the detection result is output. Phase control circuit 5
Reference numeral 3 inputs a detection signal from the temperature sensor 52, and adjusts and outputs a phase control signal based on the input detection signal. That is, the surrounding environment that affects the characteristics of the phase matching circuit 51 is monitored, and appropriate phase control is performed according to the surrounding environment.

Here, the temperature sensor 52 and the phase control circuit 5
3, an external environment detection unit that detects another external environment (surrounding environment) such as a control signal from another circuit, a power supply voltage, or a combination of external environments, and a detection result of the external environment detection unit. A phase control circuit that adjusts the phase control signal based on the
May be provided. In addition, the temperature sensor 52
This corresponds to the detecting means of the present invention.

The operation of the sixth embodiment in the above configuration will be described. In the operation of the sixth embodiment, when the PLL characteristics fluctuate due to a temperature change and the phase difference between the input and output clock signals deviates from a predetermined value, the phase control circuit 53
Detects a temperature change based on a detection signal from the temperature sensor 52 and adjusts a value of a phase control signal to be output. Other operations are the same as those in the first embodiment, and a description thereof will not be repeated.

As described above, according to the sixth embodiment,
In addition to the effects of the first embodiment, since the surrounding environment is monitored and the phase control signal is adjusted in accordance with the environmental fluctuation, even if the PLL characteristic fluctuates due to some environmental fluctuation, the phase difference between the input and output clock signals is reduced. This has the effect of automatically controlling and constantly maintaining a predetermined phase difference. In the fourth, fifth, and sixth embodiments, if a frequency divider is used as in the second and third embodiments, the second and third embodiments are used. The same effect as that of No. 3 can be obtained.

[0049]

As described above, according to the present invention, by adding an offset for controlling the phase of the output signal to the signal for controlling the frequency of the output signal, the output signal can be controlled without using a delay circuit. Since the phase can be controlled, there is an effect that the phase can be accurately controlled even when the input signal is a high-speed clock signal.

According to the next invention, the phase comparing means compares the phase of the input signal with the phase of the feedback signal,
A first comparison result signal corresponding to the comparison result is output, the phase control means outputs a phase control signal for controlling the phase of the output signal, and the calculation means outputs the first comparison result signal from the phase comparison means. A signal and a phase control signal from the phase control means are input and operated, and an operation result signal corresponding to the operation result is output. The oscillation means outputs an output signal based on the operation result signal from the operation means. As a result, the phase of the output signal can be controlled without using a delay circuit, so that the phase control can be accurately performed even when the input signal is a high-speed clock signal.

According to the next invention, the first frequency dividing means comprises:
Since the output signal is frequency-divided to generate a feedback signal to the phase comparison means, even when the output signal is multiplied, the phase of the output signal can be controlled without using a delay circuit, and the input signal can be controlled by a high-speed clock. Thus, there is an effect that the phase control can be performed accurately even when the signal is

According to the next invention, the second frequency dividing means includes:
Since an external signal is frequency-divided to generate an input signal to the phase comparing means, the phase control range can be expanded, and an effect that a wider range of phase control can be performed is achieved.

According to the next invention, the phase control means adjusts the phase control signal based on the first comparison result signal or the second comparison result signal from the phase comparison means,
Even if the characteristics (PLL characteristics) of the phase matching circuit fluctuate and the phase difference between the input and output signals fluctuates, the phase control signal can be adjusted so as to appropriately maintain the phase difference, so that the phase control is more accurately performed. Can be performed.

According to the next invention, since the phase comparing means adjusts the phase control signal based on the operation result signal from the operation means, even if the frequency of the input signal fluctuates, the phase difference is set to an appropriate value. Thus, there is an effect that the phase control signal can be adjusted as described above.

According to the next invention, the phase comparison means adjusts the phase control signal based on the signal in one or a plurality of portions of the feedback loop of the phase matching circuit.
Even if the frequency of the input signal and / or the phase difference between the input and output signals fluctuates, the phase control signal can be adjusted so that the phase difference has an appropriate value.

According to the next invention, the detecting means detects the ambient temperature, the fluctuation of the power supply voltage, the state of the surrounding environment such as a control signal from another circuit, and the phase comparing means detects the detection result of the detecting means. Adjust the phase control signal based on Thus, even if the phase difference between the input and output signals fluctuates due to a change in the state of the surrounding environment, the phase control signal can be adjusted so that the phase difference has an appropriate value. The effect is that it can be done.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a schematic configuration of a phase matching circuit according to a first embodiment of the present invention;

FIG. 2 is a timing chart illustrating an operation of the phase matching circuit when the phase control signal according to the first embodiment is not output;

FIG. 3 is a timing chart illustrating an operation of the phase matching circuit when the phase control signal according to the first embodiment is output.

FIG. 4 is a diagram illustrating a schematic configuration of a phase matching circuit according to a second embodiment of the present invention;

FIG. 5 is a diagram illustrating a schematic configuration of a phase matching circuit according to a third embodiment of the present invention;

FIG. 6 is a diagram illustrating a schematic configuration of a phase matching circuit according to a fourth embodiment of the present invention;

FIG. 7 is a diagram illustrating a schematic configuration of a phase matching circuit according to a fifth embodiment of the present invention;

FIG. 8 is a diagram illustrating a schematic configuration of a phase matching circuit according to a sixth embodiment of the present invention;

FIG. 9 is a diagram showing a schematic configuration of a conventional PLL circuit.

[Explanation of symbols]

1, 11, 21, 31, 41, 51 Phase matching circuit, 2
Phase comparator, 3 low-pass filter (LPF), 4,
32, 42, 53 Phase control circuit, 5 arithmetic circuit, 6
Voltage controlled oscillator (VCO), 12,22 divider, 52
Temperature sensor.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Kazuo Kubo, 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsui Electric Co., Ltd. (72) Hiroshi Ichigase 2-2-2 Marunouchi, Chiyoda-ku, Tokyo No. 3 Mitsubishi Electric Corporation F-term (reference) 5J106 AA04 CC01 CC21 CC38 CC41 CC52 DD44 GG00 HH02 KK05

Claims (8)

[Claims] 1. A phase matching circuit for controlling a phase of an output signal based on a feedback signal, wherein an offset is added to a signal for controlling a frequency of the output signal. 2. A phase matching circuit for controlling a phase of an output signal based on a feedback signal, wherein the phase comparison circuit compares the phases of an input signal and the feedback signal and outputs a first comparison result signal according to the comparison result. Means, a phase control means for outputting a phase control signal for controlling the phase of the output signal, and a first comparison result signal from the phase comparison means and a phase control signal from the phase control means. A phase matching circuit comprising: a calculating means for calculating and outputting a calculation result signal according to the calculation result; and an oscillating means for outputting the output signal based on the calculation result signal from the calculation means. . 3. The phase matching circuit according to claim 2, further comprising a first frequency divider for dividing the output signal to generate a feedback signal to the phase comparator. 4. The phase matching circuit according to claim 3, further comprising second frequency dividing means for dividing an external signal to generate an input signal to said phase comparing means. . 5. The phase comparator, comprising: comparing a phase of the input signal and a phase of the feedback signal; and outputting a second comparison result signal according to a comparison result; And a smoothing means for time-smoothing the comparison result signal of No. 2 and outputting the first comparison result signal. The phase control means comprises a first comparison result signal from the phase comparison means or a second comparison result signal. The phase matching circuit according to claim 2, wherein the phase control signal is adjusted based on a comparison result signal. 6. The phase matching circuit according to claim 2, wherein the phase comparison means adjusts the phase control signal based on a calculation result signal from the calculation means. 7. The phase comparison signal according to claim 2, wherein the phase comparison means adjusts the phase control signal based on a signal in one or more parts of a feedback loop of a phase matching circuit. Phase matching circuit. 8. The apparatus according to claim 2, further comprising detecting means for detecting a state of the surrounding environment, wherein said phase comparing means adjusts the phase control signal based on a detection result of the detecting means. 8. The phase matching circuit according to any one of claims 7 to 7.