JP2001244435A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide, as a semiconductor device having a simple structure and its manufacturing method having a simple process, a memory cell and a contact forming process of its peripheral-circuit region, whereby the upper electrode of an LSI memory and the deriving of the upper electrode to its peripheral-circuit region are formed by a comparably easy process. SOLUTION: In the semiconductor device and its manufacturing method, a memory cell has on a semiconductor substrate 1 a capacitor comprising a first electrode 14a made of a first conductive material; a dielectric film 18; and a second electrode 19 made of a second conductive material WNx, etc., and has a third electrode 14b made of the first conductive material. The second electrode 19 is extended from the capacitor to the third electrode 14b. The second and third electrodes 19, 14b are connected electrically by the second conductive material WNx, etc., filled into a second groove 22 provided on the third electrode 14b.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a storage element of an LSI memory and a method of manufacturing the same.

[0002]

2. Description of the Related Art In an LSI memory, a memory cell is composed of a transfer transistor (hereinafter, transistor) and an information storage capacitor (hereinafter, storage capacitor).

In recent years, international competition has intensified in this field,
It has become essential to supply large-capacity LSI memories to the market at low prices. Therefore, there is a need for a technology capable of manufacturing a highly integrated LSI memory at a lower price.

[0004] In order to realize higher integration, the structure of the memory cell is complicated, the step between the memory cell region and the peripheral circuit region is enlarged, and the difficulty of the processing step is increased. Above all,
The difficulty in the process of forming a contact between a memory cell and a peripheral circuit region has increased, which has been an obstacle in manufacturing LSI memories at lower prices.

Therefore, the present inventor has proposed in Japanese Patent Application Laid-Open No. Hei 10-189912 a conventional semiconductor device having excellent matching between the memory cell forming process and the contact forming process in the peripheral circuit region and a method of manufacturing the same. I have.

Hereinafter, a conventional semiconductor device and a method of manufacturing the same will be described with reference to the drawings.

FIG. 14 is a plan view and a sectional view showing the structure of a conventional semiconductor device. Further, in the figure, the left side is the memory cell area m, and the right side is the peripheral circuit area p. FIG.
4A is a plan view, and FIG. 14B is a cross-sectional view taken along the line xx ′ in FIG.

In the figure, 101 is a semiconductor substrate, 102 is an element isolation region, 103 is a gate insulating film, 104 is a gate electrode, 105 is a protective film, 106 is a gate side wall insulating film, 10
7 is a source / drain diffusion layer, 114a is a storage electrode made of the first conductor film, 114b is a dummy pattern made of the first conductor film, 114c is a contact plug in a peripheral circuit region made of the first conductor film, and 118 is a contact plug of the first conductor film. Capacitor dielectric film 119 is a counter electrode formed of a second conductive film, 12
7 is a wiring layer.

In FIG. 1, a dummy pattern 114b and a contact plug 114c in a peripheral circuit region are formed simultaneously with the storage electrode 114a of the first conductor of the storage capacitance of the memory cell. Therefore, the number of steps can be reduced, and the difficulty of the steps due to the step between the memory cell region and the peripheral circuit region can be reduced.

[0010]

However, even in the above-mentioned conventional technique, the formation of the wiring layer 127 requires
An opening process for extracting the electrodes is required. This opening step includes forming a resist mask by a photo process for forming the opening, etching an insulating film for forming the opening,
A process such as removal of a resist mask is required, which burdens the process, and it is difficult to supply it to the market at a low price.

Therefore, there is a demand for a technique which is excellent in matching when forming a memory cell region and a peripheral circuit region and which can manufacture an LSI memory at lower cost.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having a simple structure and process for forming a contact between a memory cell and a peripheral circuit region of an LSI memory and a method of manufacturing the same.

[0013]

An object of the present invention is to provide a semiconductor device, comprising: a first electrode made of a first conductor; a dielectric film;
A capacitor formed by a second electrode made of a second conductor, and a third electrode made of the first conductor, wherein the second electrode extends from the capacitor to the third electrode. This is achieved by a semiconductor device in which the second electrode and the third electrode are electrically connected on the third electrode.

In addition, the above object is to provide a method for manufacturing a semiconductor device having a memory cell region and a peripheral circuit region on a semiconductor substrate, wherein a first electrode made of a first conductor is formed in the memory cell region. Forming a third electrode made of the first conductor at a boundary between the memory cell region and the peripheral circuit region; and providing the third electrode with the memory cell region from the boundary. A step portion is formed in which a portion belonging to the peripheral circuit region is lower than a portion belonging to the peripheral circuit region, and a dielectric film and a second electrode made of a second conductor are formed on the first electrode; Forming a dielectric film and the second electrode on the side wall of the step portion of the third electrode; and forming the second electrode and the dielectric film on the side wall portion Forming a groove in which a part of the groove is removed;
And electrically connecting the second electrode and the third electrode with each other.

That is, according to the present invention, the extraction of the counter electrode is completed without going through the steps of forming a resist mask by a photo process, etching an insulating film, removing the resist mask, and the like, and is formed by a relatively easy process. Therefore, a semiconductor device and a method of manufacturing the same can be provided by a simpler configuration and process for forming a memory cell of an LSI memory and forming a contact in a peripheral circuit region.

[0016]

[First Embodiment] The semiconductor device and the method for fabricating the same according to a first embodiment of the present invention will be explained with reference to FIGS.

FIG. 1 is a plan view and a sectional view showing the structure of the semiconductor device according to the first embodiment of the present invention. The left side is a memory cell region M and the right side is a peripheral circuit region P. FIG.
FIG. 1A is a plan view, and FIG.
It is X 'sectional drawing. 2 to 4 are process sectional views showing the method for manufacturing the semiconductor device according to the present embodiment.

First, the structure of the semiconductor device according to the present embodiment will be explained with reference to FIG.

The semiconductor substrate 1 is defined by an element isolation region 2, and a transistor including a gate insulating film 3, a gate electrode 4, a protective film 5, a gate side wall insulating film 6, and a source / drain diffusion layer 7 is present at a predetermined position. ing. In the memory cell region M, the same conductor is used to store a storage electrode (hereinafter referred to as a storage electrode) 14a, which is a first electrode of a storage capacitor, at a position extending over a boundary between the memory cell region M and the peripheral circuit region P. A contact electrode (hereinafter, referred to as a contact electrode) 14b, which is a third electrode, and a contact plug 14c exist in the peripheral circuit region P.

The capacitor dielectric film 18 and a counter electrode (hereinafter referred to as a counter electrode) 19 as a second electrode constitute a storage capacitor of the memory cell region M, and a step portion of the contact electrode portion 14b extending over the boundary. Also extends to the side wall portion.

In the side wall, there is a first groove 21 formed by etching the capacitor dielectric film 18 and the counter electrode 19 from the surface. At the bottom of the first groove, the capacitor dielectric film 18 is etched deeper than the counter electrode 19 to form a second groove 22. The second groove 22 is filled by volume expansion when both or any of the side wall of the contact electrode 14b and the counter electrode 19 is oxidized or nitrided to generate an oxide or a nitride.

For the contact electrode 14b and the counter electrode 19, a material such as W (tungsten), which also has conductivity, is selected. In the case of W, the second trench 22 is filled with a conductive WNx (tungsten nitride) film 23 and both are electrically connected. The insulating film 26 is present in the first groove 21, and the contact electrode 14b and the contact plug 14c in the peripheral circuit region are exposed by flattening the surface.

These do not require a photo process and can be used for etch-back or CMP (Chemical Mesh).
An opening is formed by a mechanical polishing method and connected to the wiring layer 27.

In the plan view of FIG. 1A, an example of the arrangement of storage cells 14a in a memory cell region M is shown. The boundary between the memory cell region M and the peripheral circuit region P is indicated by the pattern of the insulating film 26. The intersection of the contact electrode 14b and the pattern of the insulating film 26 indicates the positional characteristics of the electrode 14b.

Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS.

Referring to FIG. 2A, for example, an STI (Shallow Trench Isosol) is formed on the semiconductor substrate 1.
After the formation of the element isolation region 2 according to (a), a transistor is formed by the gate insulating film 3, the gate electrode 4, the protective film 5, the gate sidewall insulating film 6, and the source / drain diffusion layer 7. Note that the gate electrode 4 also serves as a word line.
On the source / drain diffusion layer 7 in the memory cell region M,
A plug 7a of doped polysilicon is formed.

On one of the source / drain diffusion layers 7,
A bit line 8 intersecting with the word line is formed via a plug 7a, and an extraction electrode 8 is formed on the peripheral circuit region P.
Form c.

Next, an insulating film 9 is formed on the entire surface, and the
The surface of the insulating film 9 is planarized by the method. Thereafter, an opening connected to the plug 7a and the extraction electrode 8c of the peripheral circuit region P is formed in the insulating film 9, and the inside of the opening is formed, for example, of W / TiN /
It is filled with a conductor film 10 such as Ti.

Next, a silicon nitride film 11 having a thickness of, for example, 50 nm serving as an etching stopper is formed by CVD.
A silicon oxide film 12 having a thickness of 0.3 to 0.6 μm and an amorphous silicon film having a thickness of, for example, 50 nm serving as an etching mask are sequentially formed. Thereafter, the amorphous silicon film is patterned by a photo process, and the amorphous silicon film 13 is used as an etching mask.
Openings that will become storage electrodes, contact electrodes, and peripheral circuit contact plugs in the future are formed.

Referring to FIG. 2B, a CVD method is used.
A W film 14 having a thickness of, for example, 100 nm serving as a first conductor is formed. The W film 14 is formed so as to fill the opening formed by the silicon oxide film 12 and the amorphous silicon film 13, and its surface is relatively flat.

Referring to FIG. 2C, the W film 14 is etched back by dry etching of SF6 (sulfur hexafluoride) gas plasma until the amorphous silicon film 13 is exposed.

Next, by etching the amorphous silicon film 13, the W film 14 is formed as an isolated pattern of a portion to be a storage electrode and a contact electrode and a peripheral circuit region contact plug 14c. Instead of etching the W film 14 and the amorphous silicon film 13, it is also possible to use a CMP method.

Referring to FIG. 3A, a CVD method is used.
A silicon nitride film 16 having a thickness of, for example, 20 nm serving as an etching protection film is formed. Next, the peripheral circuit region is covered with a resist mask 17 formed by a photo process, the silicon nitride film 16 is etched, and the W film is etched by about 100 nm to 300 nm by dry etching of SF6 plasma to obtain a desired accumulation. Make the height necessary to obtain the capacity. Here, the storage electrode 14a and the contact electrode 14b are formed.

In the contact electrode 14b located at a position intersecting the boundary, only a portion existing on the memory cell region M side is etched, so that a step occurs. Due to this step,
A side wall is formed along a boundary crossing the contact electrode 14b.

Next, the silicon nitride film 16 and the storage electrode 1
Using the mask 4a and the contact electrode 14b as a mask, the silicon oxide film 12 in the memory cell region is etched down to the silicon nitride film 11 by dry etching with fluorine plasma and, if necessary, wet etching with an HF (hydrofluoric acid) solution.

Although the conductor film 10 exists below the contact electrode 14b, the conductor film 10 does not need to function as a conductor, and is not necessarily required. However, when the conductor film 10 does not exist under the contact electrode 14b, the base of the contact electrode 14b becomes an insulating film, and the adhesion strength with the base becomes lower than when the base is a conductor film. There is a possibility that the contact electrode 14b may be peeled off inside, and this peeling can be prevented.

Referring to FIG. 3B, a Ta 2 O 5 film 18 having a thickness of, for example, 10 nm to be a capacitor dielectric film and a film having a thickness of, for example,
A 200 nm W film 19 and a 500 nm thick silicon oxide film 20 are sequentially formed.

Next, the silicon oxide film 20 on the peripheral circuit region P is removed by, for example, the CMP method, and the W film 19 and the Ta 2 O 5 film 18 are removed by the etch back or the CMP method. Flatten. In addition,
In the case of etching back, the following FIG. 3 (C) and FIG.
The removal can be performed simultaneously with the removal of the W film 19 and the Ta2 O5 film 18 in the step (A).

In the contact electrode 14b below the boundary, the capacitor dielectric film 18 and the counter electrode 19 are formed so that the side wall of the step rises from the memory cell region M to the peripheral circuit region P.
Are formed and terminate at the surface.

At this stage, since the dielectric film 18 is interposed between the contact electrode 14b and the counter electrode 19,
Both are not electrically connected.

Referring to FIG. 3C, the counter electrode 1 formed on the side wall portion of the boundary and the side wall portion inside the contact electrode portion is formed.
9 is removed by dry etching, and the first groove 21 is removed.
Is in the process of being formed. The contact electrode 14b
Is made of W similarly to the counter electrode 19, but is not etched because it is covered with the silicon nitride film 16.

Referring to FIG. 4A, contact electrode 1
The first groove 21 is formed by etching the Ta2 O5 film 18 formed on the side wall 4b to the same depth as the counter electrode 19. The Ta2 O5 film 18 has a thickness of, for example, 10 nm, and is etched by isotropic etching using fluorine plasma dry etching under the same etching conditions as for the silicon oxide film. At this time, the silicon oxide film 20 is also etched, but the thickness to be etched is small compared to its thickness of 100 to 300 nm, and has no influence.

Further, the Ta 2 O 5 film 18 is etched to form a second groove 22 at a part of the bottom of the first groove 21. This groove is formed between the contact electrode 14 b and the counter electrode 19.
The width is equivalent to the thickness of the Ta2 O5 film 18, and is, for example, 10 nm. Ta2 O5 in this step
The etching of the film 18 is 10 to 20 nm, and does not affect the silicon oxide film 20 as described above.

Referring to FIG. 4B, for example, thermal nitriding is performed at 400 ° C. for 5 to 10 minutes in an NH 3 atmosphere. The contact electrode 14b and the counter electrode 18 are both W, and the nitride WNx has conductivity. In the second groove 22,
The WNx film 23 is formed and filled by volume expansion at that time. At the same time, the contact electrode 14b and the counter electrode 18 can be electrically connected. The second groove has a width of, for example, 10 nm.
Therefore, this step is completed by the thermal nitridation for the above time.

Next, a silicon oxide film 26 is formed on the entire surface by CVD, and the first groove 21 is filled. afterwards,
The silicon oxide film 26 and the silicon nitride film 16 other than filling the first groove 21 are removed by an etch-back method or a CMP method.

As a result, the process of forming the opening for taking out the wiring of the counter electrode and the opening for the peripheral circuit region includes forming a resist mask by a photo process for forming the opening, etching an insulating film for forming the opening, removing the resist, and the like. It is completed without going through the process of.

Referring to FIG. 4C, wiring layers 27 such as necessary lead lines for the counter electrode, main word lines, and peripheral circuits are formed.

In this embodiment, W is used as the material of the storage electrode 14a and the counter electrode 19, but other materials can be selected.

For example, Ru (ruthenium) is selected as the storage electrode 14a and the contact electrode 14b, and the second groove is filled by volume expansion due to oxidation, so that Ru oxide RuOx is used.
(Ruthenium oxide) can be electrically connected because it is a conductor. In this case, instead of the thermal nitridation step of FIG. 4B, thermal oxidation is performed at 450 ° C. in an O 2 atmosphere, for example, and the second groove 22 is filled by volume expansion due to oxidation. Further, dry etching of O2 plasma is used for the etching.

The material of the counter electrode 19 is R
Selection of u, WN, TiN, TiON, etc. is also possible.

Further, although Ta 2 O 5 was used as the dielectric film 18, another material such as BST (BaStTaO 3) was used.
) And ST (StTaO3).

[Second Embodiment] The semiconductor device and the method for fabricating the same according to a second embodiment of the present invention will be explained with reference to FIGS. In addition, the first shown in FIGS.
The same components as those of the semiconductor device according to the embodiment and the method of manufacturing the same are denoted by the same reference numerals, and description thereof will be omitted or simplified.

FIG. 5 is a plan view and a sectional view showing the structure of the semiconductor device according to the second embodiment of the present invention. The left side is a memory cell region M and the right side is a peripheral circuit region P. FIG.
FIG. 5A is a plan view, and FIG.
It is Y 'sectional drawing. 6 to 9 are process sectional views illustrating the method for manufacturing the semiconductor device according to the present embodiment.

First, the structure of the semiconductor device according to the present embodiment will be explained with reference to FIG. This embodiment is applied to a cylindrical capacitor structure in which a higher storage capacitance is obtained by utilizing both inner and outer side walls of the storage electrode as electrodes in order to reduce the area of the memory cell.

In the plan view of FIG. 5A, an example is shown in which the storage electrodes 34a in the memory cell region M are arranged in memory cells. The boundary between the memory cell region M and the peripheral circuit region P is indicated by the pattern of the silicon oxide film 26. Contact electrode 34
b and the pattern of the silicon oxide film 26
The positional characteristics of b are shown. The contact electrode 34b has a structure having inner and outer side walls similar to the storage electrode 34a in a plan view. At the intersection of the pattern of the contact electrode 34b and the silicon oxide film 26, the silicon oxide film 26 exists along the inner side wall of the contact electrode 34b.

Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS.

In FIG. 6A, the opening of the insulating film 12 to be a storage electrode, a contact electrode, and a contact plug of a peripheral circuit in the future is obtained by the same process as that of FIG. 2A for describing the first embodiment. Since a portion is formed, the description is omitted.

Referring to FIG. 6B, by the CVD method,
A Ru film 34 having a thickness of, for example, 30 nm serving as a first conductor is formed. Unlike the step shown in FIG. 2B of the first embodiment, the opening of the insulating film 12 is not filled with the Ru film 34 in the present embodiment.

Next, a 200-nm-thick silicon oxide film 15 serving as an inner protective film is formed by SOG (coating glass) coating, and the Ru film 34 is embedded. Next, the silicon oxide film 15 is etched to
While exposing the uppermost surface of the u film 34 to the surface, the Ru film 3
4 is formed to protect the bottom of the concave region.

Referring to FIG. 6C, silicon oxide film 1
The protrusion of the Ru film 34 and the amorphous silicon film 13 protruded by the depression 5 are etched back by dry etching of O2 gas and CF4 gas to form a portion to be a storage electrode and a contact electrode, and a peripheral circuit contact plug 34c. Each is formed as an isolated pattern.

Referring to FIG. 7A, a CVD method is used.
For example, a silicon nitride film 16 having a thickness of 50 nm is formed as an etching protection film. Next, the peripheral circuit region P is protected by a resist mask 17 formed by a photo process, and the Ru film 34 is etched by about 100 nm to 300 nm by O2 gas plasma dry etching to a height determined by a desired storage capacity. Here, the storage electrode 34a and the contact electrode 34b are formed.

At the contact electrode 34b at the position intersecting the boundary, only the portion existing on the memory cell region side is etched, so that a step occurs.

Referring to FIG. 7B, silicon oxide film 1
2 and 15 are removed by dry etching of fluorine plasma and wet etching of HF solution. In this step, the silicon oxide film 15 below the resist mask 17 is removed until the side wall inside the contact electrode 34b is exposed. The insulating film 9 is protected by the silicon nitride film 11. Therefore, after the completion of the etching, the resist mask 17 and the silicon nitride film 16 have an eaves shape.

Next, the resist mask 17 is peeled off.

Note that the conductive film 10 is formed of the contact electrode 34c.
The reason for the existence is the same as that described with reference to FIG. 3A in the first embodiment.

Referring to FIG. 7C, the CVD method is used.
A Ta2 O5 film 18 having a thickness of, for example, 10 nm serving as a capacitor dielectric film, and a 50 nm film having a thickness of, e.g.
An Ru film 19 having a thickness of m, for example, a silicon oxide film 20 having a thickness of 500 nm is sequentially formed.

Next, the silicon oxide film 20 on the peripheral circuit region is removed by, for example, the CMP method, and thereafter, the Ru film 19 and the Ta film on the same region are removed by the etch-back or the CMP method.
The 2O5 film 18 is removed and the surface is planarized to the surface of the silicon nitride film 16. In the case of etch back,
Ru film 19 and Ta2 O in steps (A) and (B)
5 It can be performed simultaneously with the removal of the film 18.

In the contact electrode 34b below the boundary, the Ta2 O5 film 18 and the R of the counter electrode are formed on the side wall inside the electrode so as to crawl from the memory cell region M to the peripheral circuit region P.
A u film 19 is formed. On the surface, it is formed along the eaves shape of the silicon nitride film 16 and terminates. At this stage, T is applied between the contact electrode 34a and the Ru film 19 of the counter electrode.
Since the a2 O5 film 18 is interposed, the two are not electrically connected.

Referring to FIG. 8A, opposing electrode 19 formed on the side wall on the inner surface of the contact electrode portion is removed by dry etching of O2 gas plasma, so that first groove 21 is being formed. State. The contact electrode 34b is protected by the silicon nitride film 16.

Referring to FIG. 8B, contact electrode 3
The first groove 21 is formed by etching the Ta2 O5 film 18 formed on the side wall on the inner surface of 4b to the same depth as the counter electrode 19. The Ta2 O5 film 18 has a thickness of, for example, 10
The etching condition is the same as the etching condition for the silicon oxide film by dry etching with fluorine plasma. At this time, the silicon oxide film 20 is also etched, but the thickness to be etched is small compared to its thickness of 100 to 300 nm, and has no influence.

Further, the Ta 2 O 5 film 18 is etched to form a second groove 22 at a part of the bottom of the first groove 21. This groove is formed between the contact electrode 34 b and the counter electrode 19.
The width is equivalent to the thickness of the Ta2 O5 film 18 and is 10 nm. The etching of the Ta2 O5 film in this step is 10 to 20 nm, and does not affect the silicon oxide film 20 as described above.

Referring to FIG. 8C, thermal oxidation is performed at 450 ° C. for several minutes in an oxygen atmosphere, for example. Contact electrode 3
4b and the counter electrode 19 are both Ru, and the oxide thereof has conductivity. In the second groove 22, the RuOx film 2
4 are formed and filled by volume expansion at that time. At the same time, the contact electrode 34b and the counter electrode 19 can be electrically connected. Since the width of the second groove is, for example, 10 nm, this step is completed by the thermal nitridation for the above-mentioned time.

Referring to FIG. 9A, a silicon oxide film 26 is formed on the entire surface to fill first groove 21. Next, the silicon oxide film 26 except for filling the first groove 21 and the silicon nitride film 16 are removed by an etch method or a CMP method.

As a result, the opening step of taking out the wiring of the peripheral circuit and the counter electrode involves the steps of forming a resist mask by a photo process for forming the opening, etching the insulating film for forming the opening, removing the resist, and the like. Complete without.

Referring to FIG. 9 (B), necessary lead lines for the counter electrode, main word lines, wiring layers 27 for peripheral circuits and the like are formed.

In this embodiment, Ru is used as an example of the material of the storage electrode 34a and the counter electrode 19, but other materials can be selected. For example, as in the first embodiment, W can be selected as the storage electrode, and the second groove can be filled by volume expansion due to nitridation to be electrically connected. In this case, the steps of thermal nitridation and etching are the same as in the first embodiment.

The selection of the material of the dielectric film 18 is the same as in the first embodiment.

As the material of the counter electrode, W, WN, TiN, TiON, etc. can be selected in addition to Ru.

Referring to FIG. 10, a part of the present embodiment will be further described.

FIGS. 10A and 10B are cross-sectional views focusing on the yy 'cross section in FIG. 5A.
FIG. 7A shows a cross section focusing only on a portion where the pattern of the resist mask 17 and the contact electrode 34b intersect in the step of FIG. The structure of the same part is shown in FIG.
Is the same as the structure of the contact electrode 14b in the first embodiment shown in FIG.

That is, on the side wall of the step portion of the contact electrode 34b on the end face of the resist mask 17,
The electrical connection between the contact electrode 34b and the counter electrode 19 is performed.

FIG. 10B shows a connection portion of the cross section of the contact electrode 34b in the step of forming the wiring layer 27 shown in FIG. 9B.

Therefore, the electrical connection between the contact electrode 34b and the counter electrode 19 is established only by the connection portion. In this case, in the step of FIG. 7B, when etching the silicon oxide film 15, only the inner surface of the storage electrode 34a that is not covered with the resist mask 17 may be removed. It is not necessary to expose the inner wall of the contact electrode 34b.

In the step of FIG. 6B, a conductor can be selected instead of the silicon oxide film 15 serving as the inner surface protection film. For example, a film thickness of 2
A film of W of 00 nm can be formed. In this case, FIG.
0 (C) and (D).

In FIG. 10C, not the etching of the silicon oxide film 15 in the step of FIG.
Plasma etching of W using a gas is performed. W15a inside the contact electrode 34b is
The portion covered with the rim remains to form a step in the same electrode. On the side wall of the same step, the contact electrode 34b and the counter electrode 19
Are electrically connected.

FIG. 10D shows a step of forming the wiring layer 27. When the inner surface protection film is made of the conductor 15a as in the case of W, the inner surface of the contact plug 34c in the peripheral circuit region is filled with the conductor, so that a lower-resistance contact characteristic can be realized.

As described above, in the present embodiment, the contact electrode 34
As a portion where b and the counter electrode 19 are electrically connected,
Inner side wall of contact electrode 34b, contact electrode 3
When the inner surface protection film 15 of the contact electrode 34b is a conductor, there is a side wall of the step of the inner surface protection film in the same electrode. These electrical connections, either alone,
Alternatively, a plurality of combinations can be used.

[A Third Embodiment] The semiconductor device and the method for fabricating the same according to a third embodiment of the present invention will be explained with reference to FIG.

The present embodiment is an example of the same memory cell shape as that of the second embodiment, and FIG. 11 is a view showing a process unique to this embodiment. The steps of the present embodiment go through the same steps as in FIG. 6 described in the second embodiment, but the silicon nitride film 16 is omitted as compared with the step shown in FIG. 7A of the second embodiment. .

FIG. 11A shows a step of omitting the silicon nitride film and protecting the peripheral region only with the resist mask 17.

Referring to FIG. 11B, a process of forming a Ta2 O5 film 18, a counter electrode 19 and a silicon oxide film 20 and flattening the same as in the second embodiment will be described. The eave shape seen in FIG. 7A of the second embodiment is not seen in the present embodiment.

In the present embodiment, after the step shown in FIG. 11B, the counter electrode 19 is etched to form a groove (not shown) as in the second embodiment, but the storage electrode 34a and the counter electrode 19 are formed. The silicon nitride film serving as the etching protection film can be omitted by a combination of material selection such as the above.

For example, by selecting W as the storage electrode 34a and TiN as the counter electrode 19, only the counter electrode 19 is etched by wet etching of hydrogen peroxide + sulfuric acid, and the Ta2 O5 film 18 is further etched to form a groove. 21 are formed.

In the present embodiment, in the step of filling the groove with the conductor, conditions suitable for the selected material are determined. In the case of the above-described material example, a thermal nitriding treatment is performed.

[Fourth Embodiment] The semiconductor device and the method for fabricating the same according to a fourth embodiment of the present invention will be explained with reference to FIGS.

This embodiment is an example of the same memory cell shape as that of the second embodiment, and FIG. 12 is a view showing a process unique to this embodiment. In the steps of the present embodiment, the first groove 21 and the second groove 22 are formed through the same steps as the steps shown in FIGS. 6 to 8B in the second embodiment. The subsequent steps unique to this embodiment are shown in FIG.

Referring to FIG. 12A, a 10-nm-thick TiN film 25 is formed on the entire surface by CVD. Since the TiN film 25 is formed by the CVD method, the step coverage is good, and the TiN film 25 is formed on the inner side walls of the first groove 21 and the second groove 22. The conductor film 25 is the second
Is formed so as to fill the groove 22 of FIG.

Referring to FIG. 12B, the TiN film 25 is removed by dry etching using plasma of a chlorine-based gas while leaving the inside of the second groove 22, and the contact electrode 34b is formed.
And the counter electrode 19 are electrically connected.

Referring to FIG. 12C, a silicon oxide film 26 filling the first groove 21 is formed. Next, by performing planarization for removing the silicon oxide film 26, an opening step of taking out wiring of the peripheral circuit region and the counter electrode is completed.

Referring to FIG. 13, in the present embodiment, FIG.
The step of not forming the second groove 22 shown in FIG. 2 can be selected.
The figure shows a process unique to this process. That is, the first
After forming the groove 21, the TiN film 25 is grown, and the first groove 2 is formed.
Excess portions are etched while leaving the TiN film 25 filled at the bottom of the substrate 1. Contact electrode 34b and counter electrode 19
Are electrically connected by the TiN film 25. Then
A silicon oxide film 26 filling the upper portion of the first groove 21 is formed.

According to the present embodiment, regarding the selection of the material of the storage electrode 34a and the counter electrode 19, when making mutual electrical connection, the degree of freedom to select a material that cannot utilize the volume expansion effect due to oxidation of the conductor film or the like. Can be increased.

This embodiment can be applied to the steps in the third embodiment. That is, FIG.
After going through the same step as (B), the step of this embodiment can be passed. In addition, the electrode structure of the present embodiment has the second structure.
Although the cylindrical type is the same as that of the embodiment, the present invention can be applied to a cylindrical type.

According to the above-described first to fourth embodiments, the openings for taking out the wiring of the peripheral circuit and the counter electrode are formed by forming a resist mask by a photo process for forming the openings, and by the insulating process for forming the openings. It can be completed without going through steps such as film etching and resist removal.

[0104]

As described above, according to the present invention,
Since the extraction of the counter electrode and the peripheral circuit region is performed by a relatively easy process, the process of forming the contact between the memory cell and the peripheral circuit region of the LSI memory is provided as a semiconductor device with a simple configuration and process and a method of manufacturing the same. As a result, it is possible to contribute to a reduction in the manufacturing cost of the LSI memory.

[Brief description of the drawings]

FIGS. 1A and 1B are a plan view and a sectional view, respectively, showing the structure of a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a process sectional view (part 1) illustrating the method for fabricating the semiconductor device according to the first embodiment of the present invention;

FIG. 3 is a sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 4 is a process sectional view (part 3) illustrating the method for fabricating the semiconductor device according to the first embodiment of the present invention;

FIGS. 5A and 5B are a plan view and a cross-sectional view illustrating a structure of a semiconductor device according to a second embodiment;

FIG. 6 is a process sectional view (part 1) illustrating the method for fabricating the semiconductor device according to the second embodiment of the present invention.

FIG. 7 is a process sectional view (part 2) illustrating the method for fabricating the semiconductor device according to the second embodiment of the present invention.

FIG. 8 is a process sectional view (part 3) illustrating the method for fabricating the semiconductor device according to the second embodiment of the present invention.

FIG. 9 is a process sectional view (part 4) illustrating the method for fabricating the semiconductor device according to the second embodiment of the present invention.

FIG. 10 is a process sectional view (part 5) illustrating the method for fabricating the semiconductor device according to the second embodiment of the present invention.

FIG. 11 is a sectional view showing the structure of a semiconductor device according to a third embodiment of the present invention;

FIG. 12 is a sectional view (part 1) illustrating a structure of a semiconductor device according to a fourth embodiment of the present invention;

FIG. 13 is a sectional view (part 2) illustrating a structure of a semiconductor device according to a fourth embodiment;

14A and 14B are a plan view and a cross-sectional view illustrating a structure of a conventional semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Element isolation region 3 Gate insulating film 4 Gate electrode 5 Gate protective film 6 Gate side wall insulating film 7 Source / drain diffusion layer 7a Plug made of doped polysilicon 8 Bit line 8c Leader electrode of peripheral circuit 9 Insulating film 10 Conductive Body film 11 Silicon nitride film 12 Silicon oxide film 13 Amorphous silicon film 14, 34 First conductor 14a, 34a Storage electrode 14b, 34b Contact electrode 14c, 34c Contact plug in peripheral circuit region 15 Insulating film serving as inner surface protection film 15a Conductor serving as inner surface protection film 16 Silicon nitride film 17 Resist mask 18 Capacitor dielectric film 19 Counter electrode 20 Silicon oxide film 21 First groove 22 Second groove 23 WNx film 24 RuOx film 25 TiN film 26 Silicon oxide film 27 Wiring layer

Claims (5)

[Claims] 1. A first electrode made of a first conductor, a dielectric film, and a second electrode made of a second conductor on a semiconductor substrate.
And a third electrode made of the first conductor, the second electrode extending from the capacitor to the third electrode, and a third electrode formed on the third electrode. 3. The semiconductor device according to claim 1, wherein the second electrode and the third electrode are electrically connected. 2. A semiconductor device having a memory cell region and a peripheral circuit region on a semiconductor substrate, comprising: a first electrode made of a first conductor on the memory cell region; Formed at the boundary between the memory cell region and the peripheral circuit region; and a capacitor formed of a dielectric film formed on the substrate and a second electrode formed of a second conductor formed on the dielectric film. A third electrode made of the first conductor; and a fourth electrode made of the first conductor formed in the peripheral circuit region, wherein the third electrode is connected to the capacitor side. The second electrode extends from the capacitor to the side wall of the step of the third electrode;
A third conductor formed on the side wall of the step and electrically connecting the second electrode and the third electrode; and a third conductor formed on the third electrode and the fourth electrode. And a plurality of wiring layers. 3. A method of manufacturing a semiconductor device having a memory cell region and a peripheral circuit region on a semiconductor substrate, comprising: forming a first electrode made of a first conductor in the memory cell region; Forming a third electrode made of a first conductor at a boundary between the memory cell region and the peripheral circuit region; and forming a portion belonging to the memory cell region from the boundary on the third electrode. A step portion lower than a portion belonging to the peripheral circuit region is formed, and a dielectric film and a second electrode made of a second conductor are formed on the first electrode. Forming the second electrode on the side wall of the step portion of the third electrode, forming the second electrode and a part of the dielectric film on the side wall portion; Forming a removed groove, filling a part of the groove with a third conductor, and forming the second electrode The method of manufacturing a semiconductor device which comprises the step of electrically connecting the third electrodes. 4. The method according to claim 1, further comprising, when forming the first electrode and the third electrode, forming a fourth electrode made of the first conductor in the peripheral circuit region. The method for manufacturing a semiconductor device according to claim 3. 5. The step of filling a part of the groove with a third conductor, wherein the first electrode or the second electrode is oxidized or nitrided, and is made of a conductive oxide or nitride. The method of manufacturing a semiconductor device according to claim 3, further comprising a step of filling a part of the groove with the second conductor.