JP2001244277A - Lateral junction field-effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a lateral JFET which is manufactured easily as a high power semiconductor switching element excellent in high breakdown strength and high speed. SOLUTION: The lateral junction field-effect transistor is provided with an SiC substrate 1. The transistor is provided with a p-type SiC film 2. The transistor is provided with an n-type SiC film 3 which is formed on the p-type SiC film. The transistor is provided with a channel region 21 whose film thickness is formed thin in the n-type SiC film. The transistor is provided with a source region 22 and a drain region 23 which are separated in the upper part on both sides of the channel region. The transistor is provided with a gate electrode 14 which is formed in a p-type region. The channel region contains n-type impurities whose concentration is higher than the concentration of impurities in parts of the n-type SiC film on both sides of it.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lateral junction field effect transistor, and more particularly to a lateral junction field effect transistor using SiC as a semiconductor.

[0002]

2. Description of the Related Art A junction type field effect transistor (JFET: Jun)
ction Field Effect Transistor) is to apply a reverse bias voltage from a gate electrode to a pn junction provided on the side of a channel region through which carriers pass, thereby expanding a depletion layer from the pn junction to the channel region, And conducts operations such as switching. Among them, the “lateral” junction field effect transistor refers to a transistor in which carriers move parallel to the element surface in a channel region. Channel carriers are electrons (n
Type) or hole (p-type), but SiC, which is the object of the present invention, has a higher electron mobility than holes.
Usually, the channel region is an n-type impurity region. Therefore,
In the following description, for the sake of convenience, the carrier of the channel will be electrons, and the channel region will be described as an n-type impurity region. However, it goes without saying that the channel region may be a p-type impurity region.

In recent years, JF using silicon carbide (SiC)
ET is attracting attention. SiC has carrier mobility of S
Since it is as large as i, the saturation drift velocity of electrons is as large as GaAs, and the withstand voltage is large, studies on high-speed switching elements and high power elements are being studied. S
The crystal structure of iC includes a hexagonal close-packed structure and a cubic close-packed structure. In the hexagonal close-packed structure, there are many structures having different repetition periods of the layers. Type) is known. Representative polytypes include 3C, 4H, 6H, and the like. C is cubic,
H means hexagonal, and the number before it indicates the repetition period. The cubic form is only 3C, which is
C and others are collectively read as α-SiC. In the following description, only 6H or 4H of α-SiC is used.

FIG. 9 is a sectional view showing the structure of a JFET using SiC (PA Ivanov et al: 4H-SiC field-effect t).
ransistor hetero-epitaxially grown on 6H-SiC subst
rateby sublimation, p757 Silicon Carbide and Relat
ed Materials 1995 Conf., Kyoto Japan). In FIG. 9, a buffer layer 109 is formed by heteroepitaxially growing a 4H-SiC film 109 containing Sn on a 6H-SiC substrate 101 by a vacuum evaporation method. Buffer layer 10
9, an SiC film 1 containing Al which is a p + -type impurity
The n-type SiC film 103 having a source region 117 and a drain region 118 is formed on both sides thereof. The source electrode 112 and the drain electrode 113 are provided above the left and right of the channel region, and the gate electrode 114 is formed below the source and drain electrodes with a groove 115 therebetween. As the electrodes 114, a Ni film of the base film 120 and an Al film of the upper film 121 are formed. By using this lateral JFET, a JFET having a high electron drift mobility and an extremely high electron mobility can be formed.

[0005]

However, this J
The FET has the following problems. (A) It is insufficient in that it has both high breakdown voltage and low on-resistance.

The breakdown voltage of a JFET is determined by the breakdown voltage of a pn junction formed by an n-type impurity region of a channel and a p-type impurity region in contact with the region. Therefore, JFET
In order to improve the breakdown voltage performance, the breakdown voltage of the pn junction may be improved. In order to improve the breakdown voltage of the pn junction, the concentration of the n-type impurity, which is a channel impurity, may be reduced. As a result, the channel current decreases, and the on-resistance (the resistance in a state where carriers flow through the channel region) increases. ) Increases. As a result, power is consumed and the element temperature rises. Since the lateral JFET has a negative temperature coefficient in the range where the drain current is large, negative feedback is applied to the temperature rise, but no negative feedback is applied in the range where the drain current is small. Further, regardless of the magnitude of the drain current, power consumption in the element is not preferable. Another reason why the on-resistance of the JFET cannot be reduced is the contact resistance at the electrodes. In the configuration shown in FIG. 9, when each electrode is formed of Ni, the impurity concentration is too low, so that the Schottky contact is likely to remain, and the ohmic contact cannot be obtained. (B) The switching speed is insufficient.

[0007] The switching speed is determined by the charge / discharge time of the depletion layer of the pn junction. Assuming that the depletion layer capacitance is C and the gate resistance is Rg, the charge / discharge time is determined by CRg. Therefore, if the gate resistance Rg can be reduced, the switching time can be shortened, but the conventional J shown in FIG.
In the FET, a groove is formed in the second conductivity type region, and the gate resistance cannot be sufficiently reduced. Note that the gate resistance Rg can be changed from the gate electrode 114 to the channel 111 if importance is placed on grasping intuitively while sacrificing some accuracy.
The resistance of the path leading to the pn junction interface at the center of the pn junction. (C) The manufacturing process is complicated and requires high precision and strict control.

When the JFET shown in FIG. 9 is manufactured, it is manufactured by the following method. The buffer layer 109 is formed on the SiC substrate 101, and then the p + type SiC film 10
2 is formed. Next, as shown in FIG.
A film is formed, and a portion where a channel, a source, and a drain region are to be formed is patterned by using RIE (Reactive Ion Etching). Next, as shown in FIG. 11, a Ni film is formed as the lower layer 120 of the electrode. An upper layer 121 of an electrode is formed on the Ni film as shown in FIG.
1 film is formed. At this time, the Al film cannot be positioned just above the Ni film to form a film, which often causes misalignment. If Al adheres to the side wall or the like, it acts as a floating electrode and makes the device operation unstable. Next, as shown in FIG. 13, a channel region 111 is formed by RIE using the source electrode 112 and the drain electrode 113 as a mask and etching the space therebetween. At this time, the surface of the p + film 102 is also etched, and a groove 115 is formed together with the channel region. At the time of this etching, Al and the like adhered due to the above positional shift are also removed. The reason why the electrode is a two-layer film of a Ni film and an Al film is to form an ohmic contact. Due to the above groove, the resistance Rg of the path from the gate electrode to the pn junction interface at the center of the channel region increases, and when used for a switching element, the rise (fall) occurs.
The time gets longer. In addition, extra man-hours are required to form the groove,
This is a cost increase factor. (D) The operation becomes unstable due to the surface charge, and the surface leakage current is large.

A malfunction occurs due to the surface charge and the surface leakage current, and the yield is reduced. (E) The JFET is normally normally-on type (on state when no voltage is applied to the gate), and the gate circuit configuration becomes complicated when used for controlling a rotating machine or the like. That is, since the gate is turned on when no voltage is applied to the gate, if the gate circuit breaks down, the rotating machine keeps rotating, which is dangerous. Therefore, it is necessary to provide a mechanism for turning off the gate circuit in the event of a failure in preparation for a failure. Further, since it is necessary to continuously apply the voltage in the off state, power consumption occurs during the off period.

Accordingly, a first object of the present invention is to provide a lateral junction field effect transistor which is easy to manufacture as a high-power semiconductor switching element excellent in high withstand voltage and high speed. It is a second object of the present invention to provide a normally-off lateral junction field-effect transistor while ensuring the above excellent characteristics.

[0011]

According to a first aspect of the present invention, there is provided a lateral JFET comprising a semiconductor substrate and a second substrate formed on the substrate.
The semiconductor device includes a conductive semiconductor film, a first conductive semiconductor film formed on the second conductive semiconductor film, and a channel region formed with a reduced thickness in the first conductive semiconductor film. A source region and a drain region separately formed on both sides of the channel region, the source region and the drain region being a film made of the first conductivity type semiconductor formed on the first conductivity type semiconductor film; And a gate electrode formed in the region. Further, the channel region contains a first conductivity type impurity at a higher concentration than the impurity concentration of the first conductivity type semiconductor film on both sides thereof.

With this configuration, a depletion layer is formed so as to close the cross section of the channel from both sides of the channel region and turned off, and the voltage is shared by the depletion layer, so that the breakdown voltage of the lateral JFET is reduced. And the on-resistance can be reduced. For this reason, the present lateral JFET does not consume power even when a large current flows, and can be used as a switching element with low loss and high withstand voltage. The first conductivity type may be n-type or p-type, and the second conductivity type may be p-type or n-type. The semiconductor substrate may be an n-type Si substrate, a p-type Si substrate, or an n-type SiC.
Needless to say, the substrate may be a p-type SiC substrate.

In the lateral JFET of the second aspect, in the lateral JFET of the first aspect, the second conductivity type semiconductor film has a surface without a groove, and the gate electrode is a second conductivity type semiconductor region. It consists of two gate electrodes formed on the flat surface of the conductive semiconductor film.

With this configuration, since no groove or the like is provided between the source / drain and the gate, the gate resistance can be reduced, and as a result, the switching response speed can be increased. In addition, in the manufacturing process, there is no problem with slight displacement of the formation of the gate electrode, so that a decrease in yield can be prevented.

In the lateral JFET according to a third aspect, in the lateral JFET according to the first aspect, the semiconductor substrate is a second conductivity type semiconductor substrate containing a second conductivity type impurity, and the gate electrode is a region of the second conductivity type semiconductor. It comprises a back gate structure provided over the back surface of the certain second conductivity type semiconductor substrate.

With this configuration, the gate electrode is provided on the entire surface on the back side of the second conductivity type semiconductor substrate, so that the gate resistance is reduced. As a result, the response speed of the switching is improved, and the switching element can be used as a high-speed switching element. Further, formation of the gate electrode is also facilitated.

In the lateral JFET according to claim 4, claims 1 to
In any one of the lateral JFETs of No. 3, the source region and the drain region are regions containing a first conductivity type impurity whose concentration is higher than that of the first conductivity type semiconductor film on both sides of the channel region.

According to this configuration, the on-resistance can be reduced without lowering the breakdown voltage. The electrodes are Ni and A
Ohmic contact can be formed without using a two-layer structure using 1 or the like. As a result, in the manufacturing process, no groove is formed as a result, the gate resistance can be suppressed low, and the rise (fall) time of switching can be reduced.

In the lateral JFET according to the fifth aspect,
In any one of the lateral JFETs of No. 4, the impurity concentration of the second conductivity type semiconductor film is higher than 10 ¹⁹ cm ⁻³ .

According to this configuration, ohmic contact is established at the gate electrode, and the gate resistance is reduced. For this reason, the rise time and the fall time at the time of switching can be shortened, and a high-speed response can be achieved.

In the lateral JFET according to the sixth aspect,
5, the source electrode formed on the source region, the drain electrode formed on the drain region, and the gate electrode formed in the region of the second conductivity type semiconductor have the respective electrodes. It is made of a metal that makes ohmic contact with a semiconductor containing impurities that come into contact with the semiconductor.

According to this configuration, the electrodes can be formed by simple steps, and the electrode plate does not need to have a two-layer structure or the like. As a result, a groove or the like for increasing the gate resistance is not formed as a result, and the rise (fall) time of switching can be shortened. Examples of the metal that makes ohmic contact with the second conductivity type and the first conductivity type SiC films containing impurities at a high concentration include Ni.

In the lateral JFET according to the seventh aspect,
6, the surface excluding the source electrode, the drain electrode and the gate electrode is covered with an insulating film.

When the element surface is exposed, operation instability is caused by surface leakage current and surface charge formation. By the coating with the insulating film, such troubles can be prevented and the switching operation can be performed stably.

In the lateral JFET of the present invention, the semiconductor substrate is a SiC substrate, the first conductive type semiconductor film is a first conductive type SiC film, and the second conductive type semiconductor film is a second conductive type SiC film.
C film.

By using SiC as a semiconductor,
It has high withstand voltage, and can ensure high carrier mobility and high saturation drift velocity. Therefore, it can be used for a high-speed switching element or a high-power element.

According to a ninth aspect of the present invention, in the lateral JFET of the eighth aspect, the SiC substrate is a 6H-SiC substrate, and both the second conductivity type SiC film and the first conductivity type SiC film are 6H-SiC. is there.

According to the above configuration, thin films having good crystallinity are stacked, and there is no case where the yield is reduced due to malfunction or the like due to poor crystallinity.

According to the tenth aspect of the invention, there is provided a lateral JFET.
In both lateral JFETs, the second conductivity type SiC film and the first conductivity type SiC film are both 4H-SiC,
The second conductivity type SiC film made of H-SiC is formed on a 6H-SiC substrate via a 4H-SiC buffer layer.

4H-S with good crystallinity due to buffer layer
Since an iC film can be obtained, and 4H-SiC has a higher electron mobility than that of 6H-SiC or the like,
It can be suitable for a high-speed switching element or the like.

In the lateral JFET according to claim 11, claim 8
In the lateral JFET, the SiC substrate is a 4H-SiC substrate, and the second conductive type SiC film and the first conductive type SiC
Each film is 4H-SiC.

According to the above configuration, thin films having good crystallinity are stacked, and there is no case where the yield is reduced due to malfunction or the like due to poor crystallinity. As mentioned above, 4H
Since -SiC has a higher electron mobility than 6H-SiC or the like, -SiC can be suitable for a high-speed switching element or the like.

In the lateral JFET of claim 12, claim 8
In both lateral JFETs, the second conductivity type SiC film and the first conductivity type SiC film are both 6H-SiC,
The second conductivity type SiC film made of H-SiC is formed on a 4H-SiC substrate via a 6H-SiC buffer layer.

6H-S with good crystallinity due to buffer layer
An iC film can be obtained, and an optimal SiC crystal can be used depending on the application.

In the lateral JFET according to the thirteenth aspect, the first aspect has the following features.
In any one of the horizontal JFETs Nos. 1 to 12, the thickness of the channel region is equal to the thickness of the second conductive type semiconductor film and the channel region side of the first conductive type semiconductor film formed on the second conductive type semiconductor film. The width is smaller than the depletion layer width in the first conductivity type semiconductor film due to the diffusion potential at the junction.

With this configuration, a state in which the depletion layer extending to the side of the first conductivity type SiC film on the side of the channel region closes the channel region when the gate voltage is zero is realized.
The depletion layer may cover one side of the channel region, or may block both sides of the channel region. For this reason, a normally-off JFET can be obtained, and it can be used for controlling a rotating device or the like without forming a complicated mechanism for taking measures against a gate circuit failure. To turn it on,
What is necessary is just to apply a positive potential that overcomes this diffusion potential. Normally, the diffusion potential generated in the thermal equilibrium state is 2 V to 3 V, so that the depletion layer is removed by applying a positive potential of 2 V to 3 V to the gate electrode, and the channel region becomes conductive. Further, since the off applied potential is 0 V, a significant reduction in off-time power consumption can be obtained as compared with an applied potential of about 22 V required for turning off a normally-on JFET. As a result, it is possible to provide a low power consumption JFET that can easily be mounted on a rotating device or the like while ensuring a high-speed switching function with low loss and high withstand voltage.

In the lateral JFET according to the thirteenth aspect, for example, the impurity concentration at the side of the channel region is 5 × 10 ¹⁶ cm.
⁻³ or less, and the thickness of the channel region is 550 nm or less.

When the impurity concentration in the side region of the channel region is set to 5 × 10 ¹⁶ cm ⁻³ or less and the impurity concentration in the second conductivity type SiC film is set to a higher normal concentration, The depletion layer width exceeds 550 nm. For this reason,
In a state where the gate voltage is zero, a state where the depletion layer extending to the side of the channel region on the side of the first conductivity type SiC film blocks the channel region is realized. That is, the normally-off JF
An ET can be obtained, and the JFET can be mounted on a rotating device or the like without attaching a circuit that takes measures against complicated gate circuit failure.

According to a fourteenth aspect of the present invention, there is provided a lateral JFET comprising a semiconductor substrate, a second conductivity type semiconductor film formed on the substrate, and a first conductivity type semiconductor film formed on the second conductivity type semiconductor film. A film, a channel region formed by reducing the thickness of the first conductivity type semiconductor film, and a film made of the first conductivity type semiconductor formed on the first conductivity type semiconductor film, The semiconductor device includes a source region and a drain region separately formed on both sides of the region, and a gate electrode formed in the region of the second conductivity type semiconductor. In this lateral JFET, the thickness of the channel region depends on the diffusion potential at the junction between the second conductivity type semiconductor film and the first conductivity type semiconductor film formed on the second conductivity type semiconductor film. It is smaller than the width of the depletion layer in the type semiconductor film.

With the above configuration, for example, a depletion layer due to a diffusion potential is spread at the junction between the channel region (the first conductivity type semiconductor layer) and the underlying second conductivity type semiconductor layer to obtain a normally-off JFET. be able to. That is, the present invention is not limited to the case where the impurity concentration of the channel region is lower than that of the side portion.
A normally-off JFET can be obtained.

[0041]

Next, an embodiment of the present invention will be described with reference to the drawings.

(Embodiment 1) FIG. 1 is a sectional view of a lateral JFET according to Embodiment 1. In FIG. 1, 6
On a H-SiC substrate 1, a 6H-p + type SiC film 2 is formed. It is of course possible to use a 4H type substrate in addition to the 6H type substrate. Hereinafter, "6H-" or "4H-" is omitted. In FIG. 1, channel region 2
Numeral 1 contains an n-type impurity at a higher concentration than the impurity concentration of the n-type SiC film 3 on both sides thereof. The source electrode 12 and the drain electrode 13 are formed in the source region and the drain region, which are the n + SiC films 4 located above both sides of the channel, respectively, as viewed from the channel region 21. The end of the p + -type SiC film 2 is connected to the upper n-type SiC film 3.
Two gate electrodes 14 are formed on one comparatively wide flat surface which is not covered with and sandwiches the source electrode 12 and the drain electrode 13 formed above the center. ing. That is, the source,
The conductive path between the drain region and the gate electrode has a wide cross section without any narrow part in the middle due to a groove or the like. The impurity concentration of each region is, for example, as follows. Channel region 21: n-type impurity> 1 × 10 ¹⁸ cm ⁻³ n-type SiC films on both sides of channel region 3: n-type impurity 2
× 10 ¹⁷ cm ^-3 source and drain regions (n + -type SiC film) 4: n-type impurity> 1 × 10 ¹⁹ cm ^-3 p-type SiC film 2: p-type impurity> 1 × 10 ¹⁹ cm ^-3 In the region, the thickness a, the length l, and the width w in the direction perpendicular to the paper surface can be determined according to the size of the element.
Since the source electrode 12 and the source region 22 and the drain electrode 13 and the drain region 23 are connected to a high-concentration region having an impurity concentration of more than 1 × 10 ¹⁹ cm ⁻³ and a metal film, for example, Ni is used as a material for the metal film. Thereby, an ohmic contact can be formed. Further, the connection between the gate electrode 14 and the p-type SiC film 2 as the gate region is also a connection between the high concentration region having an impurity concentration of more than 1 × 10 ¹⁹ cm ⁻³ and the metal film. Ohmic contact can be formed by using a material and performing heat treatment.

In the ON state of the lateral JFET, carriers flow from the source electrode 12 to the drain region 23 through the source region 22 and the channel region 21.
In this path, since the channel region has a high impurity concentration even if the cross-sectional area is small, the resistance can be reduced, the on-resistance is reduced, and the power consumption can be reduced. Therefore, even if a large current flows, the power loss is small and the heat generation can be suppressed low. On the other hand, the gate electrode 1
4 to form a depletion layer on the n-type SiC film side of the pn junction. This depletion layer is formed in the channel region 21
, And grows into the channel so as to block the path cross section of the channel region as the reverse bias voltage is increased. The channel is turned off when the path cross section of the channel region is closed by the depletion layer.

By using the structure of the lateral JFET, the breakdown voltage can be improved without increasing the on-resistance, the switching response time can be shortened, and a JFET having stable performance can be provided. Therefore, it can be used as a high-speed switching element for low loss and large power. This horizontal JFET has a simple and easy manufacturing process, and rarely causes troubles such as a decrease in yield, so that it can be manufactured at a low cost after all.

(Second Embodiment) FIG. 2 is a sectional view of a lateral JFET according to a second embodiment. The impurity concentration of portions other than the gate electrode is the same as that of the lateral JFET of FIG.
FIG. 2 is characterized in that the gate electrode 14 is formed over the back surface of the p-type SiC substrate 1. According to the configuration of FIG. 2, the ON / OFF state can be realized by applying the same gate voltage as in FIG. Further, the gate resistance Rg can be further reduced, and as a result, the rise (fall) time of switching can be shortened. Further, the manufacturing method is simplified, and the yield can be improved.

(Embodiment 3) FIG. 3 is a sectional view of a lateral JFET according to Embodiment 3. 3, the thickness a of the channel region 21, pn ^- diffusion potential of the junction (2
(Approximately V to 3 V) to make the width smaller than the depletion layer width generated on the side of the n ⁻ layer. In addition, although it is “width” at the joint, FIG.
In, the “width” is the thickness. Specifically, n
^- when the impurity concentration of the layer with 1 × 10 ¹⁶ cm ^-3, thickness a of the channel region becomes 500nm or less. The impurity concentration n of the channel region is preferably higher than the concentration n− of the n− layer. In order to realize the ON state in the lateral JFET of FIG. 3, a positive potential higher than the source potential is applied to the gate electrode. If the gate potential is increased above the diffusion potential,
Since the pn-junction becomes conductive, it is meaningless to increase the gate potential beyond the diffusion potential. That is, in the off state, the gate potential may be zero potential, and in the on state, the gate potential may be a positive potential of about 3V.

Next, the withstand voltage design of the lateral JFET shown in FIG. 3 will be described. The withstand voltage design is 200 V, and the thickness W of the n-type SiC film 3 in FIG. 3 is 900 nm. At this time, based on the relationship between W and the breakdown voltage shown in FIG.
10-220V, certainly exceeding 200V. When W is 900 nm, the thickness a of the channel region is set to 500 nm.
The impurity concentration of the n − layer that gives the thickness of the depletion layer due to the diffusion potential larger than the thickness a is about 1 × 10 ¹⁶ cm ⁻³ or less as described above. Further, the impurity concentration n of the channel region 21 can be set to 3.8 × 10 ¹⁷ cm ⁻³ , which is higher than the impurity concentration of the n − layer. In this way, it is possible to obtain a normally-off lateral JFET while ensuring the withstand voltage. Therefore, a normally-off state can be realized, power consumption can be reduced, and control can be performed using the horizontal JFET without taking measures against a failure of a gate circuit in a rotating machine or the like. .

(Embodiment 4) FIG. 5 is a sectional view of a lateral JFET according to Embodiment 4. In FIG. 5, n
The type SiC film has two layers, a lower n ⁻ layer 3a and an upper n ₁ layer 3b, on both sides of the channel region 21. For withstand voltage, high-speed on / off operation, and the like, and for realization of a normally-off state, it is desirable that n ₁ and n ₂ have a higher concentration than n ⁻ , and n ₂ is higher than n _1. It is desirable to be a concentration. According to this configuration, a high-speed on / off operation and a high withstand voltage can be ensured at a high level, and a normally-off lateral JFET can be obtained as in the third embodiment.

In order to obtain a withstand voltage of 200 V, the thickness W of the two layers (n ⁻ layer / n ₁ layer) is set to 1200 nm, and the impurity concentration is set as follows. The concentration of the upper n-layer n ₁ = 1 × 10 ¹⁷ cm ⁻³ , and the concentration of the lower n-layer n ⁻ = 1 × 1
0 ¹⁶ cm ⁻³ , the concentration n _{2 in the} channel region = 3.8 × 10 ¹⁷
By setting cm ⁻³ and the channel region thickness a = 500 nm, a breakdown voltage of 200 V can be ensured, and a normally-off lateral JFET with high-speed on-off operation can be obtained.

[0050]

EXAMPLE A lateral JFET using the structure shown in FIG. 1 was manufactured. FIG. 1 illustrates a method of manufacturing a conventional lateral JFET.
FIGS. 6 to 8 are diagrams illustrating steps corresponding to FIGS. First, a p + -type SiC film is formed on a p-type SiC substrate, and then an n-type SiC film is formed. This n-type SiC
The impurity concentration of the film 3 was 1.66 × 10 ¹⁷ cm ⁻³ .
Further, after forming an n + -type SiC film thereon, etching is performed by RIE to pattern a region including the source and drain regions (FIG. 6). Then the sauce,
Etching is performed by RIE at the center of the portion including the drain region to form a groove, so that the source region 22 and the drain region 23 are separated from each other. An n-type impurity is doped into the channel region 21 formed below the bottom of the groove by ion implantation (FIG. 7). Channel region 21
Was set to 1.36 × 10 ¹⁸ cm ⁻³ .
Channel length 1 is 8 μm, channel thickness a is 214 nm
(0.214 μm), and the width w in the direction perpendicular to the paper is 0.7
It was 2 mm. Next, a gate electrode is formed on the p + SiC film 2 and a source region 22 which is an n + impurity region.
And a drain region 23 are provided with a source electrode 12 and a drain electrode 13, respectively (FIG. 8). After this, p +
An etching step for providing a groove in the SiC film 2 is not provided.
In the lateral JFET of the comparative example, as shown in FIG. 9, the impurity concentration of the source region and the drain region was not particularly increased, and the concentration of the n-type SiC film 3 was kept at 1.66 × 10 ¹⁷ cm ⁻³ . The shape of the channel is the horizontal J
Same as FET. The breakdown voltage and on-resistance were measured for both lateral JFETs. Table 1 shows the results of both measurements.

[0051]

[Table 1]

As shown in Table 1, the on-resistance was 2.20 mΩ · cm ² to 0.93 m while the breakdown voltage was as high as 155 V.
Ω · cm ² could be reduced.

While the embodiments and examples of the present invention have been described above, the embodiments and examples of the present invention disclosed above are merely examples, and the scope of the present invention is not limited to these. The invention is not limited to the embodiments and examples. The scope of the present invention is shown by the description of the claims, and further includes all modifications within the meaning and scope equivalent to the description of the claims.

[0054]

According to the present invention, it is possible to provide a lateral JFET suitable for a high-power semiconductor switching element having high withstand voltage and high speed. Since this lateral JFET can be manufactured by a simple and stable manufacturing process, it can be manufactured with a high yield.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a lateral JFET according to a first embodiment.

FIG. 2 is a cross-sectional view of a lateral JFET according to a second embodiment.

FIG. 3 is a cross-sectional view of a lateral JFET according to a third embodiment.

FIG. 4 is a diagram showing a relationship between an element breakdown voltage and W.

FIG. 5 is a cross-sectional view of a lateral JFET according to a fourth embodiment.

FIG. 6 is a cross-sectional view of a stage in which an n + SiC film is formed and patterned by RIE in an intermediate fabrication stage of the lateral JFET of FIG. 1;

7 is a cross-sectional view at a stage where a channel region is formed by RIE after the stage of FIG. 6 and impurities are ion-implanted.

FIG. 8 is a cross-sectional view of a stage where an electrode is formed by forming a Ni film after the stage of FIG. 7;

FIG. 9 is a configuration sectional view of a conventional lateral JFET.

FIG. 10 is a cross-sectional view of a stage in which an n-channel layer is formed in an intermediate fabrication stage of the lateral JFET of FIG. 9;

11 is a cross-sectional view of a stage where a Ni film as a first layer of a two-layer electrode is formed after the stage of FIG. 10;

FIG. 12 is a cross-sectional view of a stage where an Al film as a second layer of the two-layer electrode is formed after the stage of FIG. 11;

FIG. 13 is a cross-sectional view of a stage where a groove is provided between the gate region and the center after the stage of FIG. 12;

[Explanation of symbols]

1 p-type SiC substrate, 1 a SiC substrate, 2 p-type Si
C film, 3 n type SiC layer, 3a n ^- layer (lower layer n layer),
3b n ₁ layer (upper n layer), 4 n + -type SiC film (source and drain regions), 5 insulating film, 21 channel region, 12 source electrode, 13 drain electrode, 14 gate electrode, 20 Ni layer, 22 source region , 23 drain region, 114 gate region, 120 Ni film, 1
21 Al film, 115 grooves, a channel region thickness, n
The n-type impurity concentration of the _two- channel region and the total thickness of the n − layer and the n ₁ layer on the side of the W channel region.

Continued on the front page F term (reference) 5F045 AB06 AF02 AF13 BB16 DA53 DA59 DA66 5F102 FA00 FA01 GC02 GD04 GJ02 GK02 GL02 GN02 GV00 GV05 HC01 HC07 HC16

Claims (14)

[Claims] A first conductive type semiconductor film formed on the semiconductor substrate; a second conductive type semiconductor film formed on the substrate; a first conductive type semiconductor film formed on the second conductive type semiconductor film; A channel region formed with a reduced thickness in the type semiconductor film; and a film made of the first conductivity type semiconductor formed on the first conductivity type semiconductor film, on both sides of the channel region. A source region and a drain region that are formed separately, and a gate electrode that is formed in a region of the second conductivity type semiconductor, wherein the channel region has an impurity concentration of a portion of the first conductivity type semiconductor film on both sides thereof. A lateral junction field effect transistor, which also contains a high concentration of first conductivity type impurities. 2. The second conductive type semiconductor film has a surface without a groove, and the gate electrode is formed on a flat surface of the second conductive type semiconductor film which is a region of the second conductive type semiconductor. 2. The lateral junction field-effect transistor according to claim 1, comprising two gate electrodes. 3. The semiconductor substrate according to claim 1, wherein the semiconductor substrate is a second conductivity type semiconductor substrate containing a second conductivity type impurity, and the gate electrode is a region of the second conductivity type semiconductor, a back surface of the second conductivity type semiconductor substrate. 2. The lateral junction field-effect transistor according to claim 1, wherein the lateral junction field-effect transistor is constituted by a back gate structure provided over the entire surface. 4. The method according to claim 1, wherein the source region and the drain region are
4. The lateral junction field-effect transistor according to claim 1, wherein the lateral junction field-effect transistor is a region containing a first-conductivity-type impurity at a higher concentration than a portion of the first-conductivity-type semiconductor film on both sides of the channel region. 5. . 5. The lateral junction field effect transistor according to claim 1, wherein an impurity concentration of said second conductivity type semiconductor film exceeds 10 ¹⁹ cm ⁻³ . 6. A source electrode formed on the source region, a drain electrode formed on the drain region, and a gate electrode formed on the region of the second conductivity type semiconductor, respectively. The lateral junction field-effect transistor according to claim 1, wherein the lateral junction field-effect transistor is formed of a metal that forms an ohmic contact with a semiconductor containing an impurity that contacts the transistor. 7. The lateral junction field effect transistor according to claim 1, wherein a surface excluding the source electrode, the drain electrode, and the gate electrode is covered with an insulating film. 8. The semiconductor device according to claim 1, wherein the semiconductor substrate is a SiC substrate, the first conductivity type semiconductor film is a first conductivity type SiC film, and the second conductivity type semiconductor film is a second conductivity type SiC film. 8. The lateral junction field effect transistor according to any one of 1 to 7. 9. The SiC substrate is a 6H—SiC substrate, and the second conductive SiC film and the first conductive Si
9. The lateral junction field effect transistor according to claim 8, wherein each of the C films is 6H-SiC. 10. The SiC film of the second conductivity type and the SiC film of the first conductivity type are both 4H-SiC.
The second conductivity type SiC film made of H-SiC is 6H-Si.
9. The lateral junction field effect transistor according to claim 8, wherein the lateral junction field effect transistor is formed on a C substrate via a 4H-SiC buffer layer. 11. The SiC substrate is a 4H—SiC substrate, and the second conductive type SiC film and the first conductive type S
9. The lateral junction field effect transistor according to claim 8, wherein each of the iC films is 4H-SiC. 12. The second conductivity type SiC film and the first conductivity type SiC film are both 6H-SiC,
The second conductivity type SiC film made of H-SiC is 4H-Si.
9. The lateral junction field effect transistor according to claim 8, wherein the transistor is formed on a C substrate via a 6H-SiC buffer layer. 13. The method according to claim 1, wherein the thickness of the channel region is the second.
Depletion in the first conductivity type semiconductor film due to the diffusion potential at the junction between the conductivity type semiconductor film and the channel region side of the first conductivity type semiconductor film formed on the second conductivity type semiconductor film 13. The lateral junction field-effect transistor according to claim 1, which is smaller than a layer width. 14. A semiconductor substrate; a second conductivity type semiconductor film formed on the substrate; a first conductivity type semiconductor film formed on the second conductivity type semiconductor film; A channel region formed with a reduced thickness in the type semiconductor film; and a film made of the first conductivity type semiconductor formed on the first conductivity type semiconductor film, on both sides of the channel region. A source region and a drain region formed separately, and a gate electrode formed in a region of the second conductivity type semiconductor, wherein the thickness of the channel region is the second conductivity type semiconductor film; The first semiconductor layer formed on the first type semiconductor film;
A lateral junction field-effect transistor having a width smaller than a depletion layer width in the first conductivity type semiconductor film due to a diffusion potential at a junction with the conductivity type semiconductor film.