JP2001232839A - Thermal head - Google Patents

Thermal head

Info

Publication number
JP2001232839A
JP2001232839A JP2000046309A JP2000046309A JP2001232839A JP 2001232839 A JP2001232839 A JP 2001232839A JP 2000046309 A JP2000046309 A JP 2000046309A JP 2000046309 A JP2000046309 A JP 2000046309A JP 2001232839 A JP2001232839 A JP 2001232839A
Authority
JP
Japan
Prior art keywords
bonding pad
bonding
electrode pattern
lead
wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000046309A
Other languages
Japanese (ja)
Inventor
Naoki Takojima
直樹 田古嶋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba Hokuto Electronics Corp
Original Assignee
Toshiba Corp
Toshiba Hokuto Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Hokuto Electronics Corp filed Critical Toshiba Corp
Priority to JP2000046309A priority Critical patent/JP2001232839A/en
Publication of JP2001232839A publication Critical patent/JP2001232839A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
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    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
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    • H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electronic Switches (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a thermal head which can prevent a bonding wire 13 from contacting the other electrode pattern 4 when the electrode pattern 4 is wire bonded to a bonging pad 7. SOLUTION: A plurality of heating resistors 3 are formed on a substrate 1. The electrode pattern 4 including a lead wire 6 to be connected to each heating resistor 3 and bonding pad 7 is formed. The lead wire 6 in the periphery of the bonding pad 7 is placed to a lower position by 0.3-120 μm from the substrate 1 than a surface of the bonding pad 7. The bonding wire 13 connected to the bonding pad 7 can be prevented from contacting the lead wire 6 of the other electrode pattern 4 wired in the periphery of the bonding pad 7.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、発熱抵抗体に接続
された電極パターンのボンディングパッドを介して電気
的に結線されるサーマルヘッドに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thermal head which is electrically connected via a bonding pad of an electrode pattern connected to a heating resistor.

【０００２】[0002]

【従来の技術】サーマルヘッドは、たとえば、ビデオプ
リンタ、カード印刷機、製版機などに用いられている。2. Description of the Related Art Thermal heads are used in, for example, video printers, card printers, plate making machines and the like.

【０００３】従来のサーマルヘッドは、図３に示すよう
に、アルミナなどの基体１上に保温および平滑層として
グレーズ層２を形成し、このグレーズ層２上に、複数の
発熱抵抗体３を主走査方向に沿って並列に形成するとと
もに、これら各発熱抵抗体３の発熱部3aを介して接続さ
れる複数の個別電極の電極パターン４および共通電極の
電極パターン５を形成している。In a conventional thermal head, as shown in FIG. 3, a glaze layer 2 is formed as a heat insulating and smoothing layer on a substrate 1 made of alumina or the like, and a plurality of heating resistors 3 are mainly formed on the glaze layer 2. In addition to being formed in parallel along the scanning direction, the electrode pattern 4 of a plurality of individual electrodes and the electrode pattern 5 of a common electrode connected via the heating portion 3a of each heating resistor 3 are formed.

【０００４】各電極パターン４は、各発熱抵抗体３に接
続されるリード配線６およびこのリード配線６に接続さ
れたボンディングパッド７を有し、隣接する電極パター
ン４のボンディングパッド７の位置を互いにずらして配
列するとともに、各位置毎に複数の電極パターン４のボ
ンディングパッド７を並列に配列して複数列のボンディ
ングパッド列８を形成している。Each electrode pattern 4 has a lead wire 6 connected to each heating resistor 3 and a bonding pad 7 connected to the lead wire 6, and positions of the bonding pads 7 of the adjacent electrode patterns 4 are mutually set. A plurality of bonding pad rows 8 are formed by arranging the bonding pads 7 of the plurality of electrode patterns 4 in parallel with each other at each position.

【０００５】発熱抵抗体３および電極パターン４が形成
されたグレーズ層２の表面には、電極パターン４のボン
ディングパッド７の部分を除いて保護層９を形成してい
る。[0005] On the surface of the glaze layer 2 on which the heating resistor 3 and the electrode pattern 4 are formed, a protective layer 9 is formed except for the bonding pad 7 of the electrode pattern 4.

【０００６】サーマルヘッドを駆動するドライバ部側で
は、プリント基板10上にドライバＩＣ11を搭載してお
り、このドライバＩＣ11のボンディングパッド12と電極
パターン４のボンディングパッド７とを、金線などのボ
ンディングワイヤ13を用いたワイヤボンディングにより
結線している。On the driver side for driving the thermal head, a driver IC 11 is mounted on a printed circuit board 10. The bonding pads 12 of the driver IC 11 and the bonding pads 7 of the electrode pattern 4 are connected to bonding wires such as gold wires. 13 are connected by wire bonding.

【０００７】[0007]

【発明が解決しようとする課題】ところで、最近のサー
マルヘッドは、より高画質の追求などに基づく電極パタ
ーン４の高密度化に伴い、隣接する電極パターン４間の
距離が縮小したり、ボンディングパッド７の周辺のパタ
ーンが複雑化する傾向にある。このような場合、ワイヤ
ボンディング時に電極パターン４のボンディングパッド
７とドライバＩＣ11のボンディングパッド12とを結線す
る際に、たとえば、図４に示すように、結線材料として
用いられるボンディングワイヤ13のねじれ、たれなどに
より、ボンディングワイヤ13が隣接する他の電極パター
ン４のリード配線６などに接触し、配線不良となる。ま
た、ワイヤボンディング時に配線不良が生じなくとも、
ドライバＩＣ11をシリコーン樹脂などで封止する際に、
ボンディングワイヤ13が他の電極パターン４のリード配
線６に接触し、配線不良となる問題がある。By the way, in recent thermal heads, the distance between the adjacent electrode patterns 4 has been reduced or the bonding pad has been increased as the density of the electrode patterns 4 has increased due to the pursuit of higher image quality. 7 tends to be more complicated. In such a case, when connecting the bonding pad 7 of the electrode pattern 4 and the bonding pad 12 of the driver IC 11 at the time of wire bonding, for example, as shown in FIG. 4, the bonding wire 13 used as a connection material is twisted or sagged. As a result, the bonding wire 13 comes into contact with the lead wiring 6 of another electrode pattern 4 adjacent thereto, resulting in a wiring failure. Also, even if no wiring failure occurs during wire bonding,
When sealing the driver IC 11 with silicone resin, etc.
There is a problem that the bonding wire 13 comes into contact with the lead wiring 6 of another electrode pattern 4 to cause a wiring failure.

【０００８】このような課題を解決するため、たとえ
ば、特開平１１−４８５１４号公報に示されるように、
ボンディングパッド７やボンディングパッド列８のみを
保護層９から露出させる場合では、基体１上の発熱抵抗
体３を含む電極パターン４全面に保護層９をスパッタ法
により成膜したあと、ボンディングパッド７を選択的に
ＲＩＥ（リアクティプ・イオン・エッチング）にて開口
させるためにエッチングマスクを作成しなくてはならな
いとともに、保護層９上にフォトレジストを塗布または
コーティングして再度フォトリソグラフィー技術を用い
る必要がある。To solve such a problem, for example, as disclosed in Japanese Patent Application Laid-Open No. H11-48514,
When only the bonding pad 7 and the bonding pad row 8 are exposed from the protective layer 9, the protective layer 9 is formed by sputtering on the entire surface of the electrode pattern 4 including the heating resistor 3 on the base 1, and then the bonding pad 7 is removed. An etching mask must be created in order to selectively open by RIE (reactive ion etching), and a photoresist must be applied or coated on the protective layer 9 and photolithography technology must be used again. .

【０００９】しかし、ドライエッチング時のフォトレジ
ストの選択比が低いため、フォトレジストの厚みを保護
層９の厚みに対して３〜５倍程度厚くする必要があり、
ローラー方式、スピン方式の何れをとっても厚さの均一
性を得ることが困難であるという問題がある。このと
き、ドライフィルムを用い、エッチングマスクを形成す
る方法もあるが、ＳｉＯＮ系の保護層９上への密着カが
弱く、各ボンディングパッド列８間に保護層９を残すた
めに細線を設けても現像時に剥れが生じ、所望の部分の
みを露出させることが困難である。However, since the selectivity of the photoresist at the time of dry etching is low, it is necessary to make the thickness of the photoresist approximately three to five times as large as the thickness of the protective layer 9.
There is a problem that it is difficult to obtain a uniform thickness in any of the roller method and the spin method. At this time, there is a method of forming an etching mask using a dry film. However, adhesion to the SiON-based protective layer 9 is weak, and a thin line is provided to leave the protective layer 9 between the bonding pad rows 8. Also, peeling occurs during development, and it is difficult to expose only a desired portion.

【００１０】また、製造プロセスを工夫してボンディン
グパッド７のみを露出させることができたとしても、基
体１上のボンディングパッド７とドライバＩＣ11を電気
的に結線する際にワイヤボンディング装置の精度によ
り、ボンディングパッド７の周囲の保護層９とボンディ
ングワイヤ13を送り出すキャピラリとが干渉し、ボンデ
ィングワイヤ13がボンディングパッド７に対して不着と
なり、配線不良となる問題がある。Even if only the bonding pads 7 can be exposed by devising the manufacturing process, even if the bonding pads 7 on the base 1 are electrically connected to the driver IC 11 due to the accuracy of the wire bonding apparatus, There is a problem that the protective layer 9 around the bonding pad 7 and the capillary that sends out the bonding wire 13 interfere with each other, so that the bonding wire 13 is not attached to the bonding pad 7 and wiring failure occurs.

【００１１】本発明は、このような点に鑑みなされたも
ので、電極パターンのボンディングパッドに対するワイ
ヤボンディング時などに、ボンディングワイヤが他の電
極パターンと接触するのを防止でき、配線不良を防止で
き、歩留りおよび信頼性を向上できるサーマルヘッドを
提供することを目的とする。The present invention has been made in view of the above points, and can prevent a bonding wire from coming into contact with another electrode pattern at the time of wire bonding of an electrode pattern to a bonding pad and the like, and can prevent a wiring defect. It is another object of the present invention to provide a thermal head capable of improving yield and reliability.

【００１２】[0012]

【課題を解決するための手段】本発明は、基体と、この
基体上に形成された複数の発熱抵抗体と、前記基体上に
形成され、前記各発熱抵抗体に接続されるリード配線お
よびこのリード配線に接続されるボンディングパッドを
有し、基体からの高さがボンディングパッドの表面より
ボンディングパッドの周辺のリード配線が０．３〜１２
０μｍ低い位置に位置する複数の電極パターンとを具備
しているものである。そして、基体からの高さをボンデ
ィングパッドの表面よりボンディングパッドの周辺のリ
ード配線を０．３〜１２０μｍ低い位置に位置させたこ
とにより、ワイヤボンディング時のボンディングワイヤ
がボンディングパッドの周囲に配線された他の電極パタ
ーンのリード配線と接触するのが防止される。０．３μ
ｍ以下では高低差が少なすぎるためにボンディングワイ
ヤが他の電極パターンのリード配線と接触するのを防止
する効果が少なく、１２０μｍ以上では高低差が大きす
ぎるために所定の電極パターンに形成できなかったりリ
ード配線の切れなどが発生しやすくなるので、０．３〜
１２０μｍの範囲とすることが必要である。According to the present invention, there is provided a base, a plurality of heating resistors formed on the base, lead wires formed on the base and connected to the respective heating resistors, and lead wires. A bonding pad connected to the lead wiring, wherein a height of the lead wiring around the bonding pad from the surface of the bonding pad is 0.3 to 12 from the surface of the bonding pad;
And a plurality of electrode patterns located at a position lower by 0 μm. By positioning the lead wiring around the bonding pad at a height lower than the surface of the bonding pad by 0.3 to 120 μm below the height from the base, the bonding wire at the time of wire bonding was wired around the bonding pad. Contact with the lead wiring of another electrode pattern is prevented. 0.3μ
If the height is less than m, the effect of preventing the bonding wire from coming into contact with the lead wiring of another electrode pattern is small because the height difference is too small. Since the lead wiring is likely to break,
It is necessary to be in the range of 120 μm.

【００１３】また、隣接する電極パターンのボンディン
グパッドの位置が互いにずれて配列されるとともにこれ
ら各位置毎に複数の電極パターンのボンディングパッド
が並列に配列されて複数列のボンディングパッド列が形
成され、これらボンディングパッド列の列間のリード配
線がボンディングパッドの表面より低い位置に位置する
ことにより、複数の電極パターンが高密度に配線された
場合でも、ボンディングワイヤがボンディングパッド列
の列間に位置する他の電極パターンのリード配線と接触
するのが防止される。The positions of the bonding pads of adjacent electrode patterns are shifted from each other, and the bonding pads of a plurality of electrode patterns are arranged in parallel at each of these positions to form a plurality of bonding pad rows. Since the lead wires between the rows of the bonding pad rows are positioned lower than the surface of the bonding pads, the bonding wires are positioned between the rows of the bonding pad rows even when a plurality of electrode patterns are densely wired. Contact with the lead wiring of another electrode pattern is prevented.

【００１４】また、基体上に形成されるとともに、表面
に発熱抵抗体および電極パターンが形成されるグレーズ
層を具備し、このグレーズ層の表面に、ボンディングパ
ッドの表面より低い位置に位置されるリード配線が形成
される凹部が形成されていることにより、リード配線を
ボンディングパッドの表面より低い位置に位置させるこ
とが可能となる。A glaze layer formed on the base and having a heating resistor and an electrode pattern formed on the surface thereof is provided, and a lead positioned lower than the surface of the bonding pad is provided on the surface of the glaze layer. By forming the concave portion in which the wiring is formed, the lead wiring can be positioned lower than the surface of the bonding pad.

【００１５】また、基体上に少なくとも各電極パターン
のボンディングパッドの部分を除いて形成された保護層
を具備している場合、ボンディングパッドの表面より低
い位置のリード配線上に形成された保護層の高さが低く
なり、ワイヤボンデング時にボンディングワイヤを供給
するキャピラリが保護層と干渉するのが防止される。Further, when a protective layer is formed on the base except at least the bonding pad portion of each electrode pattern, the protective layer formed on the lead wiring at a position lower than the surface of the bonding pad is provided. The height is reduced, and the capillary for supplying the bonding wire during wire bonding is prevented from interfering with the protective layer.

【００１６】[0016]

【発明の実施の形態】以下、本発明の一実施の形態を図
１および図２を参照して説明する。なお、図３および図
４に示した構成と同様の構成については同一符号を用い
て説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. Note that components similar to those shown in FIGS. 3 and 4 will be described using the same reference numerals.

【００１７】図１および図２において、たとえばアルミ
ナなどの基体１上に保温および平滑層としてグレーズ層
２が形成され、このグレーズ層２上に、複数の発熱抵抗
体３が主走査方向に沿って並列に形成されているととも
に、これら各発熱抵抗体３の発熱部を介して接続される
複数の個別電極の電極パターン４および共通電極の電極
パターンが形成されている。In FIGS. 1 and 2, a glaze layer 2 is formed as a heat-retaining and smoothing layer on a substrate 1 such as alumina, and a plurality of heating resistors 3 are formed on the glaze layer 2 in the main scanning direction. An electrode pattern 4 of a plurality of individual electrodes and an electrode pattern of a common electrode which are formed in parallel and are connected via the heat generating portion of each of the heat generating resistors 3 are formed.

【００１８】各電極パターン４は、各発熱抵抗体３に接
続されるリード配線６およびこのリード配線６に接続さ
れたボンディングパッド７を有し、隣接する電極パター
ン４のボンディングパッド７の位置が互いにずれて配列
されているとともに、各位置毎に複数の電極パターン４
のボンディングパッド７が並列に配列されて複数列のボ
ンディングパッド列８が形成されている。Each electrode pattern 4 has a lead wire 6 connected to each heating resistor 3 and a bonding pad 7 connected to the lead wire 6, and the positions of the bonding pads 7 of the adjacent electrode patterns 4 are mutually different. A plurality of electrode patterns 4 are arranged at each position while being shifted.
Are arranged in parallel to form a plurality of bonding pad rows 8.

【００１９】発熱抵抗体３および電極パターン４が形成
されたグレーズ層２の表面には、電極パターン４のボン
ディングパッド７の部分、すなわち各ボンディングパッ
ド列８を除いて保護層９が形成されている。On the surface of the glaze layer 2 on which the heating resistor 3 and the electrode pattern 4 are formed, a protective layer 9 is formed except for the bonding pad 7 of the electrode pattern 4, that is, except for each bonding pad row 8. .

【００２０】サーマルヘッドを駆動するドライバ部側で
は、プリント基板上にドライバＩＣが搭載されており、
このドライバＩＣのボンディングパッドと電極パターン
４のボンディングパッド７とが、金線などのボンディン
グワイヤ13を用いたワイヤボンディングにより結線され
ている。On the driver side for driving the thermal head, a driver IC is mounted on a printed circuit board.
The bonding pad of the driver IC and the bonding pad 7 of the electrode pattern 4 are connected by wire bonding using a bonding wire 13 such as a gold wire.

【００２１】また、グレーズ層２の表面には、ボンディ
ングパッド列８の列間に対応して凹部21が形成され、こ
の凹部21にリード配線６が形成されている。したがっ
て、基体１からの高さがボンディングパッド７の表面よ
りボンディングパッド列８の列間のリード配線６が低い
位置に位置されている。これらボンディングパッド７と
このボンディングパッド７の表面より低い位置に位置さ
れるリード配線６との高低差は、０．３〜１２０μｍの
範囲に設定されている。A recess 21 is formed on the surface of the glaze layer 2 between the bonding pad rows 8, and the lead wiring 6 is formed in the recess 21. Therefore, the height of the lead wires 6 between the bonding pad rows 8 is lower than the surface of the bonding pad 7 from the surface of the base 1. The height difference between these bonding pads 7 and the lead wires 6 positioned lower than the surface of the bonding pads 7 is set in the range of 0.3 to 120 μm.

【００２２】次に、サーマルヘッドの製造プロセスの例
を説明する。Next, an example of a manufacturing process of the thermal head will be described.

【００２３】基体１上に、厚さ２００μｍのグレーズ層
２を形成する。このグレーズ層２上にラミネータを用い
てドライフィルムレジストを基板１の全面にコーティン
グする。このコーティング時には密着性を確保するため
に、１００℃程度で基体１ごと加熱することが好まし
い。ドライフィルムレジストは、一般的に、たとえばＬ
ＤＰＥなどのカバーフィルムとポリエチレンテフタレー
ト（ＰＥＴ）などのキャリアフィルムにネガタイプのフ
ォトレジスト層がサンドイッチされた構造になってい
る。ラミネータでコーティングした直後にカバーフィル
ムを引き剥がす。A glaze layer 2 having a thickness of 200 μm is formed on a substrate 1. A dry film resist is coated on the entire surface of the glaze layer 2 using a laminator. In this coating, it is preferable to heat the entire substrate 1 at about 100 ° C. in order to secure adhesion. Dry film resists are generally, for example, L
It has a structure in which a negative type photoresist layer is sandwiched between a cover film such as DPE and a carrier film such as polyethylene terephthalate (PET). Immediately after coating with the laminator, peel off the cover film.

【００２４】次いで、所定パターンが刻みこまれたフォ
トマスクを用い、キャリアフィルムを介して露光する。
そして、キャリアフィルムを引き剥がした後、現像し、
凹部21に対応する所定の領域のみグレーズ層２の表面を
露出させてエッチングマスクを形成する。Next, exposure is performed through a carrier film using a photomask in which a predetermined pattern is engraved.
Then, after peeling off the carrier film, develop,
An etching mask is formed by exposing the surface of the glaze layer 2 only in a predetermined region corresponding to the concave portion 21.

【００２５】その後、ウェット法またはドライ法でグレ
ーズ層２の表面を所定の凹部21の探さ分、たとえば約２
０μｍ程度エッチングする。エッチング後にドライフィ
ルムレジストを剥離するため、苛性ソーダなどのアルカ
リ水溶液や専用剥離剤で処理し剥離する。Thereafter, the surface of the glaze layer 2 is cut by a wet method or a dry method by a predetermined depth of the concave portion 21, for example, about 2 μm.
Etch about 0 μm. In order to remove the dry film resist after the etching, the dry film resist is treated with an aqueous alkali solution such as caustic soda or a special remover to remove the resist.

【００２６】若しくは、ドライフィルムレジストの代わ
りに基体１上のグレーズ層２に直接液状フォトレジスト
をロールコーターなどでコーティングし、露光、現像、
エッチング、レジスト剥離工程を経ても良い。Alternatively, instead of a dry film resist, a liquid photoresist is directly coated on the glaze layer 2 on the substrate 1 by a roll coater or the like, and then exposed, developed,
Etching and resist stripping steps may be performed.

【００２７】そして、グレーズ層２の表面に凹部21を形
成した後、ＴaＳiＯ2などの発熱抵抗体３の膜、および
Ａlなどの電極パターン４の膜をそれぞれ０．０７μ
ｍ、０．８μｍ程度スパッタリングで成膜する。そし
て、フォトリソグラフィーによりパターニングし、電極
パターン４のリード配線６およびボンディングパッド７
を形成する。After forming the concave portion 21 on the surface of the glaze layer 2, the film of the heating resistor 3 such as TaSiO 2 and the film of the electrode pattern 4 such as Al are each formed to a thickness of 0.07 μm.
m, about 0.8 μm is formed by sputtering. Then, patterning is performed by photolithography, and the lead wiring 6 and the bonding pad 7 of the electrode pattern 4 are formed.
To form

【００２８】基板１上にＳｉＯＮなどの保護層９をスパ
ッタリングで４μｍ程度成膜し、再度ドライフィルムレ
ジストや液状レジストなどをコーティングし、フォトリ
ソグラフィーによりボンディングパッド列８、または発
熱抵抗体３の発熱部3a以外の部分を露出させる部分をパ
ターニング、ＲＩＥ（リアクティプ・イオン・エッチン
グ）にて保護層９を除去し、レジスト層を剥離し、少な
くともボンディングパッド列８を露出させる。A protective layer 9 of SiON or the like is formed to a thickness of about 4 μm on the substrate 1 by sputtering, and is coated again with a dry film resist or a liquid resist, and the bonding pad row 8 or the heating section of the heating resistor 3 is formed by photolithography. The portion exposing the portion other than 3a is patterned, the protective layer 9 is removed by RIE (reactive ion etching), the resist layer is peeled off, and at least the bonding pad row 8 is exposed.

【００２９】次いで、サーマルヘッドを駆動するドライ
バ部側のプリント基板上に搭載されたドライバＩＣのボ
ンディングパッドと、電極パターン４のボンディングパ
ッド７とを、ワイヤボンディング装置により金線などの
ボンディングワイヤ13を用いたワイヤボンディングによ
り結線する。さらに、ドライバＩＣをシリコン樹脂で封
止し、その後、所定の実装工程を経て、サーマルヘッド
が完成する。Then, the bonding pads of the driver IC mounted on the printed circuit board on the driver side for driving the thermal head and the bonding pads 7 of the electrode pattern 4 are connected to bonding wires 13 such as gold wires by a wire bonding apparatus. The connection is made by the used wire bonding. Further, the driver IC is sealed with a silicon resin, and thereafter, through a predetermined mounting process, the thermal head is completed.

【００３０】以上のように構成されるサーマルヘッドで
は、基体１からの高さをボンディングパッド７の表面よ
りボンディングパッド７の周辺のリード配線６を低い位
置に位置させたことにより、ワイヤボンディング時のボ
ンディングワイヤ13がボンディングパッド７の周囲に配
線された他の電極パターン４のリード配線６と接触する
のを防止し、配線不良を防止でき、歩留りおよび信頼性
を向上できる。In the thermal head configured as described above, the height of the lead wire 6 around the bonding pad 7 from the surface of the bonding pad 7 is set lower than the surface of the bonding pad 7, so that the thermal head during wire bonding can be used. It is possible to prevent the bonding wire 13 from coming into contact with the lead wiring 6 of the other electrode pattern 4 wired around the bonding pad 7, prevent the wiring failure, and improve the yield and reliability.

【００３１】また、隣接する電極パターン４のボンディ
ングパッド７の位置が互いにずれて配列されるとともに
これら各位置毎に複数の電極パターン４のボンディング
パッド７が並列に配列されて複数列のボンディングパッ
ド列８が形成され、これらボンディングパッド列８の列
間のリード配線６がボンディングパッド７の表面より低
い位置に位置することにより、複数の電極パターン４が
高密度に配線された場合でも、ボンディングワイヤ13が
ボンディングパッド列８の列間に位置する他の電極パタ
ーン４のリード配線６と接触するのを防止できる。Further, the positions of the bonding pads 7 of the adjacent electrode patterns 4 are arranged to be shifted from each other, and the bonding pads 7 of the plurality of electrode patterns 4 are arranged in parallel at each of these positions to form a plurality of bonding pad rows. 8 are formed, and the lead wires 6 between the rows of the bonding pad rows 8 are positioned lower than the surface of the bonding pads 7, so that even when the plurality of electrode patterns 4 are densely wired, the bonding wires 13 are formed. Can be prevented from contacting with the lead wiring 6 of another electrode pattern 4 located between the bonding pad rows 8.

【００３２】また、グレーズ層２の表面に、ボンディン
グパッド７の表面より低い位置に位置されるリード配線
６が形成される凹部21を形成することにより、リード配
線６をボンディングパッド７の表面より低い位置に位置
させることができる。Further, by forming a recess 21 in the surface of the glaze layer 2 in which the lead wiring 6 located at a position lower than the surface of the bonding pad 7 is formed, the lead wiring 6 is lower than the surface of the bonding pad 7. Position.

【００３３】また、ボンディングパッド７とこのボンデ
ィングパッド７の表面より低い位置に位置されるリード
配線６との高低差は、０．３〜１２０μｍとすることが
必要である。０．３μｍ以下では、高低差が少なすぎる
ために、ボンディングワイヤ13が他の電極パターン４の
リード配線６と接触するのを防止する効果が少ない。１
２０μｍ以上では、配線パターン４のパターニング時に
フォトマスクとフォトレジストとの間（プロキミシティ
ギャップ）が大きいため、露光精度が低まり、設計通り
に電極パターン４を形成できなかったり、基体１上の凹
凸が顕在化してリード配線６の切れなどの要因になり、
薄膜工程での歩留り低下を招く恐れがある。そのため、
０．３〜１２０μｍの範囲とすることが必要で、より好
ましくは６〜３０μｍとなる。The height difference between the bonding pad 7 and the lead wiring 6 located at a position lower than the surface of the bonding pad 7 must be 0.3 to 120 μm. If the thickness is 0.3 μm or less, the height difference is too small, and the effect of preventing the bonding wire 13 from contacting the lead wiring 6 of another electrode pattern 4 is small. 1
When the thickness is 20 μm or more, since the distance between the photomask and the photoresist (the proxicity gap) is large at the time of patterning the wiring pattern 4, the exposure accuracy is reduced, and the electrode pattern 4 cannot be formed as designed, or Irregularities become obvious and cause factors such as breakage of the lead wiring 6,
There is a possibility that the yield may be reduced in the thin film process. for that reason,
It is necessary to be in the range of 0.3 to 120 μm, more preferably 6 to 30 μm.

【００３４】また、基体１上に少なくとも各電極パター
ン４のボンディングパッド７の部分を除いて形成された
保護層９を具備している場合、ボンディングパッド７の
表面より低い位置のリード配線６上に形成された保護層
９の高さが低くなり、ワイヤボンデング時にボンディン
グワイヤ13を供給するキャピラリが保護層９と干渉する
のを防止でき、ボンディングワイヤ13をボンディングパ
ッド７に対して確実に接続できる。When the protective layer 9 is formed on the base 1 except at least the bonding pad 7 of each electrode pattern 4, the protective layer 9 is formed on the lead wiring 6 at a position lower than the surface of the bonding pad 7. The height of the formed protective layer 9 is reduced, so that the capillary supplying the bonding wire 13 during wire bonding can be prevented from interfering with the protective layer 9, and the bonding wire 13 can be reliably connected to the bonding pad 7. .

【００３５】また、保護層９を成膜した基板１上にドラ
イフィルムなどを用いてボンディングパッド列８間のみ
に保護層９を残し、ボンディングパッド７上の保護層９
を除去する製造プロセスの際、ボンディングパッド７の
表面よりボンディングパッド列８間のリード配線６を低
い位置に位置させたことにより、ボンディングパッド列
８間の保護層９上のフォトマスクの剥がれ、ずれなどの
現像不良を低減できるとともに、ボンディングパッド７
上での保護層９が残るのを低減でき、薄膜工程において
も高歩留りを期待できる。On the substrate 1 on which the protective layer 9 is formed, the protective layer 9 is left only between the bonding pad rows 8 using a dry film or the like, and the protective layer 9 on the bonding pad 7 is formed.
In the manufacturing process of removing the lead, the lead wiring 6 between the bonding pad rows 8 is positioned lower than the surface of the bonding pad 7, so that the photomask on the protective layer 9 between the bonding pad rows 8 is peeled off and shifted. And the like.
The remaining protective layer 9 can be reduced, and a high yield can be expected even in a thin film process.

【００３６】そして、ビデオフォトプリンタ用（たとえ
ば３００ｄｐｉ用）として、本実施の形態によるサーマ
ルヘッドと従来技術によるサーマルヘッドとを試作し、
保護層９からボンディングパッド７の部分を開口させて
ワイヤボンディングするまでの製造プロセスにおける歩
留を比較した結果を表１に示す。ボンディングパッド７
の開口部寸法は、主走査方向５５μｍ、副走査方向１６
０μｍである。Then, a thermal head according to the present embodiment and a thermal head according to the prior art were prototyped for a video photo printer (for example, for 300 dpi).
Table 1 shows the results of comparing the yield in the manufacturing process up to the point where the bonding pad 7 is opened from the protective layer 9 and wire bonding is performed. Bonding pad 7
Are 55 μm in the main scanning direction and 16 μm in the sub-scanning direction.
0 μm.

【００３７】[0037]

【表１】 このように、本実施の形態のサーマルヘッドは、従来技
術のサーマルヘッドに比べて、薄膜形成工程および実装
工程での不良を防止でき、歩留りおよび信頼性を向上で
きる。[Table 1] As described above, the thermal head of the present embodiment can prevent defects in the thin film forming step and the mounting step, and can improve the yield and reliability, as compared with the thermal head of the related art.

【００３８】なお、前記実施の形態では、グレーズ層２
の表面に、ボンディングパッド列８の列間に対応して凹
部21を形成することにより、ボンディングパッド７の表
面よりボンディングパッド列８の列間のリード配線６を
低い位置に位置していたが、ボンディングパッド７の部
分のみを他の部分より高くし、ボンディングパッド７の
全周にわたってグレーズ層２に凹部21を形成することに
より、ボンディングパッド７の表面よりボンディングパ
ッド７の周辺に位置する他の電極パターン４のリード配
線６を低い位置に位置させるようにしても、同様の作用
効果を得ることができる。In the above embodiment, the glaze layer 2
The recesses 21 are formed on the surfaces of the bonding pad rows 8 in correspondence with the rows of the bonding pad rows 8, so that the lead wires 6 between the rows of the bonding pad rows 8 are positioned lower than the surface of the bonding pads 7. By forming only the portion of the bonding pad 7 higher than the other portion and forming the concave portion 21 in the glaze layer 2 over the entire periphery of the bonding pad 7, other electrodes located on the periphery of the bonding pad 7 from the surface of the bonding pad 7 are formed. Even when the lead wiring 6 of the pattern 4 is located at a lower position, the same effect can be obtained.

【００３９】また、グレーズ層２に形成した凹部21によ
って、ボンディングパッド７の表面より他の電極パター
ン４のリード配線６を低い位置に位置させていたが、ボ
ンディングパッド７の位置に対応してグレーズ層２を高
く形成することにより、ボンディングパッド７の表面を
他の電極パターン４のリード配線６より高い位置に位置
させても、同様の作用効果を得ることができる。Although the recesses 21 formed in the glaze layer 2 position the lead wires 6 of the other electrode patterns 4 lower than the surface of the bonding pad 7, the glaze corresponds to the position of the bonding pad 7. By forming the layer 2 high, the same function and effect can be obtained even if the surface of the bonding pad 7 is positioned higher than the lead wiring 6 of the other electrode pattern 4.

【００４０】[0040]

【発明の効果】本発明によれば、基体からの高さをボン
ディングパッドの表面よりボンディングパッドの周辺の
リード配線を０．３〜１２０μｍ低い位置に位置させた
ので、ワイヤボンディング時のボンディングワイヤがボ
ンディングパッドの周囲に配線された他の電極パターン
のリード配線と接触するのを防止し、配線不良を防止で
き、歩留りおよび信頼性を向上できる。According to the present invention, the height of the lead wire around the bonding pad from the surface of the bonding pad is lower by 0.3 to 120 μm than the surface of the bonding pad. The contact with the lead wiring of another electrode pattern wired around the bonding pad can be prevented, the wiring failure can be prevented, and the yield and reliability can be improved.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の一実施の形態を示すサーマルヘッドの
断面図である。FIG. 1 is a sectional view of a thermal head showing one embodiment of the present invention.

【図２】同上サーマルヘッドの平面図である。FIG. 2 is a plan view of the thermal head.

【図３】従来のサーマルヘッドを示し、(a)は平面図、
(b)は断面図である。FIG. 3 shows a conventional thermal head, where (a) is a plan view,
(b) is a sectional view.

【図４】従来のサーマルヘッドの断面図である。FIG. 4 is a sectional view of a conventional thermal head.

【符号の説明】[Explanation of symbols]

１ 基体 ２ グレーズ層 ３ 発熱抵抗体 ４ 電極パターン ６ リード配線 ７ ボンディングパッド ８ ボンディングパッド列 ９ 保護層 21 凹部 REFERENCE SIGNS LIST 1 base 2 glaze layer 3 heating resistor 4 electrode pattern 6 lead wiring 7 bonding pad 8 bonding pad row 9 protective layer 21 recess

Claims (4)

【特許請求の範囲】[Claims] 【請求項１】 基体と、 この基体上に形成された複数の発熱抵抗体と、 前記基体上に形成され、前記各発熱抵抗体に接続される
リード配線およびこのリード配線に接続されるボンディ
ングパッドを有し、基体からの高さがボンディングパッ
ドの表面よりボンディングパッドの周辺のリード配線が
０．３〜１２０μｍ低い位置に位置する複数の電極パタ
ーンとを具備していることを特徴とするサーマルヘッ
ド。1. A base, a plurality of heating resistors formed on the base, a lead wire formed on the base and connected to each of the heating resistors, and a bonding pad connected to the lead wiring. And a plurality of electrode patterns whose height from the base is lower than the surface of the bonding pad by 0.3 to 120 μm in the lead wiring around the bonding pad. . 【請求項２】 隣接する電極パターンのボンディングパ
ッドの位置が互いにずれて配列されるとともにこれら各
位置毎に複数の電極パターンのボンディングパッドが並
列に配列されて複数列のボンディングパッド列が形成さ
れ、 これらボンディングパッド列の列間のリード配線がボン
ディングパッドの表面より低い位置に位置することを特
徴とする請求項１記載のサーマルヘッド。2. The bonding pads of adjacent electrode patterns are arranged so as to be shifted from each other, and the bonding pads of a plurality of electrode patterns are arranged in parallel at each of these positions to form a plurality of bonding pad rows. 2. The thermal head according to claim 1, wherein the lead wires between the bonding pad rows are positioned lower than the surface of the bonding pad. 【請求項３】 基体上に形成されるとともに、表面に発
熱抵抗体および電極パターンが形成されるグレーズ層を
具備し、このグレーズ層の表面に、ボンディングパッド
の表面より低い位置に位置されるリード配線が形成され
る凹部が形成されていることを特徴とする請求項１また
は２記載のサーマルヘッド。3. A lead formed on a substrate and having a glaze layer on the surface on which a heating resistor and an electrode pattern are formed, and a lead positioned on the surface of the glaze layer at a position lower than the surface of the bonding pad. 3. The thermal head according to claim 1, wherein a concave portion in which the wiring is formed is formed. 【請求項４】 基体上に少なくとも各電極パターンのボ
ンディングパッドの部分を除いて形成された保護層を具
備していることを特徴とする請求項１ないし３いずれか
記載のサーマルヘッド。4. The thermal head according to claim 1, further comprising a protective layer formed on the substrate except for at least a portion of a bonding pad of each electrode pattern.
JP2000046309A 2000-02-23 2000-02-23 Thermal head Pending JP2001232839A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000046309A JP2001232839A (en) 2000-02-23 2000-02-23 Thermal head

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000046309A JP2001232839A (en) 2000-02-23 2000-02-23 Thermal head

Publications (1)

Publication Number Publication Date
JP2001232839A true JP2001232839A (en) 2001-08-28

Family

ID=18568743

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000046309A Pending JP2001232839A (en) 2000-02-23 2000-02-23 Thermal head

Country Status (1)

Country Link
JP (1) JP2001232839A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007103423A (en) * 2005-09-30 2007-04-19 Renesas Technology Corp Semiconductor device and its manufacturing method
JP2010274466A (en) * 2009-05-27 2010-12-09 Kyocera Corp Head base body, manufacturing method thereof, recording head, and recording apparatus
JP2011009702A (en) * 2009-05-28 2011-01-13 Kyocera Corp Electronic apparatus, image forming apparatus, and image input apparatus
JP2016191878A (en) * 2015-03-31 2016-11-10 住友大阪セメント株式会社 Electric circuit board

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007103423A (en) * 2005-09-30 2007-04-19 Renesas Technology Corp Semiconductor device and its manufacturing method
JP2010274466A (en) * 2009-05-27 2010-12-09 Kyocera Corp Head base body, manufacturing method thereof, recording head, and recording apparatus
JP2011009702A (en) * 2009-05-28 2011-01-13 Kyocera Corp Electronic apparatus, image forming apparatus, and image input apparatus
JP2016191878A (en) * 2015-03-31 2016-11-10 住友大阪セメント株式会社 Electric circuit board

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