JP2001230323A5 - - Google Patents

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JP2001230323A5
JP2001230323A5 JP2000035267A JP2000035267A JP2001230323A5 JP 2001230323 A5 JP2001230323 A5 JP 2001230323A5 JP 2000035267 A JP2000035267 A JP 2000035267A JP 2000035267 A JP2000035267 A JP 2000035267A JP 2001230323 A5 JP2001230323 A5 JP 2001230323A5
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layout
area ratio
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半導体集積回路のレイアウトから配線抵抗や配線容量等の回路パラメータを抽出する方法であって、
モデル配線と該モデル配線の周囲に存在する同層の配線との距離と、該モデル配線のマスクレイアウト幅と仕上がり幅との差との相関データを準備し、
実際のレイアウトから、解析配線の配線長と配線幅を抽出すると共に、該解析配線と同層で周囲に存在する配線との距離を抽出し、
抽出した前記解析配線のレイアウト配線幅と、同じく抽出した前記解析配線と前記解析配線の周囲に存在する前記配線との距離とに対して、前記相関データを参照することによって得られる配線仕上がり幅を用いて、配線抵抗値と配線容量値を算出することを特徴とする回路パラメータ抽出方法。A method for extracting circuit parameters such as wiring resistance and wiring capacitance from a layout of a semiconductor integrated circuit,
Preparing correlation data between the distance between the model wiring and the wiring of the same layer existing around the model wiring and the difference between the mask layout width and the finished width of the model wiring;
From the actual layout, extract the wiring length and wiring width of the analysis wiring, and extract the distance between the analysis wiring and the wiring existing in the same layer,
The wiring finish width obtained by referring to the correlation data with respect to the extracted layout wiring width of the analysis wiring and the distance between the extracted analysis wiring and the wiring existing around the analysis wiring. A circuit parameter extraction method characterized by calculating a wiring resistance value and a wiring capacitance value. 半導体集積回路のレイアウトから配線抵抗や配線容量等の回路パラメータを抽出する方法であって、
モデル配線の配線層の、ある設定領域内における配線パターンの存在割合である配線パターン面積率と、該モデル配線の仕上がり幅の変化量との相関データを準備し、
実際のレイアウトから、解析配線の配線長と配線幅を抽出すると共に、該解析配線の配線層のパターン面積率を計算し、
抽出した前記解析配線の配線長と配線幅と、計算した前記解析配線層の前記パターン面積率とに対して、前記相関データを参照することによって得られる、面積率に起因した配線仕上がり幅の変化量を用いて、配線仕上がり幅を求め、配線抵抗値と配線容量値を算出することを特徴とする回路パラメータ抽出方法。A method for extracting circuit parameters such as wiring resistance and wiring capacitance from a layout of a semiconductor integrated circuit,
Prepare the correlation data between the wiring pattern area ratio, which is the ratio of the wiring pattern existing in the set area of the wiring layer of the model wiring, and the amount of change in the finished width of the model wiring,
Extract the wiring length and wiring width of the analysis wiring from the actual layout, calculate the pattern area ratio of the wiring layer of the analysis wiring,
Changes in the wiring finish width due to the area ratio obtained by referring to the correlation data with respect to the extracted wiring length and wiring width of the analysis wiring and the calculated pattern area ratio of the analysis wiring layer A circuit parameter extraction method characterized by calculating a wiring finish value by using a quantity and calculating a wiring resistance value and a wiring capacitance value. 前記準備する前記相関データを、前記モデル配線の配線断面を、長方形、長方形以外の鋭角や鈍角の角を有する四角形、四角以上の多角形、ある辺の形状をある曲率の円周曲線として表現する形状、およびある辺をある関数曲線で表現する形状のいずれかの変化として表現し、
前記抽出した前記解析配線のレイアウト上の配線長と配線幅に加えて、前記相関データを参照することで求められる仕上がり後の配線断面形状の断面積を計算することにより単位長当たりの配線抵抗値を求め、該単位長当たりの配線抵抗値とレイアウト上の配線長より解析配線の抵抗値と容量値を算出する請求項１または２記載の回路パラメータ抽出方法。The correlation data to be prepared is expressed by representing a cross section of the model wiring as a rectangular curve, a quadrilateral having an acute angle or an obtuse angle other than a rectangle, a polygon having a square or more, and a shape of a side as a circumferential curve having a certain curvature. Express as a change in shape and any shape that represents a side with a function curve,
In addition to the extracted wiring length and wiring width on the layout of the analysis wiring, the wiring resistance value per unit length is calculated by calculating the cross-sectional area of the finished wiring cross-sectional shape obtained by referring to the correlation data The circuit parameter extracting method according to claim 1, wherein the resistance value and the capacitance value of the analysis wiring are calculated from the wiring resistance value per unit length and the wiring length on the layout. 前記配線断面形状を台形形状として取り扱う請求項３記載の回路パラメータ抽出方法。  The circuit parameter extracting method according to claim 3, wherein the wiring cross-sectional shape is handled as a trapezoidal shape. 半導体集積回路のレイアウトから配線抵抗や配線容量等の回路パラメータを抽出する方法であって、
モデル配線のレイアウト上の配線幅をパラメータとして、該モデル配線と該モデル配線の周囲に存在する同層の配線との距離と、該モデル配線の抵抗値及び容量値の変化量とを表現した相関データを準備し、
実際のレイアウトから、解析配線の配線長と配線幅を抽出すると共に、該解析配線と同層で周囲に存在する配線との距離を抽出し、
抽出した前記解析配線のレイアウト配線幅をパラメータとして、前記相関データを参照することにより、前記解析配線の仕上がり抵抗値及び容量値を算出することを特徴とする回路パラメータ抽出方法。A method for extracting circuit parameters such as wiring resistance and wiring capacitance from a layout of a semiconductor integrated circuit,
Correlation expressing the distance between the model wiring and the same-layer wiring existing around the model wiring, and the amount of change in the resistance value and the capacitance value of the model wiring, using the wiring width on the layout of the model wiring as a parameter Prepare the data
From the actual layout, extract the wiring length and wiring width of the analysis wiring, and extract the distance between the analysis wiring and the wiring existing in the same layer,
A circuit parameter extraction method characterized in that a finished resistance value and a capacitance value of the analysis wiring are calculated by referring to the correlation data using the extracted layout wiring width of the analysis wiring as a parameter. 半導体集積回路のレイアウトから配線抵抗や配線容量等の回路パラメータを抽出する方法であって、
モデル配線のレイアウト上の配線幅をパラメータとして、該モデル配線の配線層のある設定領域内における配線パターンの存在割合である配線パターン面積率と、該モデル配線の抵抗値及び容量値の変化量との相関データを準備し、
実際のレイアウトから、解析配線の配線長と配線幅を抽出すると共に、該解析配線の配線層のパターン面積率を計算し、
抽出した前記解析配線のレイアウト配線幅をパラメータとして、前記相関データを参照することにより、前記解析配線の仕上がり抵抗値及び容量値を算出することを特徴とする回路パラメータ抽出方法。A method for extracting circuit parameters such as wiring resistance and wiring capacitance from a layout of a semiconductor integrated circuit,
With the wiring width on the layout of the model wiring as a parameter, the wiring pattern area ratio that is the ratio of the wiring pattern existing in the setting region where the wiring layer of the model wiring is present, and the amount of change in the resistance value and capacitance value of the model wiring Prepare correlation data for
Extract the wiring length and wiring width of the analysis wiring from the actual layout, calculate the pattern area ratio of the wiring layer of the analysis wiring,
A circuit parameter extraction method characterized in that a finished resistance value and a capacitance value of the analysis wiring are calculated by referring to the correlation data using the extracted layout wiring width of the analysis wiring as a parameter. 前記準備する前記相関データを、テーブル化もしくは近似計算式化しておく請求項１から６のいずれか一項記載の回路パラメータ抽出方法。  7. The circuit parameter extraction method according to claim 1, wherein the correlation data to be prepared is tabulated or approximated by an equation. 前記配線パターン面積率の計算を行う際に、チップ面積全体に占める配線パターンの面積率を計算する請求項２または６記載の回路パラメータ抽出方法。  The circuit parameter extraction method according to claim 2 or 6, wherein when calculating the wiring pattern area ratio, the area ratio of the wiring pattern occupying the entire chip area is calculated. 前記配線パターン面積率の計算を行う際に、回路ブロック毎に配線パターンの面積率を計算する請求項２または６記載の回路パラメータ抽出方法。  7. The circuit parameter extraction method according to claim 2, wherein when calculating the wiring pattern area ratio, the wiring pattern area ratio is calculated for each circuit block. 前記配線パターン面積率の計算を行う際に、配線加工プロセス工程が周囲に存在する配線パターンの面積率の影響を受け得る範囲内において、パターン面積率の計算を行う請求項２または６記載の回路パラメータ抽出方法。  7. The circuit according to claim 2, wherein when calculating the wiring pattern area ratio, the pattern area ratio is calculated within a range in which a wiring processing process step can be influenced by an area ratio of a wiring pattern existing around. Parameter extraction method. 最小加工寸法の１０倍の領域範囲内において、前記配線パターン面積率の計算を行う請求項１０記載の回路パラメータ抽出方法。  11. The circuit parameter extraction method according to claim 10, wherein the wiring pattern area ratio is calculated within a region range 10 times the minimum processing dimension. 請求項１から１１のいずれか一項記載の回路パラメータ抽出方法と、半導体リソグラフィ工程で使用するフォトマスクデータ生成工程におけるリソグラフィ工程に起因したレジスト仕上がり幅の変化量を補正する光近接効果補正、及びレジストのエッチング工程に起因した孤立パターンでのレジスト細りの変化量補正とを合わせて用いることを特徴とする半導体集積回路の設計方法。  The circuit parameter extraction method according to any one of claims 1 to 11, an optical proximity effect correction for correcting a change amount of a resist finish width caused by a lithography process in a photomask data generation process used in a semiconductor lithography process, and A method for designing a semiconductor integrated circuit, which is used in combination with correction of the amount of change in resist thinning in an isolated pattern caused by a resist etching process. マスクレイアウトデータを一旦参照して、請求項１から１１のいずれか一項記載の回路パラメータ抽出方法を用いて、配線仕上がり幅と配線抵抗値及び配線容量値を算出した上で、前記配線抵抗値及び配線容量値と設計時に設定した所望の配線抵抗値及び配線容量値とを比較し、
レイアウト配線幅に対して前記所望の配線抵抗値及び配線容量値に近づける補正を加えるか否かを判定し、
前記判定の結果、補正が必要である場合に、前記所望の配線抵抗値及び配線容量値に近づけるように前記レイアウト配線幅に補正を加え、
再度、前記レイアウト配線幅を補正した後の配線抵抗値及び配線容量値を用いて、半導体集積回路のタイミングシ検証ミュレーションを行うことを特徴とする半導体集積回路の設計方法。12. The wiring resistance value is calculated by referring to the mask layout data and calculating the wiring finish width, wiring resistance value, and wiring capacitance value by using the circuit parameter extraction method according to claim 1. Compare the wiring capacitance value with the desired wiring resistance value and wiring capacitance value set at the time of design,
It is determined whether or not to correct the layout wiring width to approximate the desired wiring resistance value and wiring capacitance value,
As a result of the determination, when correction is necessary, the layout wiring width is corrected so as to approach the desired wiring resistance value and wiring capacitance value,
A method of designing a semiconductor integrated circuit, wherein timing simulation verification of the semiconductor integrated circuit is performed again using the wiring resistance value and wiring capacitance value after correcting the layout wiring width. 半導体集積回路の設計方法であって、
配線の断面形状を台形形状として扱い、
リソグラフィ工程に起因したレジスト仕上がり幅の変化量を補正する光近接効果補正、およびレジストのエッチング工程に起因した孤立パターンでのレジスト細りの変化量補正を加えるレイアウト補正を行い、
前記レイアウト補正を用いた上での、モデル配線と該モデル配線の周囲に存在する同層の配線との距離と、該モデル配線の仕上がり形状の上底及び下底との第１相関データと共に、前記レイアウト補正を用いた上での、前記モデル配線の配線層の面積率と、前記モデル配線の仕上がり形状の上底及び下底の仕上がり値との第２相関データとを準備し、
実際のレイアウトから、解析配線の配線長と配線幅を抽出すると共に、該解析配線と同層で周囲に存在する配線との距離を抽出し、
前記解析配線の配線層のパターン面積率を計算し、
抽出した解析配線の前記配線長、前記配線幅、前記解析配線と同層で周囲に存在する配線との前記距離、および前記解析配線の配線層の前記パターン面積率を用いて、前記解析配線の台形形状断面における上底及び下底の変化量、前記解析配線の配線断面積、および配線抵抗値を計算し、
計算した前記解析配線抵抗値に対して、設計時に意図した所望の配線抵抗値及び配線容量値に近づける補正を加えるか否かを判定し、
前記判定の結果、補正が必要である場合に、前記所望の配線抵抗値及び配線容量値に近づけるようにレイアウト配線幅を変化させる補正を加え、
再度、前記補正を行った後の配線抵抗値及び配線容量値を用いて、半導体集積回路のタイミング検証シミュレーションを行うことを特徴とする半導体集積回路の設計方法。A method for designing a semiconductor integrated circuit, comprising:
Treat the cross-sectional shape of the wiring as a trapezoidal shape,
Performs optical proximity correction that corrects the amount of change in the resist finish width caused by the lithography process, and layout correction that adds the amount of change in resist thinning in the isolated pattern caused by the resist etching process.
Along with the first correlation data of the distance between the model wiring and the same-layer wiring existing around the model wiring, and the upper and lower bases of the finished shape of the model wiring, using the layout correction, Preparing the second correlation data of the area ratio of the wiring layer of the model wiring and the finished values of the top and bottom of the finished shape of the model wiring using the layout correction;
From the actual layout, extract the wiring length and wiring width of the analysis wiring, and extract the distance between the analysis wiring and the wiring existing in the same layer,
Calculate the pattern area ratio of the wiring layer of the analysis wiring,
Using the wiring length of the extracted analysis wiring, the wiring width, the distance between the analysis wiring and the wiring existing in the same layer, and the pattern area ratio of the wiring layer of the analysis wiring, Calculate the amount of change in the upper and lower bases in the trapezoidal cross section, the wiring cross-sectional area of the analysis wiring, and the wiring resistance value,
It is determined whether or not the calculated analysis wiring resistance value is to be corrected to approach the desired wiring resistance value and wiring capacitance value intended at the time of design,
If correction is necessary as a result of the determination, a correction is made to change the layout wiring width so as to approach the desired wiring resistance value and wiring capacitance value,
A method of designing a semiconductor integrated circuit, wherein a timing verification simulation of the semiconductor integrated circuit is performed again using the wiring resistance value and wiring capacitance value after the correction. 前記配線パターン面積率の計算を行う際に、チップ面積全体に占める配線パターンの面積率を計算する請求項１４記載の半導体集積回路の設計方法。  15. The method of designing a semiconductor integrated circuit according to claim 14, wherein when calculating the wiring pattern area ratio, the area ratio of the wiring pattern occupying the entire chip area is calculated. 前記配線パターン面積率の計算を行う際に、回路ブロック毎に配線パターンの面積率を計算する請求項１４記載の半導体集積回路の設計方法。  15. The method of designing a semiconductor integrated circuit according to claim 14, wherein, when calculating the wiring pattern area ratio, the wiring pattern area ratio is calculated for each circuit block. 前記配線パターン面積率の計算を行う際に、配線加工プロセス工程が周囲に存在する配線パターンの面積率の影響を受け得る範囲内において、パターン面積率の計算を行う請求項１４記載の半導体集積回路の設計方法。  15. The semiconductor integrated circuit according to claim 14, wherein when calculating the wiring pattern area ratio, the pattern area ratio is calculated within a range in which a wiring processing process step can be influenced by an area ratio of a wiring pattern existing around. Design method. 最小加工寸法の１０倍の領域範囲内において、前記配線パターン面積率の計算を行う請求項１７記載の半導体集積回路の設計方法。  18. The method of designing a semiconductor integrated circuit according to claim 17, wherein the wiring pattern area ratio is calculated within a region range 10 times the minimum processing dimension.
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